1 (a) There are two errors in the following register transfer notation for the fetch‑execute cycle.

1 MAR [PC]

2 PC [PC] − 1

3 MDR [MAR]

4 CIR [MDR]

Complete the following table by:

• identifying the line number of each error
• describing the error
• writing the correct statement.

Line
Description of the error Correct statement
number

PC > [PC] + 1
The next instruction is fetched not the previous one

It is data stored at the address shown at MAR that is supposed to

be copied not the contents of MAR therefore double brackets are used MDR < [[MAR]]

[4]

[Turn over
 (b) The following table shows part of the instruction set for a processor. The processor has one
general purpose register, the Accumulator (ACC), and an Index Register (IX).

Instruction
Explanation
Opcode Operand
LDM #n Immediate addressing. Load the number n to ACC
LDD <address> Direct addressing. Load the contents of the location at the given address to
ACC
STO <address> Store the contents of ACC at the given address
INC <register> Add 1 to the contents of the register (ACC or IX)
CMP <address> Compare the contents of ACC with the contents of <address>
JPN <address> Following a compare instruction, jump to <address> if the compare was False
JMP <address> Jump to the given address
IN Key in a character and store its ASCII value in ACC
OUT Output to the screen the character whose ASCII value is stored in ACC
END Return control to the operating system
XOR #n Bitwise XOR operation of the contents of ACC with the operand
XOR <address> Bitwise XOR operation of the contents of ACC with the contents of <address>
AND #n Bitwise AND operation of the contents of ACC with the operand
AND <address> Bitwise AND operation of the contents of ACC with the contents of <address>
OR #n Bitwise OR operation of the contents of ACC with the operand
OR <address> Bitwise OR operation of the contents of ACC with the contents of <address>
LSL #n Bits in ACC are shifted logically n places to the left. Zeros are introduced on
the right hand end
LSR #n Bits in ACC are shifted logically n places to the right. Zeros are introduced on
the left hand end
<address> can be an absolute or symbolic address
# denotes a denary number, e.g. #123
B denotes a binary number, e.g. B01001101

The current contents of main memory are shown:

Address Data
100 00001111
101 11110000
102 01010101
103 11111111
104 00000000
 Each row of the following table shows the current contents of ACC in binary and the instruction
that will be performed on those contents.

Complete the table by writing the new contents of the ACC after the execution of each
instruction.

Current contents of the ACC Instruction New contents of the ACC

11111111 OR 101 11111111

00000000 XOR #15 00001111

10101010 LSR #2 00101010

01010101 AND 104 00000000

[4]

[Turn over
2 The following diagram shows four register notations and seven descriptions.

Draw one line from each register notation to its most appropriate description.

Register notation Description

Holds the op code and operand of an

MDR instruction ready for it to be decoded

Holds the address of the next instruction to

be read

Holds flags that are set when the Arithmetic

CIR and Logic Unit (ALU) executes instructions

Holds data read from, or to be written to,

memory

MAR Holds the current value in the Index Register

Holds the address where data is to be

written to or read from

PC Holds the result of the last instruction

executed by the ALU
[4]

[Turn over
3 The table shows part of the instruction set for a processor. The processor has one general purpose
register, the Accumulator (ACC), and an Index Register (IX).

Instruction
Explanation
Op code Operand
Direct addressing. Load the contents of the location at the
LDD <address>
given address to ACC.
Indirect addressing. The address to be used is at the given
LDI <address>
address. Load the contents of this second address to ACC.
STO <address> Store the contents of ACC at the given address.

ADD <address> Add the contents of the given address to ACC.

INC <register> Add 1 to the contents of the register (ACC or IX).

JMP <address> Jump to the given address.

Compare the contents of ACC with the contents of
CMP <address>
<address>.
Following a compare instruction, jump to <address> if the
JPE <address>
compare was True.
END Return control to the operating system.

The current contents of the main memory are:

Address Instruction
50 LDI 103
51 CMP 101
52 JPE 59
53 ADD 102
54 STO 102
55 LDD 100
56 INC ACC
57 STO 100
58 JMP 51
59 ADD 102
60 STO 102
61 END

100 1
101 3
102 0
103 100
(a) Trace the program currently in memory using the following trace table.

Memory address
Instruction
ACC
address 100 101 102 103

50 1 1 3 0 100

51

52

53 1

54 1

55 2

56
3

57
3

51

52

59 4

60 4

61

[5]

[Turn over
(b) The instruction in memory address 50 needs to be changed to use direct addressing to load
the contents of the memory location at address 100.

Give the new instruction to replace LDI 103.

LDD 100
............................................................................................................................................. [1]

(c) Each instruction in the assembly language program is encoded in 16 bits (8-bit op code
followed by an 8-bit operand).

(i) The instruction JPE 59 has the operand 59.

Convert the operand 59 into 8-bit binary.

1 1 1 0 1 1

[1]
128 64 32 16 4 2 1
8

(ii) Convert the denary value 59 into hexadecimal.

.....................................................................................................................................
3A [1]

(d) The assembly language program uses direct and indirect addressing.

Identify two other modes of addressing used in an assembly language program.

1 ................................................................................................................................................
intermediate

2 ................................................................................................................................................
register
[2]
4 The table shows part of the instruction set for a processor. The processor has one general purpose
register, the Accumulator (ACC), and an Index Register (IX).

Instruction
Explanation
Op code Operand
LDD <address> Direct addressing. Load the content of the location at the given
address to ACC.
LDI <address> Indirect addressing. The address to be used is at the given
address. Load the contents of this second address to ACC.
DEC <register> Subtract 1 from the contents of the register (ACC or IX).
CMP <address> Compare the contents of ACC with the contents of <address>.
JMP <address> Jump to the given address.
JPE <address> Following a compare instruction, jump to <address> if the
compare was True.
STO <address> Store the contents of ACC at the given address.
END Return control to the operating system.

The current contents of the main memory are:

Address Instruction
100 LDD 200
101 CMP 201
102 JPE 106
103 DEC ACC
104 STO 200
105 JMP 101
106 END

200 2
201 0
202 200
(a) Trace the program currently in memory using the following trace table.

Memory address
Instruction
ACC
address
200 201 202

100 2 2 0 200

101

102

103 1

104 3

105

101

102

103 0

104 4

105

101

102

106

[3]

(b) The instruction in memory address 100 needs to be changed. It needs to use indirect
addressing to load the contents of memory address 200.

Give the new instruction to replace LDD 200.

LDI 200
............................................................................................................................................. [1]
[Turn over
(c) Each instruction in the assembly language program is encoded in 16 bits (8-bit op code
followed by an 8-bit operand).

(i) The instruction CMP 201 has the operand 201.

Convert the operand 201 into 8-bit binary.

1 1 0 1 0 1 1
1
[1]

(ii) State the maximum number of op codes that can be represented using eight bits.
255
..................................................................................................................................... [1]

(d) The status register contains condition flags.

Identify three condition flags that can be set in the status register.
carry
1 ................................................................................................................................................

2 ................................................................................................................................................
zero

sign
3 ................................................................................................................................................
[3]