VLSI

INTERVIEW
PREPARATION
UART PROTOCOL
4 Power Packed Sections

By ProV Logic
UART COMMUNICATION
UART Transmitter
01 UART Receiver
UART Frame format

BAUD RATE GENERATOR

UART Baud rate Calculation
02 Frequency & Divisor
Calculation
Interview Questions

INTERVIEW PREPARATION
03 Theory examples on UART
Coding analysis of UART
Interview Questions
 UART COMMUNICATION
UART stands for Universal Asynchronous Receiver/Transmitter.
It’s not a communication protocol like SPI and I2C, but a physical
circuit in a microcontroller, or a stand-alone IC.
A UART’s main purpose is to transmit and receive serial data.

INTRODUCTION
In UART communication, two UARTs communicate directly with each
other.
The transmitting UART converts parallel data from a controlling
device like a CPU into serial form, transmits it in serial to the
receiving UART, which then converts the serial data back into parallel
data for the receiving device.
Only two wires are needed to transmit data between two UARTs.
Data flows from the Tx pin of the transmitting UART to the Rx pin
of the receiving UART:

UARTs transmit data asynchronously, which means there is no clock

signal to synchronize the output of bits from the transmitting UART
to the sampling of bits by the receiving UART.
Instead of a clock signal, the transmitting UART adds start and stop
bits to the data packet being transferred.
These bits define the beginning and end of the data packet so the
receiving UART knows when to start reading the bits.
 When the receiving UART detects a start bit, it starts to read the
incoming bits at a specific frequency known as the baud rate.
Baud rate is a measure of the speed of data transfer, expressed in
bits per second (bps).
Both UARTs must operate at about the same baud rate.
The baud rate between the transmitting and receiving UARTs can
only differ by about 10% before the timing of bits gets too far off.

WORKING OF UART
The UART that is going to transmit data receives the data from a
data bus.
The data bus is used to send data to the UART by another device
like a CPU, memory, or microcontroller.
Data is transferred from the data bus to the transmitting UART in
parallel form.
After the transmitting UART gets the parallel data from the data
bus, it adds a start bit, a parity bit, and a stop bit, creating the
data packet.
Next, the data packet is output serially, bit by bit at the Tx pin.
The receiving UART reads the data packet bit by bit at its Rx pin.
The receiving UART then converts the data back into parallel form
and removes the start bit, parity bit, and stop bits.
Finally, the receiving UART transfers the data packet in parallel to
the data bus on the receiving end:
UART PACKET
UART transmitted data is organized into packets.
Each packet contains 1 start bit, 5 to 9 data bits (depending on the
UART), an optional parity bit, and 1 or 2 stop bits:

START BIT
The UART data transmission line is normally held at a high voltage
level when it’s not transmitting data.
To start the transfer of data, the transmitting UART pulls the
transmission line from high to low for one clock cycle.
When the receiving UART detects the high to low voltage transition,
it begins reading the bits in the data frame at the frequency of the
baud rate.

DATA FRAME
The data frame contains the actual data being transferred.
It can be 5 bits up to 8 bits long if a parity bit is used.
If no parity bit is used, the data frame can be 9 bits long.
In most cases, the data is sent with the least significant bit first.
PARITY
Parity describes the evenness or oddness of a number.
The parity bit is a way for the receiving UART to tell if any data
has changed during transmission.
Bits can be changed by electromagnetic radiation, mismatched
baud rates, or long distance data transfers.
After the receiving UART reads the data frame, it counts the
number of bits with a value of 1 and checks if the total is an even
or odd number.
If the parity bit is a 0 (even parity), the 1 bits in the data frame
should total to an even number.
If the parity bit is a 1 (odd parity), the 1 bits in the data frame
should total to an odd number.
When the parity bit matches the data, the UART knows that the
transmission was free of errors.
But if the parity bit is a 0, and the total is odd; or the parity bit is
a 1, and the total is even, the UART knows that bits in the data
frame have changed.

STOP BIT
To signal the end of the data packet, the sending UART drives the
data transmission line from a low voltage to a high voltage for at
least two bit durations.
STEPS OF UART TRANSMISSION
STEP 1
The transmitting UART receives data in parallel from the data bus:

STEP 2
The transmitting UART adds the start bit, parity bit, and the stop
bit(s) to the data frame:
STEP 3
The entire packet is sent serially from the transmitting UART to the
receiving UART.
The receiving UART samples the data line at the pre-configured
baud rate:

STEP 4
The receiving UART discards the start bit, parity bit, and stop bit
from the data frame:
STEP 5
The receiving UART converts the serial data back into parallel and
transfers it to the data bus on the receiving end:

ADVANTAGES OF UART
Only uses two wires
No clock signal is necessary
Has a parity bit to allow for error checking
The structure of the data packet can be changed as long as both
sides are set up for it
Well documented and widely used method
1. Design a UART transceiver that dynamically adapts to
unknown baud rates without prior configuration.
A Universal Asynchronous Receiver-Transmitter (UART) transceiver is
a fundamental communication module used in embedded systems
and digital circuits.
In most traditional UART implementations, the baud rate is
predetermined and manually set in both the transmitter and
receiver.
However, designing a UART transceiver that can dynamically adapt
to an unknown baud rate requires real-time estimation and
synchronization with the incoming signal.

BAUD RATE DETECTOR MODULE

module baud_rate_detector (
input wire clk, // System clock
input wire rx, // UART RX line
output reg [15:0] baud // Detected baud rate
);
reg [15:0] counter;
reg last_rx;
always @(posedge clk) begin
if (last_rx == 1 && rx == 0) // Detect start bit (falling edge)
counter <= 0;
else
counter <= counter + 1;
if (last_rx == 0 && rx == 1) // First data bit transition
baud <= counter;
last_rx <= rx;
end
endmodule
RECEIVER MODULE
module uart_rx (
input wire clk,
input wire rx,
input wire [15:0] baud,
output reg [7:0] data,
output reg valid
);
reg [3:0] bit_count;
reg [15:0] bit_timer;
reg [7:0] shift_reg;

always @(posedge clk) begin

if (bit_timer == baud >> 1) begin // Sample at middle of bit
shift_reg <= {rx, shift_reg[7:1]};
bit_count <= bit_count + 1;
end
bit_timer <= bit_timer + 1;

if (bit_count == 8) begin
data <= shift_reg;
valid <= 1;
end else begin
valid <= 0;
end
end
endmodule
TRANSMITTER MODULE
module uart_tx (
input wire clk,
input wire start,
input wire [7:0] data,
input wire [15:0] baud,
output reg tx
);
reg [3:0] bit_count;
reg [15:0] bit_timer;
reg [9:0] shift_reg;

always @(posedge clk) begin

if (start) begin
shift_reg <= {1'b1, data, 1'b0}; // Start bit, data, stop bit
bit_count <= 0;
end

if (bit_timer == baud) begin

tx <= shift_reg[0];
shift_reg <= shift_reg >> 1;
bit_count <= bit_count + 1;
bit_timer <= 0;
end else begin
bit_timer <= bit_timer + 1;
end
end
endmodule
TOP LEVEL UART MODULE
module uart_dynamic (
input wire clk,
input wire rx,
input wire tx_start,
input wire [7:0] tx_data,
output wire tx,
output wire [7:0] rx_data,
output wire rx_valid
);
wire [15:0] baud_rate;
baud_rate_detector baud_det (
.clk(clk),
.rx(rx),
.baud(baud_rate)
);
uart_rx receiver (
.clk(clk),
.rx(rx),
.baud(baud_rate),
.data(rx_data),
.valid(rx_valid)
);
uart_tx transmitter (
.clk(clk),
.start(tx_start),
.data(tx_data),
.baud(baud_rate),
.tx(tx)
);
endmodule
2. Implement a multi-channel UART with independent baud
rates and data framing per channel.
A multi-channel UART allows multiple serial communication channels
to operate independently. Each channel has:
A separate baud rate.
Independent data framing (start, stop, parity, and data bits).
Independent transmission and reception mechanisms.

BAUD RATE DETECTOR MODULE (PER CHANNEL)

module baud_generator (
input wire clk, // System clock
input wire [15:0] baud_div, // Baud rate divisor
output reg baud_tick // Baud clock pulse
);
reg [15:0] counter;

always @(posedge clk) begin

if (counter >= baud_div) begin
counter <= 0;
baud_tick <= 1;
end else begin
counter <= counter + 1;
baud_tick <= 0;
end
end
endmodule
MULTI CHANNEL UART RECEIVER MODULE
module uart_rx (
input wire clk,
input wire baud_tick,
input wire rx,
input wire [2:0] data_bits, // 5, 6, 7, or 8 bits
input wire stop_bits, // 1 or 2 stop bits
input wire parity_en, // Enable parity
input wire parity_type, // 0 = Even, 1 = Odd
output reg [7:0] data_out,
output reg valid
);
reg [3:0] bit_count;
reg [7:0] shift_reg;
reg parity_check;
reg [1:0] stop_count;

always @(posedge clk) begin

if (baud_tick) begin
if (bit_count == 0 && rx == 0) begin // Start bit detected
bit_count <= 1;
end else if (bit_count > 0) begin
shift_reg <= {rx, shift_reg[7:1]};
bit_count <= bit_count + 1;

if (bit_count == data_bits) begin

if (parity_en) begin
parity_check <= ^shift_reg ^ parity_type;
end else begin
parity_check <= 0;
end
end
 if (bit_count == data_bits + parity_en) begin
stop_count <= 0;
end

if (bit_count >= data_bits + parity_en && stop_count <

stop_bits) begin
stop_count <= stop_count + 1;
if (stop_count == stop_bits - 1) begin
data_out <= shift_reg;
valid <= (parity_en) ? (parity_check == 0) : 1;
bit_count <= 0;
end
end
end
end
end
endmodule

MULTI-CHANNEL UART TRANSMITTER MODULE

module uart_tx (
input wire clk,
input wire baud_tick,
input wire start,
input wire [7:0] data_in,
input wire [2:0] data_bits,
input wire stop_bits,
input wire parity_en,
input wire parity_type,
output reg tx
);
 reg [3:0] bit_count;
reg [9:0] shift_reg;

always @(posedge clk) begin

if (start) begin
shift_reg <= {1'b1, data_in, parity_en ? (^data_in ^ parity_type)
: 1'b0, {stop_bits{1'b1}}};
bit_count <= 0;
end

if (baud_tick) begin
tx <= shift_reg[0];
shift_reg <= shift_reg >> 1;
bit_count <= bit_count + 1;

if (bit_count == data_bits + parity_en + stop_bits + 1) begin

bit_count <= 0;
end
end
end
endmodule
TOP-LEVEL MULTI-CHANNEL UART
module multi_channel_uart #(
parameter NUM_CHANNELS = 4
)(
input wire clk,
input wire [NUM_CHANNELS-1:0] rx,
input wire [NUM_CHANNELS-1:0] tx_start,
input wire [7:0] tx_data [NUM_CHANNELS-1:0],
input wire [15:0] baud_div [NUM_CHANNELS-1:0],
input wire [2:0] data_bits [NUM_CHANNELS-1:0],
input wire stop_bits [NUM_CHANNELS-1:0],
input wire parity_en [NUM_CHANNELS-1:0],
input wire parity_type [NUM_CHANNELS-1:0],
output wire [NUM_CHANNELS-1:0] tx,
output wire [7:0] rx_data [NUM_CHANNELS-1:0],
output wire [NUM_CHANNELS-1:0] rx_valid
);
genvar i;
generate
for (i = 0; i < NUM_CHANNELS; i = i + 1) begin : uart_channels
wire baud_tick;

baud_generator baud_inst (
.clk(clk),
.baud_div(baud_div[i]),
.baud_tick(baud_tick)
);
 uart_rx rx_inst (
.clk(clk),
.baud_tick(baud_tick),
.rx(rx[i]),
.data_bits(data_bits[i]),
.stop_bits(stop_bits[i]),
.parity_en(parity_en[i]),
.parity_type(parity_type[i]),
.data_out(rx_data[i]),
.valid(rx_valid[i])
);

uart_tx tx_inst (
.clk(clk),
.baud_tick(baud_tick),
.start(tx_start[i]),
.data_in(tx_data[i]),
.data_bits(data_bits[i]),
.stop_bits(stop_bits[i]),
.parity_en(parity_en[i]),
.parity_type(parity_type[i]),
.tx(tx[i])
);
end
endgenerate
endmodule
3. Create a UART-based error correction system that detects
and corrects single-bit errors without retransmission
This system ensures that data transmission over UART is error-
resilient by detecting and correcting single-bit errors without
retransmission.
The approach is based on Hamming Code (SEC), which adds
redundant parity bits to enable error correction at the receiver.

HAMMING ENCODER
module uart_hamming_encoder (
input wire [7:0] data_in,
output wire [11:0] encoded_out
);
wire p1, p2, p3, p4;

assign p1 = data_in[0] ^ data_in[1] ^ data_in[3] ^ data_in[4] ^

data_in[6];
assign p2 = data_in[0] ^ data_in[2] ^ data_in[3] ^ data_in[5] ^
data_in[6];
assign p3 = data_in[1] ^ data_in[2] ^ data_in[3] ^ data_in[7];
assign p4 = data_in[4] ^ data_in[5] ^ data_in[6] ^ data_in[7];

assign encoded_out = {data_in[7], data_in[6], data_in[5], p4,

data_in[4], data_in[3], data_in[2], p3, data_in[1], data_in[0], p2, p1};
endmodule
HAMMING DECODER WITH ERROR CORRECTION
module uart_hamming_decoder (
input wire [11:0] encoded_in,
output reg [7:0] data_out,
output reg error_detected,
output reg error_corrected
);
wire p1, p2, p3, p4;
wire s1, s2, s3, s4;
reg [3:0] error_pos;
reg [11:0] corrected_data;

assign p1 = encoded_in[0];
assign p2 = encoded_in[1];
assign p3 = encoded_in[3];
assign p4 = encoded_in[7];

assign s1 = p1 ^ encoded_in[2] ^ encoded_in[4] ^ encoded_in[6] ^

encoded_in[8] ^ encoded_in[10];
assign s2 = p2 ^ encoded_in[2] ^ encoded_in[5] ^ encoded_in[6] ^
encoded_in[9] ^ encoded_in[10];
assign s3 = p3 ^ encoded_in[4] ^ encoded_in[5] ^ encoded_in[6] ^
encoded_in[11];
assign s4 = p4 ^ encoded_in[8] ^ encoded_in[9] ^ encoded_in[10] ^
encoded_in[11];

always @(*) begin

error_pos = {s4, s3, s2, s1};
corrected_data = encoded_in;
error_detected = |error_pos;
error_corrected = 0;
 if (error_detected) begin
corrected_data[error_pos - 1] = ~corrected_data[error_pos - 1];
error_corrected = 1;
end

data_out = {corrected_data[11], corrected_data[10],

corrected_data[9], corrected_data[6], corrected_data[5],
corrected_data[4], corrected_data[2], corrected_data[1]};
end
endmodule

UART TX WITH HAMMING ENCODING

module uart_tx (
input wire clk,
input wire baud_tick,
input wire start,
input wire [7:0] data_in,
output reg tx
);
reg [11:0] encoded_data;
reg [3:0] bit_count;

wire [11:0] encoded_out;

uart_hamming_encoder encoder_inst (
.data_in(data_in),
.encoded_out(encoded_out)
);
 always @(posedge clk) begin
if (start) begin
encoded_data <= encoded_out;
bit_count <= 0;
end

if (baud_tick) begin
tx <= encoded_data[bit_count];
bit_count <= bit_count + 1;
end
end
endmodule

UART RX WITH HAMMING DECODING

module uart_rx (
input wire clk,
input wire baud_tick,
input wire rx,
output reg [7:0] data_out,
output reg valid,
output reg error_detected,
output reg error_corrected
);
reg [11:0] received_data;
reg [3:0] bit_count;

wire [7:0] corrected_data;

wire err_detect, err_correct;
 uart_hamming_decoder decoder_inst (
.encoded_in(received_data),
.data_out(corrected_data),
.error_detected(err_detect),
.error_corrected(err_correct)
);

always @(posedge clk) begin

if (baud_tick) begin
received_data[bit_count] <= rx;
bit_count <= bit_count + 1;

if (bit_count == 11) begin

data_out <= corrected_data;
error_detected <= err_detect;
error_corrected <= err_correct;
valid <= 1;
end
end
end
endmodule
TOP-LEVEL UART ERROR CORRECTION SYSTEM
module uart_error_correction_system (
input wire clk,
input wire baud_tick,
input wire start_tx,
input wire [7:0] data_in,
input wire rx,
output wire tx,
output wire [7:0] data_out,
output wire valid,
output wire error_detected,
output wire error_corrected
);
uart_tx tx_module (
.clk(clk),
.baud_tick(baud_tick),
.start(start_tx),
.data_in(data_in),
.tx(tx)
);

uart_rx rx_module (
.clk(clk),
.baud_tick(baud_tick),
.rx(rx),
.data_out(data_out),
.valid(valid),
.error_detected(error_detected),
.error_corrected(error_corrected)
);
endmodule
4. Develop a power-efficient UART module that automatically
enters a low-power state when idle.
This UART module is designed to automatically enter a low-power
state when idle, reducing power consumption in embedded systems
and FPGA designs.
It utilizes clock gating and dynamic power management to achieve
this.

POWER MANAGEMENT UNIT (PMU)

module uart_pmu (
input wire clk,
input wire reset,
input wire uart_active, // High when TX or RX is active
output reg clk_enable // Controls clock gating
);
reg [15:0] idle_counter;

always @(posedge clk or posedge reset) begin

if (reset) begin
clk_enable <= 1; // Enable clock at reset
idle_counter <= 0;
end else if (uart_active) begin
clk_enable <= 1; // Keep clock enabled if UART is active
idle_counter <= 0;
end else begin
idle_counter <= idle_counter + 1;
if (idle_counter > 50000) // Idle threshold for power saving
clk_enable <= 0; // Disable clock when idle
end
end
endmodule
BAUD RATE GENERATOR WITH CLOCK GATING
module baud_generator (
input wire clk,
input wire clk_enable, // Clock gating control
input wire reset,
output reg baud_tick
);
reg [15:0] counter;

always @(posedge clk or posedge reset) begin

if (reset) begin
counter <= 0;
baud_tick <= 0;
end else if (clk_enable) begin
counter <= counter + 1;
if (counter >= 5208) begin // Example: 9600 baud at 50 MHz
counter <= 0;
baud_tick <= 1;
end else
baud_tick <= 0;
end
end
endmodule

POWER-EFFICIENT UART TRANSMITTER

module uart_tx (
input wire clk,
input wire reset,
input wire baud_tick,
input wire start_tx,
input wire [7:0] data_in,
output reg tx,
output reg uart_active
);
 reg [3:0] bit_count;
reg [9:0] shift_reg;
reg transmitting;

always @(posedge clk or posedge reset) begin

if (reset) begin
tx <= 1;
bit_count <= 0;
transmitting <= 0;
uart_active <= 0;
end else if (start_tx) begin
shift_reg <= {1'b1, data_in, 1'b0}; // Start bit, 8 data bits, Stop bit
bit_count <= 0;
transmitting <= 1;
uart_active <= 1;
end else if (baud_tick && transmitting) begin
tx <= shift_reg[0];
shift_reg <= shift_reg >> 1;
bit_count <= bit_count + 1;

if (bit_count == 9) begin
transmitting <= 0;
uart_active <= 0;
end
end
end
endmodule
POWER-EFFICIENT UART RECEIVER
module uart_rx (
input wire clk,
input wire reset,
input wire baud_tick,
input wire rx,
output reg [7:0] data_out,
output reg valid,
output reg uart_active
);
reg [3:0] bit_count;
reg [9:0] shift_reg;
reg receiving;

always @(posedge clk or posedge reset) begin

if (reset) begin
bit_count <= 0;
receiving <= 0;
valid <= 0;
uart_active <= 0;
end else if (!rx && !receiving) begin // Detect start bit
receiving <= 1;
bit_count <= 0;
uart_active <= 1;
end else if (baud_tick && receiving) begin
shift_reg[9:1] <= shift_reg[8:0];
shift_reg[0] <= rx;
bit_count <= bit_count + 1;

if (bit_count == 9) begin
data_out <= shift_reg[8:1]; // Extract 8-bit data
valid <= 1;
 receiving <= 0;
uart_active <= 0;
end
end
end
endmodule
TOP-LEVEL UART WITH LOW-POWER MANAGEMENT
module power_efficient_uart (
input wire clk,
input wire reset,
input wire start_tx,
input wire [7:0] data_in,
input wire rx,
output wire tx,
output wire [7:0] data_out,
output wire valid
);
wire baud_tick;
wire clk_enable;
wire uart_active_tx, uart_active_rx;

uart_pmu pmu (
.clk(clk),
.reset(reset),
.uart_active(uart_active_tx | uart_active_rx),
.clk_enable(clk_enable)
);
 baud_generator baud_gen (
.clk(clk),
.clk_enable(clk_enable),
.reset(reset),
.baud_tick(baud_tick)
);

uart_tx tx_module (
.clk(clk),
.reset(reset),
.baud_tick(baud_tick),
.start_tx(start_tx),
.data_in(data_in),
.tx(tx),
.uart_active(uart_active_tx)
);

uart_rx rx_module (
.clk(clk),
.reset(reset),
.baud_tick(baud_tick),
.rx(rx),
.data_out(data_out),
.valid(valid),
.uart_active(uart_active_rx)
);
endmodule
5. Design a UART bridge that converts asynchronous UART
data into synchronous SPI data.
This UART bridge converts asynchronous UART data into
synchronous SPI data, allowing communication between devices
using different protocols.

UART RECEIVER
module uart_rx (
input wire clk,
input wire reset,
input wire baud_tick,
input wire rx,
output reg [7:0] data_out,
output reg valid
);
reg [3:0] bit_count;
reg [9:0] shift_reg;
reg receiving;

always @(posedge clk or posedge reset) begin

if (reset) begin
bit_count <= 0;
receiving <= 0;
valid <= 0;
end else if (!rx && !receiving) begin // Start bit detected
receiving <= 1;
bit_count <= 0;
end else if (baud_tick && receiving) begin
shift_reg[9:1] <= shift_reg[8:0];
shift_reg[0] <= rx;
bit_count <= bit_count + 1;
 if (bit_count == 9) begin // Full byte received
data_out <= shift_reg[8:1]; // Extract 8-bit data
valid <= 1;
receiving <= 0;
end
end else begin
valid <= 0;
end
end
endmodule

FIFO BUFFER
module fifo (
input wire clk,
input wire reset,
input wire wr_en,
input wire rd_en,
input wire [7:0] data_in,
output reg [7:0] data_out,
output reg empty,
output reg full
);
reg [7:0] memory [7:0]; // 8-byte FIFO
reg [2:0] rd_ptr, wr_ptr;
reg [3:0] count;

always @(posedge clk or posedge reset) begin

if (reset) begin
rd_ptr <= 0;
wr_ptr <= 0;
count <= 0;
 empty <= 1;
full <= 0;
end else begin
if (wr_en && !full) begin
memory[wr_ptr] <= data_in;
wr_ptr <= wr_ptr + 1;
count <= count + 1;
end

if (rd_en && !empty) begin

data_out <= memory[rd_ptr];
rd_ptr <= rd_ptr + 1;
count <= count - 1;
end

empty <= (count == 0);

full <= (count == 8);
end
end
endmodule
SPI MASTER
module spi_master (
input wire clk,
input wire reset,
input wire start,
input wire [7:0] data_in,
output reg miso,
output reg sclk,
output reg mosi,
output reg cs,
output reg done
);
 reg [7:0] shift_reg;
reg [2:0] bit_count;
reg transmitting;

always @(posedge clk or posedge reset) begin

if (reset) begin
shift_reg <= 0;
bit_count <= 0;
sclk <= 1;
cs <= 1;
done <= 0;
transmitting <= 0;
end else if (start) begin
shift_reg <= data_in;
bit_count <= 0;
transmitting <= 1;
cs <= 0;
end else if (transmitting) begin
sclk <= ~sclk;
if (!sclk) begin
mosi <= shift_reg[7];
shift_reg <= {shift_reg[6:0], 1'b0};
bit_count <= bit_count + 1;
end
if (bit_count == 7) begin
transmitting <= 0;
done <= 1;
cs <= 1;
end
end
end
endmodule
CONTROL UNIT
module uart_to_spi_bridge (
input wire clk,
input wire reset,
input wire baud_tick,
input wire uart_rx,
output wire spi_miso,
output wire spi_mosi,
output wire spi_sclk,
output wire spi_cs
);
wire [7:0] uart_data;
wire valid, fifo_full, fifo_empty;
wire [7:0] fifo_data;
wire spi_done;
uart_rx rx_module (
.clk(clk),
.reset(reset),
.baud_tick(baud_tick),
.rx(uart_rx),
.data_out(uart_data),
.valid(valid)
);
fifo buffer (
.clk(clk),
.reset(reset),
.wr_en(valid),
.rd_en(spi_done),
.data_in(uart_data),
.data_out(fifo_data),
.empty(fifo_empty),
.full(fifo_full)
);
 spi_master spi (
.clk(clk),
.reset(reset),
.start(!fifo_empty),
.data_in(fifo_data),
.miso(spi_miso),
.sclk(spi_sclk),
.mosi(spi_mosi),
.cs(spi_cs),
.done(spi_done)
);
endmodule
6. Implement a hardware-accelerated UART packetizing
system for handling large data streams.
This system efficiently packetizes large UART data streams using
hardware acceleration for low-latency, high-speed communication.
It segments the data into packets with headers, CRC checks, and
synchronization fields.

UART RECEIVER
module uart_rx (
input wire clk,
input wire reset,
input wire baud_tick,
input wire rx,
output reg [7:0] data_out,
output reg valid
);
reg [3:0] bit_count;
reg [9:0] shift_reg;
reg receiving;
 always @(posedge clk or posedge reset) begin
if (reset) begin
bit_count <= 0;
receiving <= 0;
valid <= 0;
end else if (!rx && !receiving) begin // Start bit detected
receiving <= 1;
bit_count <= 0;
end else if (baud_tick && receiving) begin
shift_reg[9:1] <= shift_reg[8:0];
shift_reg[0] <= rx;
bit_count <= bit_count + 1;

if (bit_count == 9) begin // Full byte received

data_out <= shift_reg[8:1]; // Extract 8-bit data
valid <= 1;
receiving <= 0;
end
end else begin
valid <= 0;
end
end
endmodule
FIFO BUFFER
module fifo (
input wire clk,
input wire reset,
input wire wr_en,
input wire rd_en,
input wire [7:0] data_in,
output reg [7:0] data_out,
output reg empty,
output reg full
);
reg [7:0] memory [15:0]; // 16-byte FIFO
reg [3:0] rd_ptr, wr_ptr;
reg [4:0] count;
always @(posedge clk or posedge reset) begin
if (reset) begin
rd_ptr <= 0;
wr_ptr <= 0;
count <= 0;
empty <= 1;
full <= 0;
end else begin
if (wr_en && !full) begin
memory[wr_ptr] <= data_in;
wr_ptr <= wr_ptr + 1;
count <= count + 1;
end

if (rd_en && !empty) begin

data_out <= memory[rd_ptr];
rd_ptr <= rd_ptr + 1;
count <= count - 1;
end
 empty <= (count == 0);
full <= (count == 16);
end
end
endmodule

CRC GENERATOR
module crc16 (
input wire clk,
input wire reset,
input wire enable,
input wire [7:0] data_in,
output reg [15:0] crc_out
);
reg [15:0] crc;

always @(posedge clk or posedge reset) begin

if (reset) begin
crc <= 16'hFFFF;
end else if (enable) begin
crc <= (crc >> 8) ^ (data_in ^ crc);
end
end

assign crc_out = crc;

endmodule
PACKETIZER
module packetizer (
input wire clk,
input wire reset,
input wire start,
input wire [7:0] data_in,
input wire fifo_empty,
output reg [7:0] packet_out,
output reg packet_valid
);
reg [3:0] state;
reg [7:0] packet_mem [3:0];
reg [7:0] index;
always @(posedge clk or posedge reset) begin
if (reset) begin
state <= 0;
packet_valid <= 0;
end else if (start && !fifo_empty) begin
case (state)
0: begin
packet_mem[0] <= 8'h7E; // Sync Byte
state <= 1;
end
1: begin
packet_mem[1] <= data_in; // Header
state <= 2;
end
2: begin
packet_mem[2] <= data_in; // Payload
state <= 3;
end
 3: begin
packet_mem[3] <= 8'hAA; // CRC Placeholder
packet_valid <= 1;
state <= 0;
end
endcase
end else begin
packet_valid <= 0;
end
end

assign packet_out = packet_mem[index];

endmodule

UART TRANSMITTER
module uart_tx (
input wire clk,
input wire reset,
input wire baud_tick,
input wire [7:0] data_in,
input wire valid,
output reg tx,
output reg ready
);
reg [3:0] bit_count;
reg [9:0] shift_reg;
reg sending;
 always @(posedge clk or posedge reset) begin
if (reset) begin
bit_count <= 0;
sending <= 0;
tx <= 1;
ready <= 1;
end else if (valid && !sending) begin
shift_reg <= {1'b1, data_in, 1'b0};
bit_count <= 0;
sending <= 1;
ready <= 0;
end else if (baud_tick && sending) begin
tx <= shift_reg[0];
shift_reg <= shift_reg >> 1;
bit_count <= bit_count + 1;

if (bit_count == 9) begin
sending <= 0;
ready <= 1;
end
end
end
endmodule
TOP-LEVEL SYSTEM
module uart_packetizer_system (
input wire clk,
input wire reset,
input wire uart_rx,
output wire uart_tx
);
wire [7:0] uart_data, fifo_data, packet_data;
wire uart_valid, fifo_full, fifo_empty, packet_valid;

uart_rx receiver (
.clk(clk),
.reset(reset),
.baud_tick(1'b1),
.rx(uart_rx),
.data_out(uart_data),
.valid(uart_valid)
);

fifo buffer (
.clk(clk),
.reset(reset),
.wr_en(uart_valid),
.rd_en(packet_valid),
.data_in(uart_data),
.data_out(fifo_data),
.empty(fifo_empty),
.full(fifo_full)
);
 packetizer pkt (
.clk(clk),
.reset(reset),
.start(!fifo_empty),
.data_in(fifo_data),
.fifo_empty(fifo_empty),
.packet_out(packet_data),
.packet_valid(packet_valid)
);

uart_tx transmitter (
.clk(clk),
.reset(reset),
.baud_tick(1'b1),
.data_in(packet_data),
.valid(packet_valid),
.tx(uart_tx)
);
endmodule
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