Half Adder and Full Adder

✓ An Adder is a digital circuit used to perform binary addition.

✓ It is a fundamental component of arithmetic logic units (ALUs) in microprocessors.
Half Adder
A Half Adder is a combinational circuit that adds two single-bit binary numbers (A and B) and
produces two outputs:
• Sum (S) – The result of binary addition.
• Carry (C) – The carry output for the next stage in multi-bit addition.
Half Adder Circuit Diagram

HALF
ADDER

Half Adder Truth Table

A B Sum (S) Carry (C)

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Half Adder Boolean Equations

• Sum: S=A⊕B (XOR Gate)
• Carry: C=A⋅B (AND Gate)
Limitations of Half Adder
✓ Cannot handle carry input from a previous addition (not suitable for multi-bit addition).
✓ Only works for adding two single-bit numbers.

Full Adder
A Full Adder is an improved version of a half adder that adds three binary inputs:
• A (First bit)
• B (Second bit)
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 • Cin (Carry from previous addition)
It produces two outputs:
• Sum (S)
• Carry Out (Cout)
Full Adder Circuit Diagram

FULL
ADDER

Full Adder Truth Table

A B Cin Sum (S) Carry Out (Cout)

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Full Adder Boolean Equations
• Sum: S=A⊕B⊕Cin
• Carry Out: Cout=(A⋅B)+(Cin⋅(A⊕B))
Advantages of Full Adder

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 ✓ Handles carry input, making it useful for multi-bit addition.
✓ Used in arithmetic logic units (ALUs) and microprocessors.
Half Adder vs Full Adder

Feature Half Adder Full Adder

Inputs 2 (A, B) 3 (A, B, Cin)
Outputs 2 (Sum, Carry) 2 (Sum, Carry Out)
Carry Input No Yes
Logic Gates Used XOR, AND XOR, AND, OR
Application Simple binary addition Multi-bit binary addition

Sequential Circuit in Digital Electronics

A sequential circuit is a type of digital circuit whose output depends not only on the present inputs but
also on the past inputs (history or previous state). This makes sequential circuits different from
combinational circuits, which depend only on current inputs.
1. Characteristics of Sequential Circuits
• Memory Element: Stores previous state information.
• Clock Signal: Synchronizes changes in output.
• Feedback Path: Uses past outputs as future inputs.
• State Transition: Moves from one state to another based on inputs and previous state.
2. Types of Sequential Circuits
Sequential circuits are classified into two main types based on clock dependency:
(A) Asynchronous Sequential Circuit
• Works without a clock.
• Changes state immediately when inputs change.
• Faster but more prone to glitches.
• Example: SR Latch using NAND/NOR gates.
(B) Synchronous Sequential Circuit
• Works with a clock pulse.
• State changes occur only at specific clock edges (rising or falling edge).
• More stable and widely used.
• Example: Flip-Flops, Counters, Shift Registers, Finite State Machines (FSMs).
3. Components of a Sequential Circuit
A synchronous sequential circuit mainly consists of:
1. Combinational Logic – Generates the next state based on the present state and inputs.
2. Memory Elements (Flip-Flops/Latches) – Stores the present state.
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 3. Clock Signal – Synchronizes state transitions.
5. Difference Between Combinational and Sequential Circuits

Feature Combinational Circuit Sequential Circuit

Memory No memory required Requires memory

Output Depends On Present input only Present & past input

Clock Required No Yes (for synchronous)

Examples Adders, Multiplexers Flip-Flops, Counters

Latches and Flip-Flops in Digital Electronics

Latches and flip-flops are fundamental building blocks of sequential circuits in digital electronics.
They are used for storing binary data (0 or 1) and play a key role in memory elements, registers, and
state machines.
1. Latch
A latch is a level-triggered (or transparent) bistable circuit that can store one bit of data. It changes
its output state as long as the enable signal is active.
Types of Latches:
1. SR Latch (Set-Reset Latch)
2. D Latch (Data Latch)
(A) SR Latch (Set-Reset Latch)
An SR Latch is the simplest type of latch, built using two NOR or NAND gates.

R R
Q
C
S Q
S
SR Latch using NOR Gates

C(control) S (Set) R (Reset) Q (Output) Q̅ (Complement)

0 X X No Change No Change

1 0 0 No Change No Change

1 0 1 0 1

1 1 0 1 0

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C(control) S (Set) R (Reset) Q (Output) Q̅ (Complement)

1 1 1 Invalid Invalid

• If S = 1, R = 0, Q is set to 1.
• If S = 0, R = 1, Q is reset to 0.
• If S = 0, R = 0, Q holds the previous state.
• If S = 1, R = 1, it's an invalid state.
SR Latch using NAND Gates
It works similarly, but the Invalid state (S=1, R=1) is replaced with a stable state (Q=0, Q̅=1).

(B) D Latch (Data Latch)

A D Latch (Data Latch) ensures that the output follows the input (D) only when the Enable signal
(E) is active.

Enable (E) D (Input) Q (Output)

0 X No Change

1 0 0

1 1 1

• If E = 1, Q follows D.
• If E = 0, Q holds its previous state.

• Controlled latches are level-triggered

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 • Flip-Flops are edge-triggered

2. Flip-Flop
A flip-flop is an edge-triggered bistable device, meaning it changes output only on the rising edge or
falling edge of a clock pulse.
Types of Flip-Flops:
1. SR Flip-Flop
2. D Flip-Flop
3. JK Flip-Flop

(A) SR Flip-Flop
An SR Flip-Flop is similar to an SR Latch but is clock-controlled, meaning it only updates its output
at the clock edge.

Clock S (Set) R (Reset) Q (Output)

↑ 0 0 No Change

↑ 0 1 0

↑ 1 0 1

↑ 1 1 Invalid

(B) D Flip-Flop
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A D Flip-Flop eliminates the invalid state of an SR Flip-Flop by ensuring D = S and D̅ = R.

Clock D (Input) Q (Output)

↑ 0 0

↑ 1 1

It acts as a delay element, storing data at each clock pulse.

(C) JK Flip-Flop
A JK Flip-Flop removes the invalid state of an SR Flip-Flop by allowing both J = 1 and K = 1 to
toggle the output.

Clock J (Set) K (Reset) Q (Output)

↑ 0 0 No Change

↑ 0 1 0

↑ 1 0 1

↑ 1 1 Toggle

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Differences Between Latch and Flip-Flop

Feature Latch (Level Triggered) Flip-Flop (Edge Triggered)

Triggering Level-triggered Edge-triggered

Clock No clock required Needs a clock signal

Usage Faster, used in small circuits Used in sequential logic circuits

Reliability More prone to glitches More stable

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Integrated Circuits: Decoder, Multiplexer, and Demultiplexer
Introduction
Integrated Circuits (ICs) are small electronic circuits built on a semiconductor chip. In digital
electronics, three important ICs are:
1. Decoder – Converts binary input into a unique output.
2. Multiplexer (MUX) – Selects one input from multiple inputs and forwards it to the output.
3. Demultiplexer (DEMUX) – Takes a single input and sends it to one of the many outputs.
These ICs are widely used in computers, communication systems, and digital applications.

1. Decoder
Definition
A decoder is a combinational circuit that takes an n-bit binary input and activates one of its 2^n
output lines. It is mainly used in memory address decoding, display drivers, and instruction
decoding in microprocessors.
Circuit Diagram of a 2-to-4 Decoder

Truth Table for 2-to-4 Decoder

A1 A0 Y3 Y2 Y1 Y0

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0

Working
• The input combination determines which one output line is activated.
• Example: If input is A1=1, A0=0, then Y2=1, and all others are 0.
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Applications
• Used in memory address decoding.
• Drives seven-segment displays.
• Used in instruction decoding in CPUs.

2. Multiplexer (MUX)
A multiplexer (MUX) is a circuit that selects one input from multiple inputs based on select lines
and sends it to the output. It is also called a data selector.
A multiplexer, often abbreviated as "MUX," is a device or circuit used in electronics and digital
systems to select one of several input signals and forward it to a single output line.
A multiplexer is a combinational logic circuit with multiple input lines, a single output line, and a set
of control lines (also called select lines).
The control lines determine which one of the input signals is routed to the output. Think of it as a
traffic controller that picks one "road" (input) out of many and directs its "traffic" (data) to a single
destination (output).
• Inputs: These are the multiple data lines feeding into the multiplexer. The number of inputs is
typically a power of 2 (e.g., 2, 4, 8, 16), denoted as 2n2^n2n, where nnn is the number of
select lines.
• Select Lines: These are control inputs that specify which input is chosen. The number of
select lines (nnn) determines how many inputs (2n2^n2n) the multiplexer can handle. For
example, 1 select line can choose between 2 inputs, 2 select lines can choose between 4
inputs, and so on.
• Output: The single line where the selected input is sent.

Specifically, a multiplexer comprising 2N inputs necessitates N select lines.

Circuit Diagram of a 4-to-1 Multiplexer

1. 2-to-1 Multiplexer
2. 4-to-1 Multiplexer
3. 8-to-1 Multiplexer
4. 16-to-1 Multiplexer

Working
• The select lines (S1, S0) determine which input (I0 to I3) is sent to the output.
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 • Example: If S1=1, S0=0, the output will be I2.
Applications
• Used in data routing in communication systems.
• Helps in switching and signal transmission.
• Used in ALUs for selecting operations.
3. Demultiplexer (DEMUX)
Definition
A demultiplexer (DEMUX) is a circuit that takes a single input and routes it to one of multiple
outputs based on select lines.
Circuit Diagram of a 1-to-4 Demultiplexer

Working
• The select lines (S1, S0) determine which output line receives the input value.
• Example: If S1=1, S0=0, input is sent to Y2.
Applications
• Used in communication systems to send data to different locations.
• Helps in data distribution in multiplexed networks.
• Used in memory and register operations.

Conclusion

Circuit Type Function Example IC

Decoder Converts binary input to a unique output 74LS138 (3-to-8 Decoder)

MUX Selects one input from multiple inputs 74LS151 (8-to-1 MUX)

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Circuit Type Function Example IC

DEMUX Distributes a single input to multiple outputs 74LS154 (1-to-16 DEMUX)

These circuits are essential in digital systems, computers, and communication networks, making
data transfer and processing more efficient.

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