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VLSI Project 2

The document details a VLSI project by Adarsh Jaiswal on designing and simulating a Traffic Light Controller using Verilog HDL, focusing on finite state machines and timing control. The system manages a two-way intersection with alternating traffic light states every 10 seconds, validated through simulation results. The project emphasizes hands-on experience in FSM design, timing control, and synthesis, showcasing the author's growing expertise in digital design.

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kollasunnykumar123
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13 views3 pages

VLSI Project 2

The document details a VLSI project by Adarsh Jaiswal on designing and simulating a Traffic Light Controller using Verilog HDL, focusing on finite state machines and timing control. The system manages a two-way intersection with alternating traffic light states every 10 seconds, validated through simulation results. The project emphasizes hands-on experience in FSM design, timing control, and synthesis, showcasing the author's growing expertise in digital design.

Uploaded by

kollasunnykumar123
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Design and Simulation of a Traffic Light Controller Using

Verilog HDL
I, Adarsh Jaiswal, recently completed a VLSI project involving the design, simulation, and
verification of a Traffic Light Controller using Verilog HDL. This project showcases the
application of digital design principles, emphasizing finite state machines (FSM), timing
control, and efficient resource utilization.

Project Overview

The Traffic Light Controller is a simplified system designed to manage a two-way


intersection with the following key features:

1. State Management:
o State 1: North-South (NS) Green, East-West (EW) Red.
o State 2: NS Red, EW Green.
o States alternate every 10 seconds.
2. Timing Logic:
o The system operates on a 50 MHz clock. A counter manages the 10-second
timing interval for state transitions.
3. Reset Functionality:
o A reset signal initializes the controller to the default state, ensuring reliable
operation.

System Resource Usage

The design was synthesized on the Xilinx Spartan-6 FPGA using Xilinx ISE Design Suite.
Below is the resource utilization:

This demonstrates the simplicity and efficiency of the design, making it suitable for low-cost
hardware.
Simulation Results

The design was validated through simulation, and the outputs matched the expected behavior:

 State 1: North-South light is Green, and East-West light is Red.


 State 2: North-South light turns Red, and East-West light turns Green.

Key Observations:

 Transitions occur precisely at 10-second intervals.


 Traffic signals follow a safe sequence without overlapping green lights.

RTL Schematic

The RTL schematic, generated post-synthesis, provides a visual representation of the design
logic. The key components include the FSM logic, counters, and traffic light control signals.

Waveform Results

Below is a snapshot of the simulation waveform:

 The signals NS_light and EW_light alternate between Green and Red states based on
the timer.
 The reset initializes the system to the default state (NS Green, EW Red).
Key Takeaways

This project provided me with hands-on experience in:

1. FSM Design: Creating robust state-based systems in Verilog.


2. Timing Control: Using counters and clock signals for precise delays.
3. Synthesis and Simulation: Validating designs through RTL schematics and
waveform analysis.

Conclusion

This project highlights my growing expertise in digital design and HDL programming. It
allowed me to bridge the gap between theoretical knowledge and practical implementation,
laying the foundation for tackling more complex VLSI designs.

I am excited to explore advanced digital design concepts and contribute to innovative projects
in this domain. Feel free to connect with me to discuss ideas or collaborate on exciting
ventures!

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