MODULE-4

Exception and Interrupt Handling: Exception handling, ARM processor

exceptions and modes, vector table, exception priorities, link register
offsets, interrupts, assigning interrupts, interrupt latency, IRQ and FIQ
exceptions, basic interrupt stack design and implementation.
Firmware: Firmware and bootloader, ARM firmware suite, Red Hat
redboot, Example: sandstone, sandstone
directory layout, sandstone code structure.
Textbook 1: Chapter 9.1 and 9.2, Chapter 10
RBT: L1, L2, L3
 Current Program Status Register(cpsr)
• The ARM core uses the cpsr to monitor and control internal
operations.
• The cpsr is a dedicated 32-bit register and resides in the
register file.
 Processor Modes
➢Processor mode: Privileged or nonprivileged.
➢privileged mode allows full read-write access to the cpsr.
➢nonprivileged mode allows read access to the control field in the cpsr and
allows read-write access to the condition flags.
➢processor modes: 6 privileged and 1 nonprivileged
1. abort
2. fast interrupt request
3. interrupt request
4. supervisor
5. system
6. undefined
7. user (nonprivileged)
ARM Register set
 Processor Modes
• Abort-> The processor enters abort mode when there is a failed attempt to
access memory.
• Fast interrupt request/Interrupt ->Fast interrupt request and interrupt request
modes correspond to the two interrupt levels available on the ARM processor.
• Supervisor -> Supervisor mode is the mode that the processor is in after reset
and is generally the mode that an operating system kernel operates in.
• System -> System mode is a special version of user mode that allows full read-
write access to the cpsr.
• Undefined ->Undefined mode is used when the processor encounters an
instruction that is undefined or not supported by the implementation.
• User (nonprivileged)-> User mode is used for programs and applications.
 Exception Handling
• An exception is any condition that needs to halt the normal
sequential execution of instructions.
• Exception handling is the method of processing these
exceptions.
• Most exceptions have an associated software exception
handler—a software routine that executes when an exception
occurs.
• The handler first determines the cause of the exception and
then services the exception.
• Servicing takes place either within the handler or by branching
to a specific service routine.
ARM Processor Exceptions and Modes
• Reset vector: is the location of the first instruction executed by the
processor when power is applied. This instruction branches to the
initialization code.
• Undefined instruction vector is used when the processor cannot decode an
instruction.
• Software interrupt vector is called when we execute a SWI instruction.
• Prefetch abort vector occurs when the processor attempts to fetch an
instruction from an address without the correct access permissions.( abort
occurs in the decode stage).
• Data abort vector is similar to a prefetch abort but is raised when an
instruction attempts to access data memory without the correct access
permissions.
• Interrupt request vector is used by external hardware to interrupt the normal
execution flow of the processor. It can only be raised if IRQs are not masked
in the cpsr.
• Fast interrupt request vector is similar to the interrupt request but is
reserved for hardware requiring faster response times. It can only be raised if
 Reset
• The Reset exception is the highest priority exception and is always
taken whenever it is signaled.
• The reset handler initializes the system, including setting up memory
and caches.
• External interrupt sources should be initialized before enabling IRQ or
FIQ interrupts.
• The reset handler must also set up the stack pointers for all processor
modes.
ARM processor exceptions and associated
modes.
• Each exception causes the core to enter a specific mode.
Block diagram of LPC2148
• Any of the ARM processor modes can be entered manually by
changing the cpsr.
• User and system mode are the only two modes that are not entered
by a corresponding exception.
Step of action
• Each exception causes the core to enter a specific mode.
• When an exception causes a mode change, the core automatically
saves the cpsr to the spsr of the exception mode
• saves the pc to the lr of the exception mode
• sets the cpsr to the exception mode
• sets pc to the address of the exception handler
• when an exception occurs the ARM processor always switches to
ARM state.
Vector Table
• Vector table—a table of addresses that the ARM core branches to,
when an exception is raised.
Vector table and processor modes.
• These addresses commonly contain branch instructions of one
of the following forms:
1. B <address>—This branch instruction provides a branch relative from
the pc.
2. LDR pc, [pc, #offset]-- This load register instruction loads the handler
address from memory to the pc.
3. LDR pc, [pc, #-0xff0]—This load register instruction loads a specific
interrupt ser_x0002_vice routine address from
address 0xfffff030 to the pc. This specific
instruction is only used when a vector interrupt
controller is present (VIC PL190).
•
Exception Priorities
 Link Register Offsets
• When an exception occurs, the link register is set to a specific address based on the
current pc.
• when an IRQ exception is raised, the link register lr points to the last executed
instruction plus 8.
• The IRQ exception is taken only after the current instruction is executed, so the return
address has to point to the next instruction, or lr − 4.
Methods to return from IRQ/FIQ interrupt handler
S at the end of the SUB instruction and the pc is the
• 1) destination register,the cpsr is automatically restored
from the spsr register.

• subtracts the offset from the link

register r14 at the beginning of the
• 2) handler.
• return to normal execution occurs by
moving the link register r14 into the
pc and restoring cpsr from the spsr.

• 3) • uses the interrupt stack to store the link

register. This method first subtracts an offset
from the link register and then stores it onto
the interrupt stack.
• LDM instruction is used to load the pc. The ˆ
symbol in the instruction forces the cpsr to
be restored from the spsr.
 Interrupts
• There are two types of interrupts available on the ARM processor.
1)interrupt causes an exception raised by an external peripheral—namely,
IRQ and FIQ.
2) Instruction that causes an exception—the SWI instruction.
• Both types suspend the normal flow of a program.
Assigning Interrupts
• A system designer can decide which hardware peripheral can produce
which interrupt request.
• It is depending on the embedded system the disigner is working.
Assigning Interrupts
• When it comes to assigning interrupts, system designers have
adopted a standard design practice:
• Software Interrupts are normally reserved to call privileged
operating system routines.
• Interrupt Requests are normally assigned for general-purpose
interrupts.
• The IRQ exception has a lower priority and higher
interrupt latency
• Fast Interrupt Requests are normally reserved for a single
interrupt source that requires a fast response time . example:
direct memory access specifically used to move blocks of
memory.
 Interrupt Latency
• interrupt latency—It is the interval of time from an external interrupt
request signal being raised to the first fetch of an instruction of a specific
interrupt service routine (ISR).
• Interrupt latency depends on a combination of hardware and software.
• System architects must balance the system design to handle multiple
simultaneous interrupt sources and minimize interrupt latency.
• If the interrupts are not handled in a timely manner, then the system will
exhibit slow response times.
• Software handlers have two main methods to minimize interrupt latency.
1. nested interrupt handler
2. prioritization
 A three-level nested interrupt.
• Nested interrupt handling is where the
software is prepared to accept another
interrupt, even before it finishes handling
the current interrupt.
• This is achieved by reenabling the
interrupts as soon as the interrupt source
has been serviced and before the
interrupt handling is complete.
• After nested interrupt has been serviced,
the control is relinquished to the original
interrupt service routine.
Prioritization
• This can be achieved by programming the interrupt controller to
ignore interrupts of the same or lower priority than the current
interrupt it is handling.
• Only a higher-priority task can interrupt the current handler.
• The processor spends time in the lower-priority interrupts until a
higher-priority interrupt occurs.
• Therefore higher-priority interrupts have a lower average interrupt
latency than the lower-priority interrupts.
• It reduces latency by speeding up the completion time on the critical
time-sensitive interrupts.
 IRQ and FIQ Exceptions
• IRQ and FIQ exceptions only occur when a specific interrupt mask is cleared in
the cpsr.
• The ARM processor will complete executing the current instruction in the
execution stage of the pipeline before handling the interrupt.
• An IRQ or FIQ exception causes the processor hardware to go through a
standard procedure (provided the interrupts are not masked)
1. The processor changes to a specific interrupt request mode, which
reflects the interrupt being raised.
2. The previous mode’s cpsr is saved into the spsr of the new interrupt
request mode.
3. The pc is saved in the lr of the new interrupt request mode.
4. Interrupt/s are disabled—either the IRQ or both IRQ and FIQ exceptions are
disabled in the cpsr. This immediately stops another interrupt request of the same
type being raised. 5. The processor branches to a specific entry in the vector
table.
what happens when an IRQ exception is raised,
example of an FIQ exception.
 Enabling and Disabling FIQ and IRQ Exceptions
Enabling The Interrupt
Disabling Interrupt