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Architecture Assignment 8

The assignment requires students to design a 32-bit ALU-based processor for R-type instructions using Logisim, integrating a register file and control unit. Deliverables include a .circ file, a detailed PDF report, and screenshots demonstrating the circuit's functionality. Testing must confirm correct ALU operations and register updates based on R-type instructions.

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4 views

Architecture Assignment 8

The assignment requires students to design a 32-bit ALU-based processor for R-type instructions using Logisim, integrating a register file and control unit. Deliverables include a .circ file, a detailed PDF report, and screenshots demonstrating the circuit's functionality. Testing must confirm correct ALU operations and register updates based on R-type instructions.

Uploaded by

b22es024
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Assignment:8

CSL3020: Computer Architecture


AY 2024-25, Semester – V
Due on: 16-11-2024
Total:50 Marks

Submission and General Guidelines:

Submit your Logisim project as a .circ file.

Include a report in PDF format detailing your design, implementation and outlining each
step involved in the process in detail.

Provide screenshots of your circuit with various R-type input instructions, along with the
corresponding ALU operations performed for each instruction.

Organize your Logisim circuit neatly, using labels for different sections (e.g., Decoder,
Control Signals, Input, Output, etc. ).

Submit your report using the filename format your_roll_no.pdf and your circuit design
file as roll_no.circ.

Design a 32-bit ALU-Based Processor for R-Type Instructions

Combine the implementation of the previous two assignments (Control Unit and 32-bit
ALU) and integrate the functionality of the register file.

Objective

Design and implement a processor system in Logisim that executes R-type instructions
using a 32-bit ALU, a 32-register register file, and a controller module with appropriate
control signals. [50]

Components and Requirements

1. Register File (32 Registers)


○ Inputs:
■ 5-bit address inputs: rs, rt, rd.
■ 32-bit Write Data input (ALU result).
■ RegWrite control signal to enable writing to the rd register.
○ Outputs:
■ 32-bit outputs: Read Data 1 (from rs), Read Data 2 (from rt).
■ Clock signal to control write operations.
2. ALU (32-bit)
○ Inputs: Read Data 1 and Read Data 2 from the register file.
○ Outputs:
■ 32-bit ALU Result. And store the result in register
■ Zero, Overflow, and Underflow flags.
3. Controller Module
○ Outputs: 9-bit control signal for ALU operations and RegWrite.
○ Generates ALU control signals based on only R-type instructions.
4. Clock
○ A clock signal to control the register write operations synchronized with the
system.

Testing and Verification

● Load R-type instructions and verify that the ALU performs the correct operation.
● Ensure the Zero, Overflow, and Underflow flags work correctly.
● Check that only the rd register is updated when RegWrite is enabled, and the
correct values are read from rs and rt.

Deliverables

● Logisim project file with the complete design.


● Screenshots of the register file, ALU, and control signals during execution.
● Screenshots of the values in the register file when a particular R-type instruction is
executed.
● A brief report explaining the integration of components and control signals.

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