UNIT-III

PERIPHERAL INTERFACING

PROGRAMMABLE KEYBOARD / DISPLAY

CONTROLLER (8279)
CONTENTS:

 What is Programmable keyboard / Display Controller (8279)

 Features of 8279
 Block Diagram of 8279
 Pin Diagram of 8279
 Modes of operation of 8279
WHAT IS 8279 ?

 Intel’s 8279 is a general purpose Keyboard Display controller that simultaneously

drives the display of a system and interfaces a Keyboard with the CPU.

 The Keyboard Display interface scans the Keyboard to identify if any key has been
pressed and sends the code of the pressed key to the CPU.

 It also transmits the data received from the CPU, to the display device.
CONTINUED..

 There are two approaches to interface a matrix keyboard and a multiplexed display
to the microprocessor namely,
1) Hardware Approach
2) Software Approach

 The disadvantage of software approach is that the microprocessor is occupied for a

considerable amount of time in checking the keyboard and refreshing the display.

 Intel 8279 follows hardware approach and it has the advantage of relieving the
processor from the above mentioned two tasks. But it is expensive.
FEATURES OF 8279:

 Intel 8279 is a 40 pin LSI device used to interface the keyboard and the multiplexed
display sections to the microprocessor 8085 or 8086.
 It supports keyboard of size up to 64 keys Matrix with 2-key lockout and n-key
rollover options.
 It supports display interface of up to 16 digits with many options.
 It has a built in hardware for key debouncing* operation.
 It provides 8 byte FIFO RAM to store keywords.
 It provides multiplexed display interface with blanking and inhibit options.
CONTINUED..

 It provides a 16 byte RAM corresponding to the 16 digit display, allowing to

interface 16 digits.
 It supports simultaneous keyboard and display operations.
 It is fully programmable, providing three modes of operation.The three modes of
operation are Scanned Keyboard mode, Scanned Sensor Matrix mode, Strobed
Input mode.
 It provides two output modes.They are Left entry(similar to type writer) and Right
entry(Similar to calculator)
 It automatically controls display refreshing and multiplexing.
BLOCK DIAGRAM OF 8279:
BLOCK DIAGRAM-CONTINUED..

 Block Diagram consists of four main sections,

1) Microprocessor(CPU) interface section
2) Scan section
3) Keyboard section
4) Display section
MICROPROCESSOR (CPU) INTERFACE
SECTION:

 This section consists of

1) Data buffers
2) I/O control
3) Control and timing registers
4) Timing and control logic.
1) DATA BUFFERS:

 The data buffers are 8-bit bi-directional buffers (DB0-DB7) that connect the internal
data bus to the external data bus.

 These lines are used for communication(i.e) transfer of data, commands and status
between the microprocessor(CPU) and 8279.
2) I/O CONTROL:

 The I/O control section uses the A0, CS, RD and WR signals to control data flow to
and from the various internal registers and buffers.
 The data flow to and from the 8279 is enabled only when CS = 0; otherwise the 8279
signals are in a high impedance state.
 The Block Diagram of 8279 interprets the data given or desired by the CPU with the
help of A0, RD and WR signals, as shown in the figure in the next slide.
 When A0 is logic 0 data is transferred and when A0 is logic 1 command word or
status word is transferred. RD and WR determine -the direction of data flow through
the data buffers.
OPERATION OF 8279:
3) CONTROL AND TIMING REGISTERS:

 The control and timing registers store the keyboard and display modes and other
operating conditions programmed by the CPU.

 The modes are programmed by sending the proper command on the data lines with
A0 = 1. The command is latched on the rising edge of WR.

 The command is then decoded and the appropriate mode/function is set.

4) TIMING AND CONTROL:

 The timing control consists of the basic timing counter chain.

 The first counter is divided by N prescaler that can be programmed to give an

internal frequency of 100 kHz.

 The other counters divide down the basic internal frequency, to provide the proper
key scan, row scan, keyboard matrix scan, and display scan times.

 The internal frequency of 100 KHz gives the internal timings.

SCAN SECTION:

 The scan section has a scan counter and four scan lines SL0-SL3.

 These lines can be decoded by a 4 to 16 decoder to generate 16 lines for scanning.

 These lines are connected to the rows of a matrix keyboard and the digit drivers of
a multiplexed display.
SCAN SECTION-CONTINUED..

 The scan section has a scan counter which has two modes :
1)Encoded mode
2)Decoded mode
1)Encoded Mode:
 In the encoded mode, the scan counter provides a binary count from 0000 to 1111 on
the four scan lines (SC3 — SC0) with active high outputs. This binary count must be
externally decoded to provide 16 scan lines.
 Display can use all 16 scan lines to interface 16 digit 7-segment display, but
keyboard can use only 8 scan lines out of 16 scan lines.
SCAN SECTION-CONTINUED..

2)Decoded Mode:
 In the decoded mode, the internal decoder decodes the least significant 2 bits of
binary count and provides four possible combinations on the scan lines (SC3 —
SC0) :1110, 1101, 1011 and 0111.

 Thus the output of decoded scan is active low. These four active low output lines
can be used directly to interface 4 digit 7 segment display, 8 x 4 matrix keyboard,
eliminating the external decoder.
KEYBOARD SECTION:

 This section consists of

1) Return buffers
2) Keyboard debounce and control
3) FIFO/sensor RAM
4) FIFO/sensor RAM status.
1) RETURN BUFFERS:

 This section has 8 return lines (RL0 — RL7) and two additional lines: Shift and
CNTL/STB (control/strobe).
 The status of the SHIFT key and the control key can be stored along with a key
closure.
 The return lines (RL0 — RL7) are connected to the columns of the keyboard.
 These eight return input lines are used to interface the matrix keyboard.
 These lines have internal pull ups which keep their status high.When the key from
the matrix keyboard is pressed, corresponding return line goes low.
 In the strobed input mode, these lines are used as 8 input lines.These lines are used
to get the 8 column outputs from the keyboard to 8279.
SHIFT AND CNTL/STB KEY IN RETURN
BUFFER:
 SHIFT:
It is a special key input line.Its status is stored along with the key position on the key
closure in the scanned keyboard mode.It also has an active internal pull up to keep it
high until a switch closure* pulls it low.
 CNTL/STB (control/strobe):
For scanned keyboard mode,this line is used as the control input.Its status is also stored
along with the key position on key closure.It also has an active internal pull up to keep
it high until a switch closure pulls it low.
In strobed input mode,this line is used as a strobe input.When activated,it loads the
status of the keyboard into the FIFO RAM.
2) KEYBOARD AND DEBOUNCE CONTROL:

 In Keyboard and debounce control unit, the keys are automatically debounced.It is
enabled only when it is Scanned keyboard mode.In this mode the return lines are
scanned whether the key is closed in the row or not.

 The status logic keeps track of the number of entries and provides an interrupt
request(IRQ) signal when the FIFO is not empty.

 If the debounce circuit detects a close switch, it waits about 10 msec to check if the
switch remains closed. If it does, the address of the switch in the matrix plus the
status of SHIFT and CONTROL keys are transferred to the FIFO RAM.
3)FIFO/SENSOR RAM:

 This is a dual function 8 x 8 RAM.

 Each new entry is written into successive RAM positions and then read in order of
entry.

 Each row of the sensor RAM is loaded with the status of the corresponding row of
sensor in the sensor matrix.
4)FIFO/SENSOR RAM STATUS:

 FIFO RAM status keeps track of the number of characters in the FIFO and whether
it is full or empty.

 The status logic also makes IRQ signal high when the FIFO is not empty, which can
be used to interrupt CPU telling that key press is detected and keycode is available
in FIFO RAM.
DISPLAY SECTION:

 The display section consists of 16 x 8 display RAM, display address registers and
display registers.The microprocessor can read from or write into any of these
registers.

 This section has 8 output lines divided into two groups,A0-A3 and B0-B3.They are
used as a group of eight lines or as two groups of four lines in synchronisation with
the scan lines for multiplexed display.

 The display can be blanked by the BD line(Blank Display) .It is active low output
signal and is used to blank the display during digit switching or by a display
blanking command.
PIN DIAGRAM:
PIN DIAGRAM-CONTINUED..

we can see that these pins are divided in four functional groups :
1) CPU interface
2) Key data
3) Display data
4) Scan
1)CPU INTERFACE PINS:

 As shown in the figure in before slide, it consists of 8-bit data bus, RD, WR, A0, CS,
RESET, CLK and IRQ lines.

1) DB0-DB7 : Bi-directional data bus :

All data, commands and status information between the CPU and the 8279 are
transmitted on these bi-directional 8-bit data bus.

2) RD : Read:
It is an active low signal. It is enabled by the microprocessor. When RD signal is low
CPU reads the contents of selected register (display RAM, status register or FIFO
RAM) from 8279; depending on the type of command and the status of the A0 signal.
CPU INTERFACE PINS-CONTINUED..

3)WR : Write:
It is an active low signal. It is enabled by the microprocessor. When WR signal is low,
CPU loads the data or the command into selected register (control register or display
register) depending on the status of A0 signal.

4)A0 : Address line:

It is the buffer address line used to select the control port (A0=1) or the data
port(A0=0).It is enabled by the microprocessor.When A0 is high, signals are
interpreted as a command or status. When A0 is low, signals are interpreted as a data.
CPU INTERFACE PINS-CONTINUED..

5)CS : Chip select :

It is an active low signal.It is enabled by the microprocessor. When low, enables the
communication between CPU and 8279.

6)RESET :
A high signal on this pin resets 8279. After being reset 8279 is configured in the following
modes: (i) 16 x 8 bit character display-left entry. (ii)Two key lockout.

7)CLK :
This signal is usually provided by an external circuit and used to generate internal
timings.The clock frequency must be greater than 200KHz to provide correct delays.
CPU INTERFACE PINS-CONTINUED..

8)IRQ : Interrupt Request :

 It is an interrupt request signal provided by the 8279 to the microprocessor
indicating the request for the next data transfer.

 It goes low with each FIFO/sensor RAM read and returns high if there is still
information in the RAM.
2)KEYBOARD DATA PINS:

 This group consists of return, SHIFT and CNTL/STB lines.

1)RL0-RL7 : Return lines :

These input lines are used to interface matrix keyboard. These lines have active internal
pullups which keep their status high.
When the key from the matrix keyboard is pressed corresponding return line goes low.
In the strobed input mode these lines are used as 8 input lines.
KEYBOARD DATA PINS-CONTINUED…

2)SHIFT :
It is a special key input line. Its status is stored along with the key position on the key
closure in the scanned keyboard modes. It has an active internal pullup to keep it high
until, a switch closure pulls it low.

3)CNTL/STB : (Control/strobe)
 For scanned keyboard mode this line is used as a control input. Like SHIFT key, its
status is stored along with the key position on the key closure. It also has an active
internal pullup to keep it high until a switch closure pulls it low.
 In the strobed input mode this line is used as a strobe input. When activated, loads
the status of keyboard into the FIFO RAM.
3)DISPLAY DATA PINS:

 This group consists of OUT A3-A0, OUT B3-B0 and BD lines.

1)OUT A3-A0 and OUT B3-B0 :

 These two four bit output ports; which can be considered as an one 8-bit port.
 These are used for sending data to display drivers from display RAM and connected
to the segment inputs of 7 segment display or row inputs of dot matrix displays.
 These lines are synchronized to the scan lines (SL0-SL3) for multiplexed digit
display. In other words we can say that when the data on the scan lines is 0000,
ports will have data from register 0 of display RAM and when the data on the scan
lines is 1111, ports will have data from register 15 of display RAM.
 The two 4-bit ports can be blanked independently.
DISPLAY DATA PINS-CONTINUED..

2)BD : Blank Display :

This is an active low output used to blank the display during digit switching or by a
display blanking command.
4) SCAN DATA:

 The scan lines SL0-SL3 scan the keyboard matrix and the display digits.

 These lines can be programmed as encoder or decoder using mode control registers.
MODES OF OPERATION OF 8279:

 1)INPUT MODES:
8279 provides 3 basic input modes for the keyboard interface
section.
(i)Scanned keyboard mode,
(ii)Scanned sensor matrix mode,
(iii)Strobed input mode.
1) INPUT MODES:

 SCANNED KEYBOARD MODE:In this mode,the keyboard can be scanned in

two ways:Encoded scan and decoded scan.The scanned keyboard mode allows key
depressions in 2-key lockout or N-key rollover.

 SCANNED SENSOR MATRIX MODE:In this mode,FIFO buffer is converted

into 8 x 8 bit map.Each bit represents the state of the switch at the same location in
the keyboard matrix.

 STROBED INPUT MODE:In this mode,data is entered into the FIFO RAM from
the return lines at the rising edge of the CNTL/STB Signal.
2) DISPLAY MODES:

 1) LEFT ENTRY: In the left entry mode,the 8279 displays characters from left to
right in the multiplexed displays.Eg:Typewriters

 2) RIGHT ENTRY: In the left entry mode,the 8279 displays characters from right
to left in the multiplexed displays.Eg:Calculators.