Embedded.

Systems
1.62 and loy
P3.2 - INTO

P3.3 - INTI

P3.4 - TO

P3.5 - T1

P3.6 - WR

P3.7 - RD
These pins can be individually programmed.

1.14. SERIAL PORT PROGRAMMING

Computers transfer data in two ways

1. Serial Data Transfer
2. Parallel Data Transfer
In parallel data transfer 8 or more lines are used to transfer data to a device
Examples of parallel transfers are printers and hard disks. In this method lots of dat
can be transferred in a short amount of time.

1.14.1. BASICS OF SERIAL COMMUNICATION

In serial communication only one bit is transferred at a time. It takes lots of tim
to transfer a lot of message.

DO

Sender Receiver Sender Receiver

Serial Transfer
D7

Parallel Transfer

Fig. 1.17. Serial Versus Parallel Data Transfer

 |1.63
8- Bit Embedded Processor
converted to serial bits
In serial data communication, the byte of data must be
single data
parallel-in-serialout shift to register, then it is transmitted over a
using a
line.
has a serial in parallel out shift register to receive the serialdata
The receiving end
and pack them into a byte.
it must be converted from 0's and
If data is to be transferred on the telephone line,
sinusoidal-shaped signals. This conversion is
1's into audio tones, which are
(modulator/demodulator).
performed by a peripheral device called a modem
signal can be transferred
When the distances short, without modulation the digital
communication lines such
using simple wire. For long-distance, data transfer is using
to modulate (convert from
as telephone, serial data communication requires a modem
audio tones to 0's and
0's and 1's two audio tones) and demodulate (convert from
1's).
Method of Communication

Serial data communication uses two mnethods for transferring data such as
1. Asynchronous
2. Synchronous
The asynchronous method transfers a single byte at a time while synchronous
method transfers a block of data at a time. There are special IC chips available for
serial data communications such as follows.
1. UART - Universal Asynchronous Receiver Transmitter
2. USART - Universal Synchronous-Asynchronous Receiver Transmitter
Types of Transmission

There are two kinds of data transmission take place.

1. Duplex Transmission
2. Simplex Transmission
1. Duplex Transmission

If the data can be transmitted and received, then it is called Duplex transmissior.
It has two types.
1. Half Duplex
2. Full Duplex
 Embedded.
1.64| Systems and ic
as Half
is transmitted one way at atime, it is referred to Duplex. If
If data
time, it is full duplex.
the day
can go both ways at the same
Receiver
Transmiter

Transmitter
Receiver

Fig. 1.18. Half Duplex Transfers

Transmitter Receiver

Fig. 1.19. Full Duplex Transfers

Simplex Transmission

The data can be transferred not yet received. Such transmission is called as
simplex transmission.
Transmitter Receiver

Fig. 1.20. Simplex Transfers

1.14.2. ASYNCHRONOUS SERIAL COMMUNICATION
Asynchronous serial data communication is widely used for character oriented
transmissions. In this method, each character is placed between start and stop
This is called Framing. bits
In data framing for asynchronous communication,
the data is placed between a
start bit and a stop bit. The start bit is always
one bit and stop bit can be one or two
bits. The start bit isalways a 0 (low) and stop bit is 1 (high).
The figure 1.21 shows the ASCII character
the start bit and a single stop A". (0100 0001 )is framed between
bit.
When there is no transfer, the signal is
(low) is referred to a space. The 1(high), which is called as mark and 0
and transmits all the bits until D7,transmission begins with a start bit followed by DO
character. finally the one stop bit indicating the
end of the
 1.65|
Embedded Processor
8- Bit

4
Start Mark
Stop 1 0 0 bit
bit
Space

DO
D7 goes out first
goes out last

Fig. 1.2l. Framing ASCII A"

Data Transfer Rate

communication is called in bps (bits per

The rate of data transfer is serial data
baud rate.
second). Another used terminology for bps is
of signal changes per second is called as baud rate. The data transfer
The number
system depends on communication ports incorporated into that
rate of a computer
system.
RS232 Standards

standard. The standard is

RS232 is the most widely used Serial VO Interfacing
used in PCs and numerous types of equipments.
+3 to + 2SV, making 3
In RS232, 1 is represented by - 3 to - 25V and 0 bit is
to a microcontroller system,
to + 3undefined. For thisreason, to connect any RS232
must use voltage converters such as MAX232 to convert the TTL Logic Levels to
we
the RS232 voltage levels and vice versa.
Pins of RS232

1 13

25
14

Fig. 1.22. Pin Diagram of RS232

|1.66 Embedded Systems and
IOT
RS232 has 25 Pins and Pin Diagram is shown in the figure and their description
shown in below table 1.1.

Table 1.I. RS232 Pins (DB-25)

Pin Deseription
1 Protective ground
2 Transmitted data (TxD)
3 Received data (RxD)
4 Request to send (RTS)
5 Clear to send (CTS)
6 Data set ready (DSR)
7 Signal ground (GND)
Data carrier detect (DCD)
9 & 10 Reserved for data testing
11 Unassigned
12 Secondary data carrier detect
13 Secondary clear to send
14 Secondary transmitted data
15
Transmit signal element timing
16 Secondary received data
17
Receive signal element timing
18
Unassigned
19
Secondary request to send
20
Data terminal ready (DTR)
21
Signal quality detector
22
Ring indicator
23
Data signal rate select
24
Transmit signal element timing
25
Unassigned
 1.67|
Processor
8- Bit Embedded
Data CommunicationClassification

Data Communication Equipment can be classified into two types

1. DTE Data Terminal Equipment
2. DCE Data Communication Equipment
receive data, while DCE
DTE, refers to terminals and computers that send and
refers to communication equipment such as modems.
RS232 Handshaking Signals

To ensure fast and reliable data transmission between two devices, the data
transfer must be cOordinated. Many of the pins of the RS232 connector are used for
handshaking signals such as follows.
1. DTR (Data Terminal Ready)
When a terminal is turned on,after going through a self-test, it sends out signal
DTRto indicate that it is ready for communication.
If there is something wrong with the COM Port, this signal will not be activated.
This is an active low signal and can be used to inform the modem that the computer
is alive and kicking.
DTR acts as output pin for DTE and input to the modem.
2. DSR (Data Set Ready)
It is an active low signal. When DCE is turned on and gone through the self-test, it
asserts DSR to indicate that it is ready to communicate.
This acts as output pin for DCE and input to DTE. For any reason, the DCE
cannot make a connection to the telephone until this signal remains inactive.
3. RTS (Request To Send)
When the DTE device has a byte to transmit, it asserts RTS to signal the modem
that it has a byte of data to transmit. RTS is an active low output from the DTE and
an input to the modem.
4. CTS (Clear to Send)
In response to RTS, when the modem has room for storing the data it is to receive,
it sends out signalCTS to the DTE to indicate that it can receive the data now. It is
input to the DTE and used by the DTE to start transmission.
5. DCD (Data Carrier Detect)
The modem asserts signal DCD to inform the DTE that a valid carrier has been
detected and that contact between it and the other modem is established.
 Embedded. Systems
|1.68 and Ior
6. RI (Ring Indicator)
An output from the modem and an input to a PC indicate that the telephone i
synchronization with the ringing
sound.
ringing. It goes on and off in

1.15. 8051 CONNECTION TO RS232

The RS232 Standard is not TTL compatible, so it requires aline driver MAX23)
levels to TTL levels and vice versa.
chip to convert RS232 voltage
RXD and TXD Pins in the 8051
The 8051 has two pins that are specifically used for transferring and receiving
data serially. Pin 11 of the 8051 is assigned to TXD and Pin 10 is designated as
RXD. These pins are TTL compatible that is the reason we need MAX232 to connect

compatible.
8051 with RS 232. Because RS 232 is not TTL
MAX232

Voc

16
1

3 2

MAX232 6

c2
5

TiN Tlour
8051 MAX232
11
11 11 14
TXDO

D
R1N Rlout
12 13
10 12 13 3
RXDO

10
T2N T2ouT

R2N R2oUT
TTL
- RS232
side Side

Fig. 1.23. (a) MAX232 (b) Its connection to the 8051

The figure. 1.23 (a) shows the MAX232 structure and figure 1.23 (6) shews how
it is connected to 8051.
 |1.69|
Processor
8- Bit Embedded
signals
used to convert the RS232's
MAX232 is a line driver (voltage
converter)
acceptable to the 8051's TXD
and RXD pins.
levels that will be
to TTL Voltage levels and vice
converts from RS232 voltage levels to TTL voltage
The MAX232 receiving data.
The MAX232 has two sets of line drivers for transferring and
versa.
drivers for RXD are
drivers used for TXD are called TIl and T2 and line
The line
defined as Rl and
R2,
Advantages

It uses 5 VPower Source

No need for dual power supplies

MAX233

MAX232 but it eliminates the need

The MAX233 performs the same job as the
for capacitors.But it ismuch more expensive than the MAX232.
Vcc

13 11

14 15

12
MAX233 16

|17 20

T1iN TloUT
3 8051 MAX233

RlouT Ri1N
2 5
TXDO

T2N T2OUT
o 18

RXDO
10 3 4 3

20
R2IN R2OUT 19 DB -9

TTL RS232
side side

(a) (b)

Fig. 1.24. (a) MAX 233 and (b) its connection to 8051

1.16. 8051SERIAL PORT PROGRAMMING

The 8051 two registers are used to perform Serial communication. Such registers
are 1. SBUF register 2. SCON register
 Embedded. Systems
1.70
and lo
1. SBUF Register
communicationin the 8051. For a
SBUF is an 8 bit register used for serial byte ot
data to be transferred via the TXD line and it must be placed in the SBUF register.
the 8051l's RXD line. SBUF
SBUF holds the byte of data when it is received by
can be accessed like any other register in the 8051.
sCON (SerialControl) Register
The SCON register is an 8 bit register used to programme the start bit, stop bbit and
data bits of data framing. It has following bit format. 0
7

RB8 TI RI
SMO SM1 SM2 REN TB8

Fig. 1.25. Format of SCONRegister

Receive interrupt flag. Set by hardware halfway
RI SCONO
be cleared
through the stop bit time in mode 1. Must
by software.
Hardware at the
TI SCON Transmit Interrupt Flag. Set by
Beginning of theStop Bit in mode
1.
Must be cleared by software.
RB8 SCON 2 Not widely used.
TB8 SCON 3 Not widely used.
REN SCON 4 Set/cleared by software to enable/disable reception.
SM2 SCON 5 Used for multiprocessor communication. (Make it 0.)
SMI SCON 6 Serial port mode specifier
SMO SCON 7 Serial port mode specifier
RI Receive Interrupt

This is important flag bit in the SCON register. When the 8051 receives data
serially via RXD, it gets rid of the start and stop bit and places the byte in the SBUF
register.
 1.71
8- Bit Embedded Processor

TI (Transmit Interrupt)
Whenthe 8051 finishes the
This is an important flag bit in the SCON register. indicate that it is ready to
transfer of the 8-bit character, it
raises the TI 1ag to
beginning of the stop bit.
transfer another byte. The TI bit is raised at the
RB8 (Receive bit 8)
stop bit. when an 8-bit data is received.
Inserial mode 1, this bit getsa copy of the
This bit is rapidly used any more.
TB8 (Transfer Bit 8)
It is used for serial modes 2 and 3.
REN (Receive Enable)
on the RXD pin of
When the REN bit is high, it allows the 8051 to receive data
receive data, by
the 8051. If REN = 1, the 8051 will perform both transfer and
making
REN =0 the receiver is disabled.
SM2

This bit enables the multiprocessing capability of 8051

SMO, SM1

These two bits determine the framing of data by specifying the number of bits per
character and the start and stop bits.
SMO SM1
0 Serial Mode 0
0 1 Serial Mode 1, 8-bit data, 1 stop bit, 1 start bit
1 Serial Mode 2
1 1 Serial Mode 3
Programming the 8051 to transfer data serially
The following steps to be taken to transfer character bytes serially.
1. The TMOD register is loaded with the value 20 H, indicating the use of
Timer 1 in mode 2 to set the baud rate.
 Embedded. Systems annd
1.72
the values shown in below table
THI is loaded with one of
2. The
data transter.
baud rate for serial
3. The SCON register is loaded withthe value 50H, indicating serial mode
and stop bits.
where an 8-bit data
is framed with start
start timer-1.
4. TRI is set to lto
is cleared by the "CLR TI" instruction.
6.5. ItThe character byte to be transferred serially 1S WTItten into the SEBUF

register. instruction **
monitored with the
use of the JNB TI, xX"
7. The TI flag bit is transferred completely.
character has been
to see if the
character, go to Step ).
8. To transfer the next
Register Values for various Baud Rates
Tablel.2. Timer 1 THI
THI(Decimal) THI(Hex)
Baud Rate
FD
-3
9600 FA
4800 -6
F4
2400 -12
E8
1200 -24

Programming the 8051 to Receive Data Serially

steps are to be taken to receive character bytes serially.

The following
register is loaded with the value 20H, indicating the use of
1. The TMOD
auto-reload) to set the baud rate.
Timer 1 in mode 2 (8-bit
rate
values in Table 10-4 to set the baud
2. THI is loaded with one of the
(assuming XTAL = 11.0592MHz).
value 50H, indicating serial mode 1.
3. The SCON register is loaded with the
where 8-bit data is framed with start and stop bits
and receive enable is
turned on.
4. TR1 is set to 1to start Timer 1.
5. RIis cleared with the "CLR RI" instruction.
6. The RIflag bit is monitored with the use of the instruction "JNB RI, Xx" to
see if an entire character has been received yet.
7. When RI is raised, SBUF has the byte. Its contents are moved into a safe
place.
 1.73
8- Bii Embedded Processor

8. To receive the next character, go to Step 5.

1.17. INTERRUPT PROGRAMMING

are two ways to do that

A single microcontroller can serve several devices. There

1. InterTupts
2. Polling
device notifies
the interrupt method, whenever any device needs its service, the
In
microcontroller by sending it an interrupt signal. Upon receiving an interrupt
the
doing and serves the device. The
signal, the microcontroller interrupts whatever it is
interrupt service Routine ((SR) or
program associated with the interrupt is called the
interrupt handler.
status of a given
InPolling method, the microcontroller continuously monitors the
device. When the status condition is met, it performs the service. After
that, it moves
can mnonitor the
on to monitor the next device until each one is serviced. Polling
met, it is
status of several devices and serve each of them as certain conditions are
not an efficient use of the microcontroller.
Interrupts Vs Polling

The advantage of interrupt is the microcontroller can serve many devices and each
device can get the attention of the microcontroller based on the priority assigned to it.
The polling method cannot assign priority because it checks all devices in a
round-robin fashion.

In the interrupt method, the microcontroller can also ignore a device request for
service. But this is not possible with the polling method.
The polling method wastes much of the microcontroller time by polling devices
that do not need service. So in order to avoid such things, the interrupt method is
used.

Interrupt Vector Table

For every interrupt, there must be an interrupt service routine (ISR) or interrupt
handler. When an interrupt is invoked, the microcontroller runs the interrupt service
routine.
 Embedded S
1.74| Systems and
memory that holds the
For every interrupt, there is a fixed location in
its ISR. The group of memory locations set to
hold the addresses of ISRs address y
interrupt vector table
called the
1.17.1. SOURCES OF INTERRUPT
interrupts can be
The 8051has five interrupt sources. Each of these
to two priority levels. The interrupt sources are
programmea
Destination
S.No Source
1. INTO External request from P3.2 pin.

2.
Overflow from Timer 0 activates the Interrupt Request
Timer 0
Flag TFO
3. INTI External request from P3.3
4
Overflow from Timer l activates the Interrupt Request
Timer 1
Flag TF1.
5.
Serial Completion of transmission or reception ofa serial frame
port activates the flags T1 or R1.
Each of these interrupt sources can be individually enabled or disabled by sett
or clearing a Interrupt Enable Register (IE).
All these sources can be programmed either to a high priority level or to a
low priority level by setting or clearing the Interrupt Priority Register (IP)
$ Low priority source can be interrupted by another high priority interrupL
But high priority interrupt cannot be interrupted by another high or low
priority interrupt.
Priority of interrupts
Source Priority Level
External interrupt 0 Highest
Timer 0 overflow

External interrupt I
Timer 1 overflow.
Serial port Lowest
 |1.75|

Processor
- Bit Embedded cycle and
during cach machine
Scanned
All these interrupts are separately
are prioritized by S6 of any machine cycle.
all the interrupts state of the next
service in the first
go to the interrupt
The process will of the following instructions.
blocked by any
machine cycle. It is not already in progress.
level is
higher priority
1. An interrupt of equal or instruction in
will be responded to until the
request
2. No interrupt
progress is completed.
In this case, the
instruction in progress is RETl or IE or IP.
3 The at least one more
response will come only after executing
instruction.

Response Time
factor in control
to an external interrupt is a very critical
The response time
required.
applications where an immediate action is
three cases or
response time will depend on the above-mentioned
The
conditions.
not blocked by any of the above three conditions, then
Once an interrupt is
processor, after the program
a hardware call is generated internally by the
branches to a predefined location.
Interrüpt Control Registers
registers such as
& The Interrupt Request Flags are in two different
1. IE Interrupt Enable Register.
2. IP Interrupt Priority Register.
External interrupts control bits are in two formats.
ITO in TCON-0
ITI in TCON -2
Control bits are set or cleared by software.

IE: Interrupt Enable Register

6 5 4 m
2 1

EA X ES ET1EX1 ETO EX0

 Embedded
1.76
Systems and Io
If EA =0 all interrupts are disabled and if EA = l each interrupt can

3 individually set orPortcleared.

IfES=0 Serial interrupt is disabled andif ES = 1, serial port intermug

is enabled.
* IfETl =0, timer 1 interrupt is disabled and if ETI = 1, timer intermup

enabled.
If EXI = 0, the External Interrupt is disabled and if EX1 -\,i

enabled.
IfET0 =0, the Timer 0Interrupt is disabled and if ETO =1, it tis enabled,
If EX0 = 0, the External Interrupt 0 is disabled and if EXO = 1, it i

enabled.

IP: Interrupt Priority Register

4 3 2 1 0
6 5
PSPT1PX0|PTO PX0|
X X X

PS =1 programs it to the higher

PS Serial Port interrupt priority level.
priority level.
PTI =1 programs it to the
PTI- Timer l interrupt priority level.
higher priority level.
PX1= 1 programs it to the
PXI External Interrupt 1priority level.
higher priority level.
PTO =1 programs it to the
* PTO Timer 0 interrupt priority level.
higher priority level.
PX0= 1 programs it to the
PXOExternal Interrupt Oprioritylevel.
higher priority level.
software.
The bits of these registers can be set or cleared by
Interrupt Request Flag and location
Interrupt Request Location
Interrupt Source
INTO ifITO = 0 P3.2
External interrupt 0
IEO, if ITO = 1 TCON.1
 |1.77
Processor
8- Bit Embedded
TCON.S
Timer 0 overflow TFO
P3.3
ENTO, ifITI=0,
External interrupt 1 TCON.7
IE1, if IT| =1
TCON.7
Timer 1 overflow TF1
T1(during transmission) SCON.I
Serial Port SCON.0
RI(during reception
Steps in Executing an Interrupt
microcontroller goes through the following
Upon activation of an Interrupt, the
steps.
the address of the next
1. It finishes the instruction it is executing and saves
instruction (PC) on the stack.
2. It also saves the current status of all interrupts internally.
that
3. It jumps to a fixed location in memory called interrupt vector table
holds the address of the interrupt service routine.
4. The microcontroller gets the address of the ISR from the interrupt vector
table and jumps to it. It starts to execute the interrupt service subroutine,
until it reaches the last instruction of the subroutine, which is RETI.
5. Upon executing the RETIinstruction, the microcontroller returns to the
place where it was interrupted.
(a) First, it sets the program counter address from the stack by popping
the top two bytes of the stack into the PC.
(b) It starts to execute from that address.
Steps in enabling Interrupt
1. Bit D7 of the IE register (EA) must be set to high to allow the rest of
register to take effect.
2. If EA = 1, interrupts are enabled and will be responded to if their
corresponding bits in IE are high.
3. IfEA = 0, no interrupt will be responded to, even if the associated bit in
the IE register is high.
 Embedded.
1.78 Systems and y
1.17.2. EXTERNAL HARDWARE INTERRUPTS
interrupts such as
Ihe 8051has two external hardware
1. INT0
2. INTI
0013H location in
These two Interrupts are having 0003H and
table and it can be enabled and disabled using the IE registers.
There are
interrupt Vecu,
two types
activation for the external hardware interrupts.
1. Level triggered
2. Edge triggered
1.17.2.1. Level Triggered Interrupts
In the level triggered mode, INTO and INTI pins are normally high and if
a ow.
level signal is applied to them, it triggers the interrupt. Then the
microcontrol e;
stops whatever it is doing and jumps to the interrupt vector table to service
the
interrupt. This is called level triggered or level activated interrupt.
The low level signal at the INT pin must be removed before the
last instruction
execution of the
of the interrupt service routine (RETI) otherwise another
will be generated. interrup
1.17.2.2. Edge Triggered Interrupts
To make INTO and INTI into edge triggered interrupts, We must
program the bits
of the TCON register. In TCON register bits ITO and ITI Flag bits
determine level
edge triggered mode of the hardware interrupts.
ITO ITI External Interrupt
Low level Triggered
1
Edge Triggered

D,
TFI TRI TFO
Do
TRO IEI ITI IEO ITO
 1.79

8- Bit Embedded Processor

hardware when the
overflow flag. Set by
TCON.7 Timer 1 as the
TF1 overflows. Cleared by hardware
Timer/Counter 1
routine.
interrupt service
to the
processor vectors
Setcleared by software to turm
TRI TCON.6 Timer 1 run control bit.
Timer/Counter 1ON/ OFF.
the
overflow flag. Set by hardware when
TCON.5 Tímer 0
TFO Cleared by hardware as the
Timer/Counter 0 overflows.
routine.
processor vectors to the service
Set/cleared by software to
turn
TCON. 4 Timer 0 run control bit.
TRO
Timer/Counter 0 ON/OFF.
Set by CPU when
IE1 TCON. 3 External Interrupt 1 edge flag.
Interrupt edge is detected. Cleared by CPU
External
This flag does not latch
when interrupt is processed.
low-level triggered interrupts.
by software to
ITI TCON. 2 Interrupt 1type control bit. Set/cleared
External
specify falling edge/low level triggered
Interrupt.
CPU when
IE0 TCON, 1 External Interrupt 0 edge flag. Set by
when
External Interruptedge detected. Cleared by CPU
low-level
interrupt is processed. This flag does not latch
triggered interrupts.
ITO TCON. 0 Interrupt.0type control bit. Set/cleared by software to
External
specify falling edge/low level tnggered
Interrupt.
1.17.3. SERIAL COMMUNICATION INTERRUPT
Serial Communication Interrupt can be obtain using RI and TI flags of SBUF
register. TI is raised when the last bit of the framed data, the stop bit is transferred
indicating that the SBUF register is ready to transfer the next byte.
RI is raised when the entire frame of data, including the stop bit is received. In
8051only one interrupt is set for serial communication. This interrupt is used to both
send and receive data.