MOS Inverter

Ideal Inverter

• A is the input variable and B is the output variable for inverter.

• Using positive logic system , logic ‘1’ represents high voltage and logic ‘0’
represents low voltage.
 VTC of an Ideal Inverter

• The voltage Vth is known as the inverter threshold voltage.

• For any input voltage between 0 and Vth = VDD/2, the output voltage is
equal to VDD (logic “1”).
• When input voltage is equal to Vth , the output switches from VDD to 0.
• For any input voltage between Vth and VDD, the output voltage is equal to 0
(logic ‘0’).
• The DC characteristics of actual inverter circuits will differ in various degree
from the ideal characteristics
Generalized circuit structure of an
nmos inverter
 Generalized circuit structure of an
nMOS Inverter
• The input voltage (Vin) of the inverter circuit is gate-to-source voltage (VGS) of the
nMOS transistor.
• The output voltage (Vout) of the circuits is equal to the drain-to-source voltage (VDS).

• The source and substrate terminals of the nMOS transistor are connected to ground
potential. Hence the source to substrate voltage is VSB = 0.
• In this generalized representation, the load device is represented as a two terminal
circuit element with terminal current IL and terminal Voltage VL.
• One terminal of the load is connected to the drain of the n- channel MOSFET., while
the other terminal is connected to VDD.
• The characteristics of the inverter circuit depend upon the type and the characteristics
of the load device.
• The output terminal of the inverter shown in figure is connected to the input of another
MOS inverter.
• The next circuit seen by the output node can be represented as a lumped
capacitance, Cout.
• Since the DC gate current of an MOS transistor is negligible, there will be no current
flow into or out of the input and output terminals of the inverter in DC steady state.
Voltage Transfer Characteristics of
generalized nMOS inverter
VTC of Generalized nMOS Inverter
• Using KCL, load current is always equal to the nMOS drain current.
I D (Vin, Vout) = IL (VL)
• The voltage transfer charcteristic describing Vout as functioin of Vin under
DC condition.
• The general shape of the VTC is similar to that of the ideal inverter transfer
characteristic.
• For very low input voltage levels, the output voltage Vout is equal to the high
value of VOH (output high voltage).
• The driver transistor is in cut-off, and does not conduct any current.
The voltage drop across the load device is very small in magnitude,
and output voltage level is high.
• As the input voltage Vin increases, the driver transistor starts conducting a
certain drain current, and the output voltage starts to decrease.
• This drop in the output voltage level occur gradually with a finite slope.
• We get two critical voltage points on this curve, where the slope of Vout
characteristics becomes equal to -1, i.e
 VTC of Generalized nMOS Inverter
• The smaller input voltage value satisfying this condition is called the input low voltage V IL, and larger input
voltage satisfying this condition is called the input high voltage VIH.
• As input voltage is further increased, the output voltage continues to drop and reaches a value of VOL (out
put low voltage) when the input voltages is equal to VOH.
• The inverter threshold voltages is defined as the point where Vin= Vout on
the VTC.
• Thus a total five critical voltages VOL, VOH, VIL,VIH, and Vth, characterize
the DC input-output voltage behavior of the inverter circuit, noise margin and
the width location of the transition region.
• The functional definitions for the first four of these critical voltage are given
below.
Noise Margin and Noise
Immunity
 Noise Margin and Noise
Immunity
• The noise margins of a digital gate or circuit indicate how
well the gate will perform under noisy conditions. The
noise margin for the high logic levels is given by
NMH= VOH - VIH
• The noise margin for the low logic levels is given by
NM L = VIL - VOL
• For VDD =5 V the ideal noise margins are 2.5 V; that is,
NML =NMH =VDD/2.
• The noise Immunity of a digital circuit is defined as ability
of a circuit to reject the noise. The noise immunity of the
circuit increases with Noise Margin.
 Graphical representation of
Noise Margin

• Input Voltage range between VIL and VIH may consider either as a logic “0”
or as a logic “1” input by the inverter.
• This region is called transition region or uncertain region.
• Ideally the slope of the voltage transfer characteristics should be very large
between VIL and VIH, because a narrow transition region allows for larger
noise margin
• Reducing the width of the uncertain region is one of the most important
design objectives.
 Power Consideration
• In VLSI chip designing there are millions of gates in the ckt and each gate ckt
Dissipates power during its operation.
• So removal of such heat or power dissipation is become an essential issue.
 Area Consideration
• To reduce chip area used by the inverter ckt, we need to
reduce the size of MOS transisor used in the circuit.
• For practical measure, we use gate area of the MOS
transistor. i.e. the product of W and L.
• An MOS transistor has minimum area when both of the
gate dimensions are made as small as possible.
• It follows that the ratio of the gate width to gate length
W/L should be a close to unity to achieve minimum
transistor area.
• This requirement usually create other design problems
like noise margins, the output current driving capability
 Inverters with n-Type MOSFET Load
• The resistive-load inverter circuit is not a suitable candidate for most
digital VLSI system applications, primarily because of the large area
occupied by the load resistor.
• Inverter circuits which use an nMOS transistor as the active load
device, instead of the linear load resistor has following advantages:
1. Silicon area occupied by the transistor is usually smaller than that
occupied by a comparable resistive load.
2. Moreover, inverter circuits with active loads can be designed to
have better overall performance compared to that of passive-load
inverters
 Saturated Enhancement-load Inverter
The circuit configurations of two inverters
with enhancement-type load devices are
depending on the bias voltage applied to
its gate terminal,

The load transistor can be operated either

in the saturation region or in the linear
region.
linear Enhancement-load Inverter
 Saturated Enhancement-load Inverter
● Inverter is always biased in the linear region.
● Thus, the VOH level is equal to VDD, resulting in higher noise
margins compared to saturated enhancement-load inverter.
● The most significant drawback of this configuration is the use of two
separate power supply voltages.
● In addition, both types of inverter circuits suffer from relatively high
stand-by (DC) power dissipation.
● hence, enhancement-load nMOS inverters are not used in any
large-scale digital applications.
 Depletion-load NMOS Inverter:
Several of the disadvantages of the
enhancement-type load inverter can be
avoided by using a depletion-type nMOS
transistor as the load device.
 Depletion-load NMOS Inverter:
● The fabrication process for producing an inverter with an
enhancement-type nMOS driver and a depletion-type nMOS load
is slightly more complicated.
● And requires additional processing steps, especially for the
channel implant to adjust the threshold voltage of the load
device.
● The resulting improvement of circuit performance and
integration possibilities, however, easily justify the additional
processing effort required for the fabrication of depletion-load
inverters.
 Depletion-load NMOS Inverter:
The immediate advantages of implementing this circuit configuration
are:
(i) sharp VTC transition and better noise margins,
(ii) single power supply, and
(iii) smaller overall layout area.
 Depletion-load NMOS Inverter:
● The circuit diagram of the depletion-load inverter circuit is shown in Fig. and a
simplified view of the circuit consisting of a nonlinear load resistor and a
nonideal switch (driver).

● The driver device is an enhancement-type nMOS transistor, with VT0 driver > 0,
● whereas the load is a depletion-type nMOS transistor, with VT0 load < 0.

● The current-voltage equations to be used for the depletion-type load

transistor are identical to those of the enhancement-type device, with the
exception of the negative threshold voltage.
 Depletion-load NMOS Inverter:
The gate and source terminal of load are connected; So, VGS = 0.
Thus, the threshold voltage of the load is negative.
Hence, 𝑉𝐺𝑆,𝑙𝑜𝑎𝑑 > 𝑉𝑇,𝑙𝑜𝑎d
Therefore, load device always has a conduction channel regardless of input
and output voltage level.
When the load transistor is in saturation region, the load current is given by
When the load transistor is in saturation region, the load current is given by

When the load transistor is in linear region, the load current is given by
Calculation of VOH
Calculation of VOL
VIL
Variation of the Inversion Threshold Voltage
as a function of kR.
Design of CMOS
VTC
 Advantages of CMOS Technology
1.Low power consumption
2.Symmetrical swing
3.Self isolated devices
4.Packing density high
5.Full logic swing
6. Sharp VTC
7.Better noise margin
8.Substrate bias effects are minimum
9.Offers more flexibility to Designer due to availability of both types of
Transistors NMOS and PMOS
Layout of CMOS Inverter
 Cascaded CMOS Inverter

• The capacitances Cgd and Cgs are primarily due to gate overlap with diffusion.
• C db and C sb are voltage-dependent junction capacitances.
• The capacitance component Cg is due to the thin-oxide capacitance over the gate
area.
• The lumped interconnect capacitance Cint which represents the parasitic capacitance
contribution of the metal or polysilicon connection between the two inverters.
• We combine the capacitances seen in figure into an equivalent lumped linear
capacitance, connected between the output node of the inverter and the ground.
 Cascaded CMOS Inverter
• Csb,n and Csb,p have no effect on the transient behavior of the circuit since
the source-to-substrate voltages of both transistors are always equal to
zero.
• The capacitances Cgs,n and Cgs,p are also not included in equation
because they are connected between the input node and the ground (or
the power supply).
First-stage CMOS inverter with Lumped
output Load Capacitance
 Delay-Time Definitions

The propagation delay times TpHL and TpLH determine the input-to-output signal delay during the
high-to-low and low-to-high transitions of the output, respectively.

TpHL is the time delay between the V50%-transition of the rising input voltage and the V50%-transition of
the failing output voltage.
TpHL = t1- t0
TpLH is defined as the time delay between the V50%-transition of the falling input voltage and the
V50%-transition of the rising output voltage.
TpLH = t3- t2
The average propagation delay Tp of the inverter is the average time required for the input signal to
 Rise Time and Fall Time

• The rise time is defined here as the time required for the output
voltage to rise from the V10% level to V90%, level.
Trise = tD- tC
• The fall time Tfall is defined here as the time required for the output
voltage to drop from the V level to V level.
Calculation of delay time
 CMOS Ring Oscillator

• The cascade connection of three identical CMOS inverters, as shown in Figure where the output
node of the third inverter is connected to the input node of the first inverter.
• As such, the three inverters form a voltage feedback loop.
• This circuit does not have a stable operating point.
• The only DC operating point, at which the input and output voltages of all inverters are equal to the
logic threshold Vth, is inherently unstable in the sense that any disturbance in node voltages would
make the circuit drift away from the DC operating.
• A closed-loop cascade connection of any odd number of inverters will display astable behavior; i.e.,
such a circuit will oscillate once any of the inverter input or output voltages deviate from the unstable
operating point, Vth. Therefore, the circuit is called a ring oscillator.
 CMOS Ring Oscillator

• As the output voltage V1 of the first inverter stage rises from VOL, to VOH, it triggers the second inverter
output V2 to fall, from VOH to VOL.
• The difference between the V50%-crossing times of V1 and V2 is the signal propagation delay TpHL2. of
the second inverter.
• As the output voltage V2 of the second inverter falls, it triggers the output voltage V3 of the third
inverter to rise from VOL to VOH.
• The difference between the V50% -crossing times of V2 and V3 is the signal propagation delay TPLH3, of
the third inverter.
• It can be seen from Figure that each inverter triggers the next inverter in the cascade connection, and
the last inverter again triggers theTfirst.
= TPHL1+ TPLH 1 +
thus sustaining TPHL2+TPLH2+
the oscillation. TPHL3 + TPLH3
• = 2Tp +2Tp
In this three-stage circuit, the oscillation period+2
T Tp
of any of the inverter output voltages can be
=3•2Tp =6Tp
Calculation of Interconnect Delay
RC Delay Models
Elmore Delay
 Switching Power Dissipation
of CMOS Inverters

• During switching events where the output load capacitance is alternating

charged up and charged down, on the other hand, the CMOS inverter
inevitably dissipates power
 Typical input and output voltage
Waveforms and the Capacitor Current
Waveform

• When the input voltage switches from low to high, the pMOS transistor in the circuit is turned off, and the
nMOS transistor starts conducting.
• During this phase, the output load capacitance Cload is being discharged through the nMOS transistor.
Thus, the capacitor current equals the instantaneous drain current of the nMOS transistor.
• When the input voltage switches from high to low, the nMOS transistor in the circuit is turned off, and the
pMOS transistor starts conducting.
• During this phase, the output load capacitance Cload is being charged up through the pMOS transistor;
therefore, the capacitor current equals the instantaneous drain current of the pMOS transistor.
 • Assuming periodic input and output waveforms, the average power dissipated by any device over one
period can he found as follows;

• Since during switching, the nMOS transistor and the pMOS transistor in a CMOS inverter
conduct current for one-half period each, the average power dissipation of the CMOS inverter
can be calculated as the power required to charge up and charge down the output load
capacitance.

• The average power dissipation of the CMOS inverter is proportional to the switching frequency f .
• Therefore, the low-power advantage of CMOS circuits becomes less prominent in high-speed operation, where
the switching frequency is high.
Also note that the average power dissipation is independent of all transistor characteristics and transistor sizes.
Generalized CMOS