SystemVerilog Module 5: Randomization and Functional Coverage (Easy and Detailed)
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Module 5A: Randomization
Introduction to Randomization
- As designs get larger, it becomes impossible to manually write testcases for every situation.
- Constrained-Random Testing (CRT) solves this by generating tests automatically, with random values but
within meaningful constraints.
- CRT uses:
- Random stimulus
- Constraints to guide random values.
- Functional coverage to check how much functionality is tested.
- Key benefit: Once a CRT environment is built, hundreds of tests can be run automatically.
What to Randomize?
- Control points must be randomized, not just data fields.
- Important areas:
- Device configurations
- Environment setups
- Input data
- Layers of encapsulated data
- Protocol errors
- Delays and synchronizations
Example: Randomizing bus packet delays uncovers timing bugs that fixed tests might miss.
Randomization in SystemVerilog
- Random variables use rand and randc keywords.
- rand -> normal random
- randc -> cycle through all values without repetition
- Constraints are used to limit randomization to legal values.
Example:
class Packet;
rand bit [7:0] src, dst;
constraint valid { src < dst; }
endclass
- Always check randomization success with if (!randomize()) $fatal();
Random Number Functions
- $random -> signed 32-bit random number
- $urandom -> unsigned 32-bit random number
- $urandom_range(low, high) -> random value within a range
Example:
$urandom_range(10, 100); // Returns a number between 10 and 100
Common Randomization Problems
- Avoid signed variables unless needed -> use unsigned for clarity.
- Large arrays -> use $urandom instead of solver for better speed.
- Prefer bit operations (>>, <<) over expensive operations (*, /, %).
Random Number Generators
- SystemVerilog uses a pseudo-random number generator (PRNG).
- Each object/thread has a separate PRNG to ensure random stability.
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Module 5B: Functional Coverage
Why Functional Coverage?
- Measures how much of the design features have been tested.
- Important even for directed tests.
- Helps guide verification progress.
Diagram: Feedback loop
Tests -> Coverage Collection -> Analyze Holes -> Refine Tests -> Repeat
Types of Coverage
- Code Coverage: Measures RTL lines, paths, toggles, FSM states.
- Functional Coverage: Measures design intent and behaviors.
- Assertion Coverage: Measures properties and constraints.
- Cross Coverage: Combination of two or more points.
Gathering Coverage Data
- Each simulation run creates a database.
- Merge data from multiple runs with different seeds.
- Only pass/fail simulations count; discard failed test coverage.
Simple Functional Coverage Example
- Create covergroup with coverpoints.
- Coverpoints: Variables to monitor.
- Covergroups: Group of coverpoints sampled together.
Example:
covergroup cg;
coverpoint dst;
endgroup
Anatomy of Cover Group
- Cover points
- Options
- Trigger (when to sample)
Triggering a Cover Group
- Use .sample() manually.
- Use event or assertion based automatic sampling.
Data Sampling
- Bins: Groups of value ranges
- Automatically created for small variables (2^N bins for N-bit variable).
- Can limit bins using auto_bin_max.
Creating and Naming Bins
- Explicit bin naming for clarity.
- ignore_bins to exclude values.
- illegal_bins to flag illegal values.
Cross Coverage
- Measures combinations of cover points.
- Example: Transaction Type vs Destination.
Coverage Options
- Type Options: Apply to all instances.
- Instance Options: Apply to one covergroup.
Analyzing Coverage
- Check bug rates.
- If coverage stalls, add new constraints or tests.
Measuring Coverage During Simulation
- Some simulators allow real-time coverage updates.
- Use this to dynamically adjust test focus.
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Quick Summary
| Topic | Key Points |
|-------------------------|------------|
| Randomization | Create random stimuli with constraints |
| Functional Coverage | Check how much of design spec is verified |
| Code Coverage | Check how much RTL code is tested |
| Cross Coverage | Measure combination of variables |
| Good Practices | Always check randomize success, carefully plan coverage |
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Final Tip
Functional Coverage and Randomization together make a powerful pair for full verification of large VLSI
designs!
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End of Notes
