ST7260xx

Low speed USB 8-bit MCU family with up to 8K Flash

and serial communications interface

Features
■ Memories
– 4 or 8 Kbytes program memory: high
density Flash (HDFlash), or FastROM with
s )
readout and write protection
– In-application programming (IAP) and in-
SO24 QFN40

c
(6x6) t(
circuit programming (ICP)
d u
– 2 very high sink true open drain I/Os (25
– 384 bytes RAM memory (128-byte stack) mA at 1.5 V)
r o
■ Clock, reset and supply management
– Run, Wait, Slow and Halt CPU modes P
– Up to 8 lines with interrupt capability

e
– 12 or 24 MHz oscillator
■ 2 timers

le t
– Programmable Watchdog
– RAM Retention mode
o
– 16-bit Timer with 2 Input Captures, 2
s
■
– Optional low voltage detector (LVD)
USB (Universal Serial Bus) interface
O b Output Compares, PWM output and clock
input
– DMA for low speed applications compliant
with USB 1.5 Mbs (version 2.0) and HID
) - ■ Communications interface

specifications (version 1.0)

t ( s – Asynchronous serial communications
interface (SCI)

transceivers
u c
– Integrated 3.3 V voltage regulator and ■ Instruction set

o d
– Supports USB DFU class specification
– 63 basic instructions

P r
– Suspend and Resume operations
– 3 Endpoints with programmable In/Out
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction

e
let
■ Development tools
configuration
– Versatile development tools including ,
■ Up to 19 I/O ports

s o
– Up to 8 high sink I/Os (10 mA at 1.3 V)
software library, hardware emulator,
programming boards, HID and DFU

Ob
Table 1. Device summary
software layer

Features ST7260K2 ST7260K1 ST7260E2 ST7260E1

Flash program memory -

8K 4K 8K 4K
bytes
RAM (stack) - bytes 384 (128)
Peripherals Watchdog timer, 16-bit timer, USB, SCI
Operating supply 4.0 V to 5.5 V
CPU frequency 8 MHz (with 24 MHz oscillator) or 4 MHz (with 12 MHz oscillator)
Operating temperature 0 °C to +70 °C
Packages QFN40 (6x6) SO24

February 2009 Rev 3 1/139

www.st.com 139
 Contents ST7260xx

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

s )
5 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
c t(
5.1
d u
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
r o
5.2
5.3
e P
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3.1
le t
Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.4
s o
ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.5
O b
ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.6 -
IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
)
5.7
( s
Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
t
5.7.1
c
Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
u
o d
6
6.1 P r
Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

e t
6.2e Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

o l 6.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

b s 6.3.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

O 6.3.2
6.3.3
Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.3.4 Condition code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.3.5 Stack pointer register (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7 Reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2 Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2.1 Watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2.2 External reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2/139
 ST7260xx Contents

7.3 Clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.3.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.0.1 Interrupt register (ITRFRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

9 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

s )
t(
9.2 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.3
c
Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
u
9.4
d
Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
o
10 P r
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
t e
le
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.2
o
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
s
10.2.1
10.2.2 O b
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10.2.3
) -
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10.2.4
t ( s
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.2.5
u c
Data register (PxDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.2.6
o d Data direction register (PxDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

P r 10.2.7 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

11
e t e
Miscellaneous register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

o l
b
12 s Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
O 12.1
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12.3.1 Software watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12.3.2 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12.3.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
12.3.4 Using Halt mode with the WDG (option) . . . . . . . . . . . . . . . . . . . . . . . . 46
12.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
12.3.6 Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

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 Contents ST7260xx

12.4 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

12.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12.4.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
12.4.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
12.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
12.4.6 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
12.4.7 16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

13 Serial communications interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . 71

s )
13.1
c t(
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
13.2
d u
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
13.2.1
r o
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
13.2.2 P
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
e
13.2.3
le t
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
13.2.4
o
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
s
13.3
13.3.1
O b
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Status register (SCISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
13.3.2
) -
Control register 1 (SCICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
13.3.3
t ( s
Control register 2 (SCICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
13.3.4
u c
Data register (SCIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
13.3.5
o d Baud rate register (SCIBRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

14 P r
USB interface (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

e te
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

o l
b s 14.2
14.3
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
O 14.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
14.4.1 DMA address register (DMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
14.4.2 Interrupt/DMA register (IDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
14.4.3 PID register (PIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
14.4.4 Interrupt status register (ISTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
14.4.5 Interrupt mask register (IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
14.4.6 Control register (CTLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
14.4.7 Device address register (DADDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
14.4.8 Endpoint n register A (EPnRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

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 ST7260xx Contents

14.4.9 Endpoint n register B (EPnRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

14.4.10 Endpoint 0 register B (EP0RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
14.5 Programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
14.5.1 Initializing the registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
14.5.2 Initializing DMA buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
14.5.3 Endpoint initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
14.5.4 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

15 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

s )
t(
15.1 ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
15.1.1
c
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
u
15.1.2
d
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

o
15.1.3
15.1.4 P r
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
15.1.5
t e
Indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
15.1.6
o le
Indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
15.1.7
b s
Relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
15.2
O
Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
-
16
( s )
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
16.1 c t
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
16.1.1
d u Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
o
Pr
16.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

e t e 16.1.3
16.1.4
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

s ol 16.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

O b 16.2
16.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
16.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
16.3.2 Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . 113
16.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
16.5 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
16.5.1 General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
16.5.2 Control timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
16.5.3 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
16.6 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

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16.6.1 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

16.6.2 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
16.7 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
16.7.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 118
16.7.2 Designing hardened software to avoid noise problems . . . . . . . . . . . . 118
16.7.3 Electro magnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . 119
16.7.4 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 119
16.7.5 Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
16.8 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
s )
16.8.1
16.8.2
c t(
General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
16.9
d u
Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
16.9.1 r o
Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
16.9.2
e P
USB - universal bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
16.9.3
le t
SCI - serial communications interface . . . . . . . . . . . . . . . . . . . . . . . . . 128

s o
17
17.1 O b
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
17.1.1
) -
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

t ( s
18 c
Device configuration and ordering information . . . . . . . . . . . . . . . . . 131
u
18.1 d
Option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
o
18.2
P r Device ordering information and transfer of customer code . . . . . . . . . . 132

te
18.3

e
Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

o l
19
b s Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
19.1 PA2 limitation with OCMP1 enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
O 19.2 Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
19.3 SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

20 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

6/139
 ST7260xx Description

1 Description

The ST7260xx devices are members of the ST7 microcontroller family designed for USB
applications running from 4.0 to 5.5 V. Different package options offer up to 19 I/O pins.
All devices are based on a common industry-standard 8-bit core, featuring an enhanced
instruction set and are available with Flash program memory. The ST7 family architecture
offers both power and flexibility to software developers, enabling the design of highly
efficient and compact application code.
The on-chip peripherals include a low speed USB interface and an asynchronous SCI
interface. For power economy, the microcontroller can switch dynamically into, Slow, Wait,
Active Halt or Halt mode when the application is in idle or stand-by state.
s )
Typical applications include consumer, home, office and industrial products.
c t(
d u
r o
e P
le t
s o
O b
) -
t ( s
u c
o d
P r
e t e
o l
b s
O

7/139
Block diagram ST7260xx

2 Block diagram

Figure 1. General block diagram

INTERNAL
CLOCK
OSCIN OSC/3
OSCILLATOR
OSCOUT
OSC/4 or OSC/2
for USB1) PORT A

s )
t(
VDD PA[7:0]
POWER
(8 bits)
VSS SUPPLY
16-bit TIMER
u c
WATCHDOG

o d
r
PORT B PB[7:0]

ADDRESS AND DATA BUS

P
RESET CONTROL (8 bits)

8-BIT CORE
t e
le
ALU

LVD
s o
USB DMA
O b PORT C

VPP/TEST PROGRAM
) - SCI
(UART)
PC[2:0]
(3 bits)

VDDA
t ( s
MEMORY
(8 Kbytes)

VSSA
u c USB SIE USBDP
USBDM

o d RAM
(384 bytes) USBVCC

P r
e t e
o l
bs
1) 12 or 24 MHz OSCIN frequency required to generate 6 MHz USB clock.

8/139
ST7260xx Pin description

3 Pin description

Figure 2. 40-lead QFN package pinout

PA1(25 mA)/ICCDATA

PA2(25 mA)/ICCCLK
NC
NC
NC
NC
NC
NC
NC
NC
s )
t(
40 39 38 37 36 35 34 33 32 31
PA0/MCO 1 30 PA3/EXTCLK
VSSA 2 29

u c
PA4/ICAP1/IT1
USBDP 3 28

o d
PA5/ICAP2/IT2

r
USBDM 4 27 PA6/OCMP1/IT3
USBVCC
VDDA
5

e P
26

25
PA7/OCMP2/IT4
PB0(10 mA)
VDD 7

e t 24 PB1(10 mA)

ol
OSCOUT 8 23 PB2(10 mA)

bs
OSCIN 9 22 PB3(10 mA)
VSS 10 21 PB4(10 mA)/IT5

-O
11 12 13 14 15 16 17 18 19 20

)
VPP/TEST
IT6/PB5(10 mA)
IT7/PB6(10 mA)
RDI/PC0
USBOE/PC2
TDO/PC1

RESET

NC
NC
IT8/PB7(10 mA)

( s
u ct
Note: NC=Do not connect

o d
P r
Figure 3. 24-pin SO package pinout

e
let
VDD 1 24 USBVcc
OSCOUT 2 23 USBDM

so
OSCIN 3 22 USBDP
VSS 4 21 VSSA

Ob
TDO/PC1 5 20 PA0/MCO
RDI/PC0 6 19 PA1(25 mA)/ICCDATA
RESET/ 7 18 PA2(25 mA)/ICCCLK
IT7/PB6(10mA) 8 17 PA3/EXTCLK
VPP/TEST 9 16 PA4/ICAP1/IT1
PB3(10 mA) 10 15 PA5/ICAP2/IT2
PB2(10 mA) 11 14 PA7/OCMP2/IT4
USBOE/PB1(10 mA) 12 13 PB0(10 mA)

9/139
 Pin description ST7260xx

RESET (see Note 1): Bidirectional. This active low signal forces the initialization of the MCU.
This event is the top priority non maskable interrupt. This pin is switched low when the
Watchdog is triggered or the VDD is low. It can be used to reset external peripherals.
OSCIN/OSCOUT: Input/Output Oscillator pin. These pins connect a parallel-resonant
crystal, or an external source, to the on-chip oscillator.
VDD/VSS (see Note 2): Main power supply and ground voltages.
VDDA/VSSA (see Note 2): Power supply and ground voltages for analog peripherals.
Alternate functions: Several pins of the I/O ports assume software programmable
alternate functions as shown in the pin description.
Note: 1 Note 1: Adding two 100 nF decoupling capacitors on the Reset pin (respectively connected
to VDD and VSS) will significantly improve product electromagnetic susceptibility
s )
performance.
c t(
2
u
To enhance the reliability of operation, it is recommended that VDDA and VDD be connected
together on the application board. This also applies to VSSA and VSS.
d
3
r o
The USBOE alternate function is mapped on Port C2 in QFN40 devices. In SO24 devices it
is mapped on Port B1.

e P
4
t
The timer OCMP1 alternate function is mapped on Port A6 in QFN40 pin devices. In SO24
devices it is not available.
le
s o
Legend / abbreviations for Figure 2, Figure 3 and Table 2, Table 3:
Type: b
I = input, O = output, S = supply
O
-
In/Output level: CT = CMOS 0.3 VDD / 0.7 VDD with input trigger

)
Output level:
s
10 mA = 10 mA high sink (Fn N-buffer only)

t (
c
25 mA = 25 mA very high sink (on N-buffer only)

u
●
o d
Port and control configuration:

Pr
Input: float = floating, wpu = weak pull-up, int = interrupt
● Output: OD = open drain, PP = push-pull, T = True open drain

e t e
The RESET configuration of each pin is shown in bold. This configuration is kept as long as

ol
the device is under reset state.

b s
O

10/139
 ST7260xx Pin description

Table 2. Device pin description (QFN40)

Level Port / control
Main

Type
Input Output function

Output
Pin n° Pin name Alternate function

Input
(after

float

wpu
reset)

OD

PP
int
1 PA0/MCO I/O CT X X Port A0 Main Clock Output
2 VSSA S Analog ground
3 USBDP I/O USB bidirectional data (data +)
4 USBDM I/O USB bidirectional data (data -)

s )
t(
5 USBVCC O USB power supply
6 VDDA S
c
Analog supply voltage

u
7 VDD S
d
Power supply voltage (4V - 5.5V)

o
8
9
OSCOUT
OSCIN
O
I
P r
Oscillator output
Oscillator input
10 VSS S
t e Digital ground

le
so
11 PC2/USBOE I/O CT X X Port C2 USB Output Enable
SCI Transmit Data
12 PC1/TDO I/O CT

O b X X Port C1
Output

13 PC0/RDI I/O CT
) - X X Port C0
SCI Receive Data
Input

( s
ct
14 RESET I/O X X Reset
15
16
NC
NC
d u
--
--
Not connected
Not connected
o
Pr
17 PB7/IT8 I/O CT 10 mA X X X Port B7
18

e t e
PB6/IT7 I/O CT 10 mA X X X Port B6

ol
19 VPP/TEST S Programming supply
20 PB5/IT6 I/O CT 10 mA X X X Port B5

b s
21 PB4/IT5 I/O CT 10 mA X X X Port B4

O 22
23
PB3
PB2
I/O CT
I/O CT
10 mA
10 mA
X
X
X
X
Port B3
Port B2
24 PB1 I/O CT 10 mA X X Port B1
25 PB0 I/O CT 10 mA X X Port B0
Timer Output Compare
26 PA7/OCMP2/IT4 I/O CT X X X Port A7
2
Timer Output Compare
27 PA6/OCMP1/IT3 I/O CT X X X Port A6
1
28 PA5/ICAP2/IT2 I/O CT X X X Port A5 Timer Input Capture 2
29 PA4/ICAP1/IT1 I/O CT X X X Port A4 Timer Input Capture 1

11/139
 Pin description ST7260xx

Table 2. Device pin description (QFN40) (continued)

Level Port / control
Main

Type
Input Output function

Output
Pin n° Pin name Alternate function

Input
(after

float

wpu
reset)

OD

PP
int
30 PA3/EXTCLK I/O CT X X Port A3 Timer External Clock
31 PA2/ICCCLK I/O CT 25 mA X T Port A2 ICC Clock
32 NC -- Do not connect
33 NC -- Do not connect
34 NC -- Do not connect
s )
35 NC -- Do not connect
c t(
36 NC -- Do not connect
d u
37 NC --
r o
Do not connect
38 NC --

e P
Do not connect
39
40
NC
PA1/ICCDATA
--
I/O CT 25 mA X
le
T
t Do not connect
Port A1 ICC Data

s o
O b
) -
t ( s
u c
o d
P r
e t e
o l
b s
O

12/139
ST7260xx Pin description

Table 3. Device pin description (SO24)

Level Port / control
Main

Type
Input Output function

Output
Pin n° Pin name Alternate function

Input
(after

float

wpu
reset)

OD

PP
int
Power supply voltage
1 VDD S
(4 V - 5.5 V)

2 OSCOUT O Oscillator output

3 OSCIN I Oscillator input

s )
t(
4 VSS S Digital ground

5 PC1/TDO I/O CT X X Port C1

u c
SCI Transmit Data

o dOutput

6 PC0/RDI I/O CT X X
r
Port C0
P
SCI Receive Data
Input

7 RESET I/O X X
t e Reset

le
so
8 PB6/IT7 I/O CT 10 mA X X X Port B6

Ob
9 VPP/TEST S Programming supply

10 PB3 I/O CT 10 mA

) - X X Port B3

(s
11 PB2 I/O CT 10 mA X X Port B2

12 PB1/USBOE
c t
I/O CT 10 mA X X Port B1 USB Output Enable

u
od
13 PB0 I/O CT 10 mA X X Port B0

Pr
Timer Output
14 PA7/OCMP2/IT4 I/O CT X X X Port A7
Compare 2

15
e t e
PA5/ICAP2/IT2 I/O CT X X X Port A5
Timer Input Capture

o l 2

b s 16 PA4/ICAP1/IT1 I/O CT X X X Port A4

Timer Input Capture
1

O 17 PA3/EXTCLK I/O CT X X Port A3 Timer External Clock

18 PA2/ICCCLK I/O CT 25 mA X T Port A2 ICC Clock

19 PA1/ICCDATA I/O CT 25 mA X T Port A1 ICC Data

20 PA0/MCO I/O CT X X Port A0 Main Clock Output

21 VSSA S Analog ground

22 USBDP I/O USB bidirectional data (data +)

23 USBDM I/O USB bidirectional data (data -)

24 USBVCC O USB power supply

13/139
Register & memory map ST7260xx

4 Register & memory map

As shown in Figure 4, the MCU is capable of addressing 8 Kbytes of memories and I/O
registers.
The available memory locations consist of up to 384 bytes of RAM including 64 bytes of
register locations, and up to 8 Kbytes of user program memory in which the upper 32 bytes
are reserved for interrupt vectors. The RAM space includes up to 128 bytes for the stack
from 0100h to 017Fh.
The highest address bytes contain the user reset and interrupt vectors.
Note: Important: memory locations noted “Reserved” must never be accessed. Accessing a
s )
t(
reserved area can have unpredictable effects on the device.

Figure 4. Memory map

u c
o d
0000h
HW registers
r
0040h

P Short addressing
(See Table 5)
t e 00FFh
RAM (192 bytes)

le
003Fh
0040h 0100h

so
Stack
RAM (128 Bytes)

Ob
(384 Bytes) 017Fh
0180h
01BFh

)-
01C0h 16-bit addressing
RAM
Reserved

t ( s 01BFh
7FFFh
8000h
u c
d
Program memory
o
P
FFDFh r (4 / 8 KBytes)

e te
FFE0h
Interrupt & reset vectors
(See Table 4) E000h

o l FFFFh
F000h
8 KBytes

bs
4 KBytes
FFDFh

14/139
ST7260xx Register & memory map

Table 4. Interrupt vector map

Exit from Halt
Vector address Description Masked by Remarks
mode

FFE0h-FFEDh Reserved area

FFEEh-FFEFh USB interrupt vector I- bit Internal interrupt No
FFF0h-FFF1h SCI interrupt vector I- bit Internal interrupt No
FFF2h-FFF3h Reserved area
FFF4h-FFF5h TIMER interrupt vector I- bit Internal interrupt No
FFF6h-FFF7h IT1 to IT8 interrupt vector I- bit External interrupt Yes
FFF8h-FFF9h USB end suspend mode interrupt vector I- bit External interrupts Yes
FFFAh-FFFBh Flash start programming interrupt vector I- bit Internal interrupt Yes

s )
t(
FFFCh-FFFDh TRAP (software) interrupt vector None CPU interrupt No

c
FFFEh-FFFFh RESET vector None Yes

Table 5. Hardware register memory map

d u
r oReset
Address Block Register label Register name

e P status
Remarks

0000h
0001h
Port A
PADR
PADDR
Port A Data Register

le
Port A Data Direction Register
t 00h
00h
R/W
R/W
0002h PBDR
s o
Port B Data Register 00h R/W
0003h
Port B
PBDDR
b
Port B Data Direction Register

O
00h R/W
0004h
0005h
Port C
PCDR
PCDDR
) - Port C Data Register
Port C Data Direction Register
1111 x000b
1111 x000b
R/W
R/W
0006h
t ( s
to
0007h
u c Reserved (2 bytes)

0008h ITC
o d
ITIFRE Interrupt Register 00h R/W
0009h
P
MISC r MISCR Miscellaneous Register 00h R/W
000Ah

e t e
to

o
000Bh l Reserved (2 bytes)

Obs 000Ch
000Dh to
WDG WDGCR Watchdog Control Register

Reserved (4 bytes)
7Fh R/W

0010h

15/139
 Register & memory map ST7260xx

Table 5. Hardware register memory map (continued)

Reset
Address Block Register label Register name Remarks
status

0011h TCR2 Timer Control Register 2 00h R/W

0012h TCR1 Timer Control Register 1 00h R/W
0013h TCSR Timer Control/Status Register 00h R/W
0014h TIC1HR Timer Input Capture High Register 1 xxh Read only
0015h TIC1LR Timer Input Capture Low Register 1 xxh Read only
0016h TOC1HR Timer Output Compare High Register 1 80h R/W
0017h TOC1LR Timer Output Compare Low Register 1 00h R/W
0018h
0019h
TIM TCHR
TCLR
Timer Counter High Register
Timer Counter Low Register
FFh
FCh )
Read only

s
R/W
001Ah TACHR Timer Alternate Counter High Register FFh
c t(
Read only
001Bh
001Ch
TACLR
TIC2HR
Timer Alternate Counter Low Register
Timer Input Capture High Register 2
FCh
xxh
d u R/W
Read only
001Dh TIC2LR Timer Input Capture Low Register 2
r o
xxh Read only
001Eh
001Fh
TOC2HR
TOC2LR
Timer Output Compare High Register 2

e
Timer Output Compare Low Register 2 P 80h
00h
R/W
R/W
0020h SCISR
le
SCI Status Register t C0h Read only
0021h SCIDR
o
SCI Data Register
s
xxh R/W
0022h
0023h
SCI SCIBRR
SCICR1
O b
SCI Baud Rate Register
SCI Control Register 1
00h
x000 0000b
R/W
R/W
0024h SCICR2

) -SCI Control Register 2 00h R/W

0025h
0026h
USBPIDR
USBDMAR
t ( s USB PID Register
USB DMA address Register
x0h
xxh
Read only
R/W
0027h USBIDR
u c USB Interrupt/DMA Register x0h R/W
0028h
0029h
o d
USBISTR
USBIMR
USB Interrupt Status Register
USB Interrupt Mask Register
00h
00h
R/W
R/W
002Ah
002Bh USBP r USBCTLR
USBDADDR
USB Control Register
USB Device Address Register
06h
00h
R/W
R/W
002Ch
e te USBEP0RA USB Endpoint 0 Register A 0000 xxxxb R/W
002Dh
o l USBEP0RB USB Endpoint 0 Register B 80h R/W

b s
002Eh
002Fh
USBEP1RA
USBEP1RB
USB Endpoint 1 Register A
USB Endpoint 1 Register B
0000 xxxxb
0000 xxxxb
R/W
R/W

O 0030h
0031h
USBEP2RA
USBEP2RB
USB Endpoint 2 Register A
USB Endpoint 2 Register B
0000 xxxxb
0000 xxxxb
R/W
R/W
0032h
Reserved (5 Bytes)
0036h
0037h Flash FCSR Flash Control /Status Register 00h R/W
0038h
to Reserved (8 bytes)
003Fh

16/139
 ST7260xx Flash program memory

5 Flash program memory

5.1 Introduction
The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individual sectors and programmed on a byte-by-
byte basis using an external VPP supply.
The HDFlash devices can be programmed and erased off-board (plugged in a programming
tool) or on-board using ICP (in-circuit programming) or IAP (in-application programming).
The array matrix organization allows each sector to be erased and reprogrammed without
affecting other sectors.
s )
c t(
5.2 Main features
d u
● 3 Flash programming modes:
r o
–
P
Insertion in a programming tool. In this mode, all sectors including option bytes
e
–
can be programmed or erased.

le t
ICP (in-circuit programming). In this mode, all sectors including option bytes can

o
be programmed or erased without removing the device from the application board.
s
–
b
IAP (in-application programming). In this mode, all sectors, except Sector 0, can

O
be programmed or erased without removing the device from the application board

●
) -
and while the application is running.
ICT (in-circuit testing) for downloading and executing user application test patterns in
RAM
t ( s
● Readout protection
u c
●
d
Register Access Security System (RASS) to prevent accidental programming or
erasing
o
P r
5.3
t e
Structure
e
s ol The Flash memory is organized in sectors and can be used for both code and data storage.

O b Depending on the overall Flash memory size in the microcontroller device, there are up to
three user sectors (seeTable 6). Each of these sectors can be erased independently to avoid
unnecessary erasing of the whole Flash memory when only a partial erasing is required.
The first two sectors have a fixed size of 4 Kbytes (see Figure 5). They are mapped in the
upper part of the ST7 addressing space so the reset and interrupt vectors are located in
Sector 0 (F000h-FFFFh).

Table 6. Sectors available in Flash devices

Flash size (bytes) Available sectors

4K Sector 0
8K Sectors 0, 1
>8K Sectors 0, 1, 2

17/139
 Flash program memory ST7260xx

5.3.1 Readout protection

Readout protection, when selected, provides a protection against program memory content
extraction and against write access to Flash memory. Even if no protection can be
considered as totally unbreakable, the feature provides a very high level of protection for a
general purpose microcontroller.
In Flash devices, this protection is removed by reprogramming the option. In this case, the
entire program memory is first automatically erased.
Readout protection is enabled and removed through the FMP_R bit in the option byte.

Figure 5. Memory map and sector address

s )
t(
8K 16K 32K Flash

c
memory size
7FFFh

d u
o
Sector 2

r
BFFFh

DFFFh
8 Kbytes
4 Kbytes
e P
24 Kbytes
Sector 1
EFFFh
FFFFh
4 Kbytes

l e t Sector 0

s o
O b
) -
( s
u ct
o d
P r
e te
o l
b s
O

18/139
 ST7260xx Flash program memory

5.4 ICC interface

ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see
Figure 6). These pins are:
– RESET: device reset
– VSS: device power supply ground
– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input/output serial data pin
– ICCSEL/VPP: programming voltage
– OSC1 (or OSCIN): main clock input for external source (optional)
– VDD: application board power supply (see Figure 6, Note 3).

s )
Figure 6. Typical ICC interface
c t(
d u
Programming tool
ICC connector
r o
Optional ICC cable

e P
t
(see note 4) Application board

(See note 3)
9 7
ol 5 e3 1
ICC connector
HE10 connector type

bs
10 8 6 4 2 Application
reset source

-O
See note 2
10kΩ

Application
power supply
( s )
ct
See note 1
Application
ICCSEL/VPP

u I/O
OSC1
OSC2

ICCDATA
VSS
VDD

RESET
ICCCLK

o d ST7

P r
e t e
o l 1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is
necessary. As soon as the programming tool is plugged to the board, even if an ICC session is not in
progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by

b s the application, isolation such as a serial resistor has to be implemented in case another device forces the
signal. Refer to the Programming Tool documentation for recommended resistor values.

O 2. During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts
between the programming tool and the application reset circuit if it drives more than 5mA at high level
(PUSH-pull output or pull-up resistor <1K). A schottky diode can be used to isolate the application reset
circuit in this case. When using a classical RC network with R>1K or a reset management IC with open
drain output and pull-up resistor >1K, no additional components are needed. In all cases the user must
ensure that no external reset is generated by the application during the ICC session.
3. The use of Pin 7 of the ICC connector depends on the programming tool architecture. This pin must be
connected when using most ST programming tools (it is used to monitor the application power supply).
Please refer to the programming tool manual.
4. Pin 9 has to be connected to the OSC1 (OSCIN) pin of the ST7 when the clock is not available in the
application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-
oscillator capability need to have OSC2 grounded in this case.

19/139
Flash program memory ST7260xx

5.5 ICP (in-circuit programming)

To perform ICP the microcontroller must be switched to ICC (in-circuit communication) mode
by an external controller or programming tool.
Depending on the ICP code downloaded in RAM, Flash memory programming can be fully
customized (number of bytes to program, program locations, or selection serial
communication interface for downloading).
When using an STMicroelectronics or third-party programming tool that supports ICP and
the specific microcontroller device, the user needs only to implement the ICP hardware
interface on the application board (see Figure 6). For more details on the pin locations, refer
to the device pinout description.

s )
5.6 IAP (in-application programming)
c t(
d u
This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP
mode or by plugging the device in a programming tool).
r o
P
This mode is fully controlled by user software. This allows it to be adapted to the user

e
le t
application, (such as user-defined strategy for entering programming mode, choice of
communications protocol used to fetch the data to be stored). For example, it is possible to

s o
download code from the SCI, or USB interface and program it in the Flash. IAP mode can be
used to program any of the Flash sectors except Sector 0, which is write/erase protected to
b
allow recovery in case errors occur during the programming operation.
O
) -
5.7 Related documentation
t ( s
u c
For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming
Reference Manual and to the ST7 ICC Protocol Reference Manual.

o d
5.7.1 r
Flash control/status register (FCSR)
P
e t e
This register is reserved for use by programming tool software. It controls the Flash
programming and erasing operations.

ol
bs
FCSR Reset value:0000 0000 (00h)

O 7

0
6

0
5

0
4

0
3

0
2

0
1

0
0

R/W R/W R/W R/W R/W R/W R/W R/W

Table 7. Flash control/status register address and reset value

Address (Hex) Register label 7 6 5 4 3 2 1 0

0037h FCSR reset value 0 0 0 0 0 0 0 0

20/139
ST7260xx Central processing unit (CPU)

6 Central processing unit (CPU)

6.1 Introduction
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-
bit data manipulation.

6.2 Main features

● 63 basic instructions
● Fast 8-bit by 8-bit multiply
s )
● 17 main addressing modes
c t(
●
●
Two 8-bit index registers
16-bit stack pointer
d u
● Low power modes
r o
● Maskable hardware interrupts
e P
● Non-maskable software interrupt
le t
s o
6.3 CPU registers
O b
accessed by specific instructions.
) -
The six CPU registers shown in Figure 7 are not present in the memory mapping and are

Figure 7. CPU registers

t ( s
c
du
7 0

ro
Accumulator
Reset value = XXh

e P 7 0

let
X index register
Reset value = XXh

so
7 0

Ob
Y index register
Reset value = XXh

15 PCH 8 7 PCL 0
Program counter
Reset value = reset vector @ FFFEh-FFFFh
7 0
1 1 1 H I N Z C Condition code register
Reset value = 1 1 1 X 1 X X X

15 8 7 0
Stack pointer
Reset value = stack higher address

X = undefined value

21/139
 Central processing unit (CPU) ST7260xx

6.3.1 Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations and to manipulate data.

6.3.2 Index registers (X and Y)

In indexed addressing modes, these 8-bit registers are used to create effective addresses or
as temporary storage areas for data manipulation. (The Cross-Assembler generates a
precede instruction (PRE) to indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures (not pushed to and
popped from the stack).

s )
6.3.3 Program counter (PC)
c t(
d u
The program counter is a 16-bit register containing the address of the next instruction to be
executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is
the LSB) and PCH (Program Counter High which is the MSB).
r o
6.3.4 Condition code register (CC)
e P
le t
The 8-bit Condition Code register contains the interrupt mask and four flags representative

s o
of the result of the instruction just executed. This register can also be handled by the PUSH

instructions.
O b
and POP instructions. These bits can be individually tested and/or controlled by specific

) -
CC
7 6
t (
5 s 4 3 2
Reset value: 111x1xxx
1 0
c
du
1 1 1 H I N Z C

r o R/W R/W R/W R/W R/W

Table 8.
e P CC register description

e t
BIt Name Function

s ol Half carry

O b 4 H
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU
during an ADD or ADC instructions. It is reset by hardware during the same
instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD
arithmetic subroutines.

22/139
 ST7260xx Central processing unit (CPU)

Table 8. CC register description

BIt Name Function

Interrupt mask
This bit is set by hardware when entering in interrupt or by software to disable all
interrupts except the TRAP software interrupt. This bit is cleared by software.
0: Interrupts are enabled.
1: Interrupts are disabled.
3 I This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM
and JRNM instructions.
Note: Interrupts requested while I is set are latched and can be processed when I is
cleared. By default an interrupt routine is not interruptible because the I bit is set by

)
hardware at the start of the routine and reset by the IRET instruction at the end of the

s
t(
routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the current interrupt routine
Negative
u c
d
This bit is set and cleared by hardware. It is representative of the result sign of the last
o
2 N 0: The result of the last operation is positive or null. r
arithmetic, logical or data manipulation. It is a copy of the result 7th bit.

P
1.
t e
1: The result of the last operation is negative (that is, the most significant bit is a logic

le
This bit is accessed by the JRMI and JRPL instructions.

o
Zero (Arithmetic Management bit)

b s
This bit is set and cleared by hardware. This bit indicates that the result of the last
1 Z
- O
arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.

( s )
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
Carry/borrow
c t
u
This bit is set and cleared by hardware and software. It indicates an overflow or an
d
0 C
r o
underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.

e P 1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC

l e t instructions. It is also affected by the ‘bit test and branch’, shift and rotate instructions.

s o
O b

23/139
Central processing unit (CPU) ST7260xx

6.3.5 Stack pointer register (SP)

SP Reset value: 01 7Fh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 1 0 SP6 SP5 SP4 SP3 SP2 SP1 SP0

R/W R/W R/W R/W R/W R/W R/W

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the
stack. It is then decremented after data has been pushed onto the stack and incremented
before data is popped from the stack (see Figure 8).
Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware.
s )
Following an MCU reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer
contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.
c t(
The least significant byte of the Stack Pointer (called S) can be directly accessed by an LD
d u
instruction.
r o
Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit,
e P
and therefore lost. The stack also wraps in case of an underflow.
le t
without indicating the stack overflow. The previously stored information is then overwritten

s o
The stack is used to save the return address during a subroutine call and the CPU context

O b
during an interrupt. The user may also directly manipulate the stack by means of the PUSH
and POP instructions. In the case of an interrupt, the PCL is stored at the first location

Figure 8.
) -
pointed to by the SP. Then the other registers are stored in the next locations as shown in

●
t ( s
When an interrupt is received, the SP is decremented and the context is pushed on the

●
stack.
u c
stack.
o d
On return from interrupt, the SP is incremented and the context is popped from the

P r
A subroutine call occupies two locations and an interrupt five locations in the stack area.

e
let
Figure 8. Stack manipulation example

so
Call Interrupt Push Y Pop Y IRET RET
subroutine event or RSP

Ob
@ 0100h

SP
SP SP
Y
CC CC CC
A A A
X X X
PCH PCH PCH
SP SP
PCL PCL PCL
PCH PCH PCH PCH PCH
SP
@ 01FFh PCL PCL PCL PCL PCL

Stack Higher Address = 017Fh

Stack Lower Address = 0100h

24/139
 ST7260xx Reset and clock management

7 Reset and clock management

7.1 Reset
The Reset procedure is used to provide an orderly software start-up or to exit low power
modes.
Three reset modes are provided: a low voltage (LVD) reset, a watchdog reset and an
external reset at the RESET pin.
A reset causes the reset vector to be fetched from addresses FFFEh and FFFFh in order to
be loaded into the PC and with program execution starting from this point.

s )
t(
An internal circuitry provides a 4096 CPU clock cycle delay from the time that the oscillator
becomes active.
Caution:
u c
When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is

o d
not programmed. For this reason, it is recommended to keep the RESET pin in low state
r
until programming mode is entered, in order to avoid unwanted behavior
P
t e
7.2 Low voltage detector (LVD)
o le
● below VIT+ when VDD is rising,
b s
Low voltage reset circuitry generates a reset when VDD is:

● below VIT- when VDD is falling.

- O
( s )
During low voltage reset, the RESET pin is held low, thus permitting the MCU to reset other
devices.

c t
d u
It is recommended to make sure that the VDD supply voltage rises monotonously when the
device is exiting from Reset, to ensure the application functions properly.

r o
7.2.1
P
Watchdog reset

e
l e t
When a watchdog reset occurs, the RESET pin is pulled low permitting the MCU to reset
other devices in the same way as the low voltage reset (Figure 9).

s o
O b
7.2.2 External reset
The external reset is an active low input signal applied to the RESET pin of the MCU.
As shown in Figure 12, the RESET signal must stay low for a minimum of one and a half
CPU clock cycles.
An internal Schmitt trigger at the RESET pin is provided to improve noise immunity.

25/139
Reset and clock management ST7260xx

Figure 9. Low voltage detector functional diagram

RESET

VDD LOW VOLTAGE

DETECTOR
INTERNAL
RESET

FROM
WATCHDOG
RESET

s )
t(
Figure 10. Low voltage reset signal output

u c
VIT+
o d
VIT-

P r
VDD
t e
o le
RESET
b s
- O
Note: Hysteresis (VIT+-VIT-) = Vhys

( s )
c t
Figure 11. Temporization timing diagram after an internal reset

d u
r
VDD o VIT+

e P
l e t
o
Obs Temporization (4096 CPU clock cycles)

$FFFE
Addresses

26/139
 ST7260xx Reset and clock management

Figure 12. Reset timing diagram

tDDR

VDD

OSCIN

tOXOV

fCPU

s )
PC FFFE FFFF

c t(
RESET 4096 CPU
d u
CLOCK
r o
CYCLES
DELAY

e P
WATCHDOG RESET

le t
Note:
s o
Refer to Electrical Characteristics for values of tDDR, tOXOV, VIT+, VIT- and Vhys

O b
7.3 Clock system
) -
t ( s
7.3.1 General description
u c
d
The MCU accepts either a crystal or ceramic resonator, or an external clock signal to drive

o
P r
the internal oscillator. The internal clock (fCPU) is derived from the external oscillator
frequency (fOSC), which is divided by 3 (and by 2 or 4 for USB, depending on the external
clock used). The internal clock is further divided by 2 by setting the SMS bit in the

te
Miscellaneous Register.
e
o l Using the OSC24/12 bit in the option byte, a 12 MHz or a 24 MHz external clock can be
used to provide an internal frequency of either 2, 4 or 8 MHz while maintaining a 6 MHz for

b s the USB (refer to Figure 15).

O The internal clock signal (fCPU) is also routed to the on-chip peripherals. The CPU clock
signal consists of a square wave with a duty cycle of 50%.
The internal oscillator is designed to operate with an AT-cut parallel resonant quartz or
ceramic resonator in the frequency range specified for fosc. The circuit shown in Figure 14 is
recommended when using a crystal, and Table 9 lists the recommended capacitance. The
crystal and associated components should be mounted as close as possible to the input
pins in order to minimize output distortion and start-up stabilisation time.

27/139
 Reset and clock management ST7260xx

Table 9. Recommended values for 24 MHz crystal resonator

Symbol Values

RSMAX(1) 20 Ω 25 Ω 70 Ω
COSCIN 56pF 47pF 22pF
COSCOUT 56pF 47pF 22pF
RP 1-10 MΩ 1-10 MΩ 1-10 MΩ
1. RSMAX is the equivalent serial resistor of the crystal (see crystal specification).

7.3.2 External clock

s )
t(
An external clock may be applied to the OSCIN input with the OSCOUT pin not connected,
as shown on Figure 13. The tOXOV specifications do not apply when using an external clock
input. The equivalent specification of the external clock source should be used instead of
u c
tOXOV (see Section 16.5: Clock and timing characteristics).

o d
Figure 13. External clock source connections
P r
t e
o le
OSCIN
b s OSCOUT

-O NC

(s)
EXTERNAL

c t CLOCK

d u
Figure 14. Crystal/ceramic resonator

r o
e P
l e t OSCIN
RP
OSCOUT

s o
O b COSCIN COSCOUT

28/139
 ST7260xx Reset and clock management

Figure 15. Clock block diagram

8, 4 or 2 MHz
0 CPU and
peripherals)
%3 %2 1

SMS

1 6 MHz (USB)
%2
%2
24 or
12 MHz 0
%2
Crystal
OSC24/12

s )
c t(
d u
r o
e P
le t
s o
O b
) -
t ( s
u c
o d
P r
e t e
o l
b s
O

29/139
Interrupts ST7260xx

8 Interrupts

The ST7 core may be interrupted by one of two different methods: maskable hardware
interrupts as listed in Table 10: Interrupt mapping and a non-maskable software interrupt
(TRAP). The Interrupt processing flowchart is shown in Figure 16.
The maskable interrupts must be enabled clearing the I bit in order to be serviced. However,
disabled interrupts may be latched and processed when they are enabled (see external
interrupts subsection).
When an interrupt has to be serviced:
● Normal processing is suspended at the end of the current instruction execution.

s )
t(
● The PC, X, A and CC registers are saved onto the stack.
● The I bit of the CC register is set to prevent additional interrupts.

u c
o d
The PC is then loaded with the interrupt vector of the interrupt to service and the first
instruction of the interrupt service routine is fetched (refer to Table 10: Interrupt mapping for
vector addresses).
P r
e
The interrupt service routine should finish with the IRET instruction which causes the
t
le
contents of the saved registers to be recovered from the stack.
Note:
o
As a consequence of the IRET instruction, the I bit will be cleared and the main program will
resume.
s
Priority management
O b
) -
By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware
entering in interrupt routine.

t ( s
u c
In the case several interrupts are simultaneously pending, a hardware priority defines which
one will be serviced first (see Table 10: Interrupt mapping).

o d
Non-maskable software interrupts

P r
This interrupt is entered when the TRAP instruction is executed regardless of the state of

e t e
the I bit. It will be serviced according to the flowchart on Figure 16.

o l Interrupts and low power mode

bs
All interrupts allow the processor to leave the Wait low power mode. Only external and
specific mentioned interrupts allow the processor to leave the Halt low power mode (refer to

O the “Exit from HALT“ column in Table 10: Interrupt mapping).

External interrupts
The pins ITi/PAk and ITj/PBk (i=1,2; j= 5,6; k=4,5) can generate an interrupt when a rising
edge occurs on this pin. Conversely, the ITl/PAn and ITm/PBn pins (l=3,4; m= 7,8; n=6,7)
can generate an interrupt when a falling edge occurs on this pin.
Interrupt generation will occur if it is enabled with the ITiE bit (i=1 to 8) in the ITRFRE
register and if the I bit of the CCR is reset.

30/139
 ST7260xx Interrupts

Peripheral interrupts
Different peripheral interrupt flags in the status register are able to cause an interrupt when
they are active if both:
● The I bit of the CC register is cleared.
● The corresponding enable bit is set in the control register.
If any of these two conditions is false, the interrupt is latched and thus remains pending.
Clearing an interrupt request is done by one of the two following operations:
● Writing “0” to the corresponding bit in the status register.
● Accessing the status register while the flag is set followed by a read or write of an
associated register.

s )
t(
Note: 1 The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting to be

2
enabled) will therefore be lost if the clear sequence is executed.
All interrupts allow the processor to leave the Wait low power mode.
u c
3
o d
Exit from Halt mode may only be triggered by an External Interrupt on one of the ITi ports

P r
(PA4-PA7 and PB4-PB7), an end suspend mode Interrupt coming from USB peripheral, or a
reset.

t e
Figure 16. Interrupt processing flowchart

o le
FROM RESET

b s
O
N
BIT I SET

) - Y N
INTERRUPT

t ( s FETCH NEXT INSTRUCTION Y

u c
o d N

Pr
IRET
STACK PC, X, A, CC
Y SET I BIT
LOAD PC FROM INTERRUPT VECTOR

e t e EXECUTE INSTRUCTION

ol
RESTORE PC, X, A, CC FROM STACK

s
THIS CLEARS I BIT BY DEFAULT

O b

31/139
 Interrupts ST7260xx

Table 10. Interrupt mapping

Exit Vector
Source Register Priority
N° Description from
block label order address
Halt

RESET Reset Highest yes FFFEh-FFFFh

N/A Priority
TRAP Software Interrupt no FFFCh-FFFDh
FLASH Flash Start Programming Interrupt yes FFFAh-FFFBh
USB End Suspend Mode ISTR FFF8h-FFF9h
yes
1 ITi External Interrupts ITRFRE FFF6h-FFF7h
2 TIMER Timer Peripheral Interrupts TIMSR
)
FFF4h-FFF5h
s
3 Reserved
Lowest no
c t(
FFF2h-FFF3h
4 SCI SCI Peripheral Interrupts SCISR Priority
d u FFF0h-FFF1h
5 USB USB Peripheral Interrupts ISTR

r o FFEEh-FFEFh

8.0.1 Interrupt register (ITRFRE)

e P
le t
so
ITRFRE Reset value: 0000 0000 (00h)
7 6 5 4 3 2 1 0

IT8E IT7E IT6E

O bIT5E IT4E IT3E IT2E IT1E

R/W R/W
)
R/W - R/W R/W R/W R/W R/W

( s
ct
Table 11. ITRFRE register description

du
Bit Name Function

ro
Interrupt enable control bits
If an ITiE bit is set, the corresponding interrupt is generated when:

e P
ITiE
7:0 (i=1 to
– a rising edge occurs on the pin PA4/IT1 or PA5/IT2 or PB4/IT5 or PB5/IT6

l e t 8)
or
– a falling edge occurs on the pin PA6/IT3 or PA7/IT4 or PB6/IT7 or PB7/IT8

s o No interrupt is generated elsewhere..

O b Table 12. Interrupt register map and reset values

Address (Hex.) Register label 7 6 5 4 3 2 1 0

ITRFRE IT8E IT7E IT6E IT5E IT4E IT3E IT2E IT1E

0008h
reset value 0 0 0 0 0 0 0 0

32/139
 ST7260xx Power saving modes

9 Power saving modes

9.1 Introduction
To give a large measure of flexibility to the application in terms of power consumption, two
main power saving modes are implemented in the ST7.
After a RESET, the normal operating mode is selected by default (RUN mode). This mode
drives the device (CPU and embedded peripherals) by means of a master clock which is
based on the main oscillator frequency divided by 3 (fCPU).
From Run mode, the different power saving modes may be selected by setting the relevant

s )
register bits or by calling the specific ST7 software instruction whose action depends on the
oscillator status.

c t(
d u
9.2 Halt mode
r o
e P
The MCU consumes the least amount of power in Halt mode. The Halt mode is entered by
executing the HALT instruction. The internal oscillator is then turned off, causing all internal

le t
processing to be stopped, including the operation of the on-chip peripherals.

s o
When entering Halt mode, the I bit in the Condition Code Register is cleared. Thus, all
external interrupts (ITi or USB end suspend mode) are allowed and if an interrupt occurs,
the CPU clock becomes active.
O b
) -
The MCU can exit Halt mode on reception of either an external interrupt on ITi, an end
suspend mode interrupt coming from USB peripheral, or a reset. The oscillator is then

t ( s
turned on and a stabilization time is provided before releasing CPU operation. The

c
stabilization time is 4096 CPU clock cycles.

u
o d
After the start up delay, the CPU continues operation by servicing the interrupt which wakes
it up or by fetching the reset vector if a reset wakes it up.

P r
e t e
o l
b s
O

33/139
 Power saving modes ST7260xx

Figure 17. Halt mode flowchart

HALT INSTRUCTION

OSCILLATOR OFF
PERIPH. CLOCK OFF
CPU CLOCK OFF
I-BIT CLEARED

N
RESET
s )
N

c t(
EXTERNAL
INTERRUPT*
Y

d u
Y
r o
OSCILLATOR
PERIPH. CLOCK

e
ON
ONP
CPU CLOCK
I-BIT
le t ON
SET

s o
b 4096 CPU CLOCK

-O
CYCLES DELAY

( s )
ct
FETCH RESET VECTOR
OR SERVICE INTERRUPT

d u
Note:
r o
Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during

P
the interrupt routine and cleared when the CC register is popped.

e
9.3 l e t
Slow mode
s o
O b In Slow mode, the oscillator frequency can be divided by 2 as selected by the SMS bit in the
Miscellaneous Register. The CPU and peripherals are clocked at this lower frequency. Slow
mode is used to reduce power consumption, and enables the user to adapt the clock
frequency to the available supply voltage.

9.4 Wait mode

Wait mode places the MCU in a low power consumption mode by stopping the CPU.
This power saving mode is selected by calling the “WFI” ST7 software instruction.
All peripherals remain active. During Wait mode, the I bit of the CC register is forced to 0 to
enable all interrupts. All other registers and memory remain unchanged. The MCU remains
in Wait mode until an interrupt or Reset occurs, whereupon the Program Counter branches
to the starting address of the interrupt or Reset service routine.

34/139
 ST7260xx Power saving modes

The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake
up.
Refer to Figure 18.
Related documentation
● AN 980: ST7 keypad decoding techniques, implementing wake-up on keystroke
● AN1014: How to minimize the ST7 power consumption
● AN1605: Using an active RC to wakeup the ST7LITE0 from power saving mode

Figure 18. Wait mode flowchart

WFI INSTRUCTION

s )
c t(
OSCILLATOR
PERIPH. CLOCK
ON
ON
d u
CPU CLOCK OFF
r o
I-BIT

e
CLEARED

P
le t
N

s o RESET

N
b
) -O
INTERRUPT
Y

( s
ct
Y OSCILLATOR ON

d u PERIPH. CLOCK
CPU CLOCK
ON
ON

r o I-BIT SET

e P IF RESET

l e t 4096 CPU CLOCK

CYCLES DELAY

s o
O b FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during
the interrupt routine and cleared when the CC register is popped.

35/139
 I/O ports ST7260xx

10 I/O ports

10.1 Introduction
The I/O ports offer different functional modes:
● Transfer of data through digital inputs and outputs and for specific pins
● Alternate signal input/output for the on-chip peripherals
● External interrupt generation
An I/O port consists of up to 8 pins. Each pin can be programmed independently as a digital
input (with or without interrupt generation) or a digital output.

s )
10.2 Functional description c t(
d u
Each port is associated to 2 main registers:
● r o
●
Data register (DR)
Data direction register (DDR)
e P
le t
Each I/O pin may be programmed using the corresponding register bits in DDR register: bit

o
X corresponding to pin X of the port. The same correspondence is used for the DR register.

s
Table 13. I/O pin functions
O b
DDR

) - Mode

t(s
0 Input

uc
1 Output

Input modes

o d
P r
The input configuration is selected by clearing the corresponding DDR register bit.
In this case, reading the DR register returns the digital value applied to the external I/O pin.
Note: 1
e t e
All the inputs are triggered by a Schmitt trigger.

o
2 l When switching from input mode to output mode, the DR register should be written first to

b s output the correct value as soon as the port is configured as an output.

O Interrupt function
When an I/O is configured as an Input with Interrupt, an event on this I/O can generate an
external Interrupt request to the CPU. The interrupt sensitivity is given independently
according to the description mentioned in the ITRFRE interrupt register.
Each pin can independently generate an Interrupt request.
Each external interrupt vector is linked to a dedicated group of I/O port pins (see Interrupts
section). If more than one input pin is selected simultaneously as an interrupt source, this is
logically ORed. For this reason if one of the interrupt pins is tied low, the other ones are
masked.
Output mode
The pin is configured in output mode by setting the corresponding DDR register bit (see
Table 13).

36/139
 ST7260xx I/O ports

In this mode, writing “0” or “1” to the DR register applies this digital value to the I/O pin
through the latch. Therefore, the previously saved value is restored when the DR register is
read.
Note: The interrupt function is disabled in this mode.
Alternate function
When an on-chip peripheral is configured to use a pin, the alternate function is automatically
selected. This alternate function takes priority over standard I/O programming. When the
signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output
mode (push-pull or open drain according to the peripheral).
When the signal is going to an on-chip peripheral, the I/O pin has to be configured in input
mode. In this case, the pin’s state is also digitally readable by addressing the DR register.
s )
Note: 1 Input pull-up configuration can cause an unexpected value at the input of the alternate
peripheral input.
c t(
2
d u
When the on-chip peripheral uses a pin as input and output, this pin must be configured as
an input (DDR = 0).
r o
Caution:
P
The alternate function must not be activated as long as the pin is configured as an input with

e
interrupt in order to avoid generating spurious interrupts.

le t
10.2.1 Port A
s o
Table 14. b
Port A0, A3, A4, A5, A6, A7 description
O
Port A
I/O

) - Alternate function

Input(1)
t ( s Output Signal Condition

c MCO (Main Clock

du
PA0 with pull-up push-pull MCO = 1 (MISCR)
Output)

PA3
r o with pull-up push-pull Timer EXTCLK
CC1 =1

P CC0 = 1 (Timer CR2)

ete
Timer ICAP1

ol
PA4 with pull-up IT1 Schmitt triggered
push-pull IT1E = 1 (ITIFRE)
input

b s Timer ICAP2

O PA5 with pull-up

push-pull IT2 Schmitt triggered
input
IT2E = 1 (ITIFRE)

Timer OCMP1 OC1E = 1

PA6(2) with pull-up IT3 Schmitt triggered
push-pull IT3E = 1 (ITIFRE)
input
Timer OCMP2 OC2E = 1
PA7 with pull-up IT4 Schmitt triggered
push-pull IT4E = 1 (ITIFRE)
input
1. Reset state
2. Not available on SO24

37/139
 I/O ports ST7260xx

Figure 19. PA0, PA3, PA4, PA5, PA6, PA7 configuration

ALTERNATE ENABLE
ALTERNATE 1 VDD
OUTPUT

0 P-BUFFER

DR VDD
PULL-UP
LATCH
DATA BUS

ALTERNATE ENABLE
DDR
LATCH PAD

DDR SEL

s )
t(
N-BUFFER

DR SEL 1
ALTERNATE ENABLE
VSS
u cDIODES

ALTERNATE INPUT 0

o d
r
CMOS SCHMITT TRIGGER

e P
Table 15. PA1, PA2 description
le t
I/O
s o Alternate function
Port A
Input(1) b
-O
Output Signal Condition

Very High Current

PA1 without pull-up

( s ) open drain

ct
Very High Current
PA2 without pull-up

1. Reset state
d u open drain

r o
e P
l e t
s o
O b

38/139
ST7260xx I/O ports

Figure 20. PA1, PA2 configuration

ALTERNATE ENABLE
ALTERNATE 1
OUTPUT
0

DR
LATCH

DDR
LATCH
DATA BUS

PAD

DDR SEL
s )
N-BUFFER
c t(
d u
DR SEL 1
ALTERNATE ENABLE

r o
0
CMOS SCHMITT TRIGGER

e
VSS

P
le t
s o
10.2.2 Port B
O b
Table 16. Port B description
) -
t ( s I/O Alternate function
Port B
c
du
Input(1) Output Signal Condition

ro
PB0 without pull-up push-pull

e P
let
PB1 without pull-up push-pull USBOE USBOE =1
(USB output enable)(2) (MISCR)

so PB2 without pull-up push-pull

Ob
PB3 without pull-up push-pull

PB4 without pull-up push-pull IT5 Schmitt triggered

IT4E = 1 (ITIFRE)
input

PB5 without pull-up push-pull IT6 Schmitt triggered

IT5E = 1 (ITIFRE)
input

PB6 without pull-up push-pull IT7 Schmitt triggered

IT6E = 1 (ITIFRE)
input

39/139
I/O ports ST7260xx

Table 16. Port B description (continued)

I/O Alternate function
Port B
Input(1) Output Signal Condition

PB7 without pull-up push-pull IT8 Schmitt triggered

IT7E = 1 (ITIFRE)
input
1. Reset state
2. On SO24 only

Figure 21. Port B configuration

s )
t(
ALTERNATE ENABLE
ALTERNATE 1 VDD
OUTPUT
0
VDD
u c
DR
LATCH
P-BUFFER

o d
DDR
ALTERNATE ENABLE

P r PAD
LATCH

t e
le
DATA BUS

DDR SEL
s o
O b N-BUFFER
DIODES

DR SEL
1
) -
t ( s ALTERNATE ENABLE

DIGITAL ENABLE

u c 0 VSS

ALTERNATE INPUT

o d
10.2.3 P
Port C
r
e te
o l Table 17. Port C description

bs
I/O Alternate function
Port C
Input(1)
O PC0 with pull-up
Output

push-pull
Signal

RDI (SCI input)

Condition

PC1 with pull-up push-pull TDO (SCI output) SCI enable

USBOE USBOE =1
PC2(2) with pull-up push-pull
(USB output enable) (MISCR)
1. Reset state
2. Not available on SO24

40/139
 ST7260xx I/O ports

Figure 22. Port C configuration

ALTERNATE ENABLE
ALTERNATE 1 VDD
OUTPUT

0
P-BUFFER

DR VDD
PULL-UP
LATCH
ALTERNATE ENABLE
DATA BUS

DDR
LATCH PAD

DDR SEL

s )
t(
N-BUFFER

DR SEL 1
ALTERNATE ENABLE
u cDIODES

VSS
o d
r
0
ALTERNATE INPUT

CMOS SCHMITT TRIGGER

e P
10.2.4 Register description le t
s o
10.2.5 Data register (PxDR)
O b
PADR
) - Reset value: 0000 0000 (00h)
PBDR
PCDR
t ( s Reset value: 0000 0000 (00h)
Reset value: 1111 x000 (Fxh)
c
du
7 6 5 4 3 2 1 0

P
R/W
D7
roD6

R/W
D5

R/W
D4

R/W R/W
D3 D2

R/W R/W
D1 D0

R/W

e t e
Table 18. PxDR register description

o l Bit Name Function

b s Data bits

O The DR register has a specific behavior according to the selected input/output

configuration. Writing the DR register is always taken into account even if the pin is
configured as an input. Reading the DR register returns either the DR register latch
7:0 D[7:0] content (pin configured as output) or the digital value applied to the I/O pin (pin
configured as input).
– When using open-drain I/Os in output configuration, the value read in DR is the
digital value applied to the I/O pin.
– For Port C, unused bits (7-3) are not accessible

41/139
 I/O ports ST7260xx

10.2.6 Data direction register (PxDDR)

PADDR Reset value: 0000 0000 (00h)

PBDDR Reset value: 0000 0000 (00h)
PCDDR Reset value: 1111 x000 (Fxh)
7 6 5 4 3 2 1 0

DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0

R/W R/W R/W R/W R/W R/W R/W R/W

Table 19. PxDDR register description

Bit Name Function
s )
Data Direction bits
c t(
DD set and cleared by software.
d u
The DDR register gives the input/output direction configuration of the pins. Each bit is
7:0
[7:0] 0: Input mode
r o
1: Output mode
For Port C, unused bits (7-3) are not accessible
e P
Table 20. I/O port register map and reset values
le t
Address (Hex.) Register label 7 6
s o 5 4 3 2 1 0

b
-O
PADR D7 D6 D5 D4 D3 D2 D1 D0
0000h
reset value 0 0 0 0 0 0 0 0

(s)
PADDR DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0
0001h
reset value 0 0 0 0 0 0 0 0
PBDR
c t D7 D6 D5 D4 D3 D2 D1 D0
0002h

d u
reset value 0 0 0 0 0 0 0 0

0003h
r o PBDDR DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0

e P reset value
PCDR
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0

l e t 0004h
reset value 0 0 0 0 0 0 0 0

s o 0005h
PCDDR
reset value
DD7
0
DD6
0
DD5
0
DD4
0
DD3
0
DD2
0
DD1
0
DD0
0

O b 0006h Reserved
0007h Reserved

10.2.7 Related documentation

● AN 970: SPI Communication between ST7 and EEPROM
● AN1048: Software LCD driver

42/139
ST7260xx Miscellaneous register

11 Miscellaneous register

MISCR Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1 0

- - - - - SMS USBOE MCO

R/W R/W R/W

Table 21. MISCR register description

Bit Name Function

s )
7:3 Reserved

c t(
Slow mode select

d u
This bit is set by software and only cleared by hardware after a reset. If this bit is set, it
2 SMS
r o
enables the use of an internal divide-by-2 clock divider (refer to Figure 15 on page 29).
The SMS bit has no effect on the USB frequency.
0: Divide-by-2 disabled and CPU clock frequency is standard
e P
t
1: Divide-by-2 enabled and CPU clock frequency is halved

le
1
USB
USB enable

s o
If this bit is set, the port PC2 (PB1 on SO24) outputs the USB output enable signal (at
OE
b
“1” when the ST7 USB is transmitting data). Unused bits 7-4 are set.
Main clock out selection
O
) -
This bit enables the MCO alternate function on the PA0 I/O port. It is set and cleared
0 MCO by software.

t ( s
0: MCO alternate function disabled (I/O pin free for general-purpose I/O)

u c
1: MCO alternate function enabled (fCPU on I/O port)

Table 22.
o d
Miscellaneous register map and reset values

P r
Address (Hex.) Register label 7 6 5 4 3 2 1 0

e
let
USB
0009h MISCR SMS OE MCO

s o reset value 0 0 0

Ob

43/139
Watchdog timer (WDG) ST7260xx

12 Watchdog timer (WDG)

12.1 Introduction
The Watchdog timer is used to detect the occurrence of a software fault, usually generated
by external interference or by unforeseen logical conditions, which causes the application
program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on
expiry of a programmed time period, unless the program refreshes the counter’s contents
before the T6 bit becomes cleared.

12.2 Main features

s )
● Programmable free-running counter (64 increments of 49,152 CPU cycles)
c t(
● Programmable reset
d u
● Reset (if watchdog activated) when the T6 bit reaches zero
r o
●
● Hardware Watchdog selectable by option byte.
e P
Optional reset on HALT instruction (configurable by option byte)

le t
12.3 Functional description
s o
O b
The counter value stored in the CR register (bits T6:T0), is decremented every 49,152

increments.
) -
machine cycles, and the length of the timeout period can be programmed by the user in 64

t ( s
If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T6:T0) rolls
c
over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin
u
d
for a period of tDOG (see Table 62: Control timings on page 114).

o
P r
The application program must write in the CR register at regular intervals during normal
operation to prevent an MCU reset. This downcounter is free-running: it counts down even if

e t e
the watchdog is disabled. The value to be stored in the CR register must be between FFh
and C0h (see Table 23: Watchdog timing (fCPU = 8 MHz) on page 45):

o l ● The WDGA bit is set (watchdog enabled)

bs
● The T6 bit is set to prevent generating an immediate reset
●
O The T5:T0 bits contain the number of increments which represents the time delay
before the watchdog produces a reset.

44/139
ST7260xx Watchdog timer (WDG)

Figure 23. Watchdog block diagram

RESET

WATCHDOG CONTROL REGISTER (CR)

WDGA T6 T5 T4 T3 T2 T1 T0

7-BIT DOWNCOUNTER

s )
c t(
fCPU CLOCK DIVIDER
d u
÷49152
r o
e P
Table 23. Watchdog timing (fCPU = 8 MHz)
le t
so
CR register initial value WDG timeout period (ms)

Ob
Max FFh 393.216

)-
Min C0h 6.144

Note: 1
s
Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by
a reset.
t (
2
u c
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
o d
12.3.1
P r
Software watchdog option

e t e
If Software Watchdog is selected by option byte, the watchdog is disabled following a reset.

o l Once activated it cannot be disabled, except by a reset.

bs
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
O
12.3.2 Hardware watchdog option
If Hardware Watchdog is selected by option byte, the watchdog is always active and the
WDGA bit in the CR is not used.

45/139
 Watchdog timer (WDG) ST7260xx

12.3.3 Low power modes

WAIT Instruction
No effect on Watchdog.
HALT Instruction
If the Watchdog reset on HALT option is selected by option byte, a HALT instruction causes
an immediate reset generation if the Watchdog is activated (WDGA bit is set).

12.3.4 Using Halt mode with the WDG (option)

If the Watchdog reset on HALT option is not selected by option byte, the Halt mode can be
used when the watchdog is enabled.
s )
t(
In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the
c
receives an external interrupt or a reset.
d u
WDG stops counting and is no longer able to generate a reset until the microcontroller

r o
If an external interrupt is received, the WDG restarts counting after 4096 CPU clocks. If a
reset is generated, the WDG is disabled (reset state).

e P
Recommendations
●
le t
Make sure that an external event is available to wake up the microcontroller from Halt
mode.
s o
●
b
Before executing the HALT instruction, refresh the WDG counter, to avoid an

O
unexpected WDG reset immediately after waking up the microcontroller.
●
-
When using an external interrupt to wake up the microcontroller, reinitialize the
)
t ( s
corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT
instruction. The main reason for this is that the I/O may be wrongly configured due to
c
external interference or by an unforeseen logical condition.
u
●
d
For the same reason, reinitialize the level sensitiveness of each external interrupt as a

o
precautionary measure.
●
P r
The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction

e t e due to a program counter failure, it is advised to clear all occurrences of the data value
0x8E from memory. For example, avoid defining a constant with the value 0x8E.

o l ● As the HALT instruction clears the I bit in the CC register to allow interrupts, the user

b s may choose to clear all pending interrupt bits before executing the HALT instruction.
This avoids entering other peripheral interrupt routines after executing the external

O interrupt routine corresponding to the wake-up event (reset or external interrupt).

12.3.5 Interrupts
None.

46/139
 ST7260xx Watchdog timer (WDG)

12.3.6 Control register (WDGCR)

WDGCR Reset value: 0111 1111 (7Fh)

7 6 5 4 3 2 1 0

WDGA T[6:0]

R/W R/W

Table 24. WDGCR register description

Bit Name Function

Activation bit
s )
7 WDGA
This bit is set by software and only cleared by hardware after a reset. When
WDGA = 1, the watchdog can generate a reset.
c t(
0: Watchdog disabled
1: Watchdog enabled
d u
r o
Note: This bit is not used if the hardware watchdog option is enabled by option byte.
7-bit counter (MSB to LSB)

e P
6:0 T[6:0]
t
These bits contain the value of the Watchdog counter. A reset is produced when it

le
rolls over from 40h to 3Fh (T6 is cleared).

Table 25.
s o
Watchdog timer register map and reset values
Address (Hex.) Register label 7
O
6b 5 4 3 2 1 0

000Ch
WDGCR
reset value
)0-
WDGA T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1

t ( s
u c
o d
P r
e t e
o l
b s
O

47/139
Watchdog timer (WDG) ST7260xx

12.4 16-bit timer

12.4.1 Introduction
The timer consists of a 16-bit free-running counter driven by a programmable prescaler.
It may be used for a variety of purposes, including pulse length measurement of up to two
input signals (input capture) or generation of up to two output waveforms (output compare
and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the CPU clock prescaler.
Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and

s )
t(
do not share any resources. They are synchronized after a MCU reset as long as the timer
clock frequencies are not modified.

u
This description covers one or two 16-bit timers. In ST7 devices with two timers, registerc
names are prefixed with TA (Timer A) or TB (Timer B).
o d
12.4.2 Main features P r
t e
le
● Programmable prescaler: fCPU divided by 2, 4 or 8
●
●
Overflow status flag and maskable interrupt

s o
External clock input (must be at least four times slower than the CPU clock speed) with
the choice of active edge
O b
●
–
)
2 dedicated 16-bit registers -
1 or 2 output compare functions each with:

–
t ( s
2 dedicated programmable signals
–
u c
2 dedicated status flags
–
d
1 dedicated maskable interrupt
o
●
–
P r
1 or 2 input capture functions each with:
2 dedicated 16-bit registers
e
let
– 2 dedicated active edge selection signals
– 2 dedicated status flags

s o – 1 dedicated maskable interrupt

Ob ●
●
Pulse width modulation mode (PWM)
One pulse mode
● Reduced power mode
● 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)(a)
The timer block diagram is shown in Figure 24.

a. Some timer pins may not be available (not bonded) in some ST7 devices. Refer to Section 3: Pin description.
When reading an input signal on a non-bonded pin, the value will always be ‘1’.

48/139
 ST7260xx Watchdog timer (WDG)

12.4.3 Functional description

Counter
The main block of the programmable timer is a 16-bit free running upcounter and its
associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called
high and low.
● Counter Register (CR)
– Counter High Register (CHR) is the most significant byte (MSB)
– Counter Low Register (CLR) is the least significant byte (LSB)
● Alternate Counter Register (ACR)
– Alternate Counter High Register (ACHR) is the most significant byte (MSB)
s )
–
t(
Alternate Counter Low Register (ACLR) is the least significant byte (LSB)

c
d u
These two read-only 16-bit registers contain the same value but with the difference that
reading the ACLR register does not clear the TOF bit (timer overflow flag), located in the

o
Status register (SR) (see note at the end of paragraph entitled 16-bit read sequence).
r
e P
Writing in the CLR register or ACLR register resets the free running counter to the FFFCh
value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in

le t
the 16-bit timer). The reset value of both counters is also FFFCh in one pulse mode and
PWM mode.

s o
The timer clock depends on the clock control bits of the CR2 register, as illustrated in

O b
Table 32. The value in the counter register repeats every 131072, 262144 or 524288 CPU
clock cycles depending on the CC[1:0] bits. The timer frequency can be fCPU/2, fCPU/4,
fCPU/8 or an external frequency.
) -
t ( s
u c
o d
P r
e t e
o l
b s
O

49/139
 Watchdog timer (WDG) ST7260xx

Figure 24. Timer block diagram

ST7 internal bus

fCPU
MCU-peripheral interface

8 high 8 low

8-bit 8 8 8 8 8 8 8 8
buffer

high

high

high

high
low

low

low

low
EXEDG

16

1/2 Output Output Input Input

s )
t(
Counter Capture Capture
1/4 register Compare Compare
register register

uc
1/8 register register
1 2 1 2
EXTCLK

d
Alternate
pin Counter
register

r o 16 16

CC[1:0]
16

e P
et
Timer internal bus
16

o l 16

Overflow
s
Ob
Output Compare Edge Detect
Detect ICAP1
circuit circuit 1
circuit pin

( s )- 6 Edge Detect
circuit 2 ICAP2

t
pin

c
du
Latch 1 OCMP1
pin

P ro
ICF1 OCF1 TOF ICF2 OCF2 TIMD 0
(Control/Status register) CSR
0
Latch 2 OCMP2
pin

e t e
o l ICIE OCIE TOIE FOLV2FOLV1OLVL2 IEDG1OLVL1 OC1E OC2E OPM PWM CC1 CC0 IEDG2EXEDG

s
(Control register 1) CR1 (Control register 2) CR2

O b
(See note 1)

Timer interrupt

1. If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (see Table 10:
Interrupt mapping on page 32).

50/139
ST7260xx Watchdog timer (WDG)

16-bit read sequence

The 16-bit read sequence (from either the Counter register or the Alternate Counter
register) is illustrated in the following Figure 25.

Figure 25. 16-bit read sequence

Beginning of the sequence

At t0 Read MSB LSB is buffered

Other
instructions

At t0 +Δt Read LSB

Returns the buffered

s )
t(
LSB value at t0

Sequence completed

u c
d
The user must first read the MSB, afterwhich the LSB value is automatically buffered.
o
the user reads the MSB several times. P r
This buffered value remains unchanged until the 16-bit read sequence is completed, even if

t e
le
After a complete reading sequence, if only the CLR register or ACLR register are read, they
return the LSB of the count value at the time of the read.

s o
Whatever the timer mode used (input capture, output compare, one pulse mode or PWM
b
mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then:
O
●
●
) -
The TOF bit of the SR register is set.
A timer interrupt is generated if:
–
t ( s
TOIE bit of the CR1 register is set and
–
c
I bit of the CC register is cleared.
u
d
If one of these conditions is false, the interrupt remains pending to be issued as soon as
o
P r
they are both true.
Clearing the overflow interrupt request is done in two steps:
e
let
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.

so
Note: The TOF bit is not cleared by access to the ACLR register. The advantage of accessing the

Ob
ACLR register rather than the CLR register is that it allows simultaneous use of the overflow
function and reading the free running counter at random times (for example, to measure
elapsed time) without the risk of clearing the TOF bit erroneously.
The timer is not affected by Wait mode.
In Halt mode, the counter stops counting until the mode is exited. Counting then resumes
from the previous count (MCU awakened by an interrupt) or from the reset count (MCU
awakened by a reset).

51/139
Watchdog timer (WDG) ST7260xx

External clock
The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register.
The status of the EXEDG bit in the CR2 register determines the type of level transition on
the external clock pin EXTCLK that will trigger the free running counter.
The counter is synchronized with the falling edge of the internal CPU clock.
A minimum of four falling edges of the CPU clock must occur between two consecutive
active edges of the external clock; thus the external clock frequency must be less than a
quarter of the CPU clock frequency.

Figure 26. Counter timing diagram, internal clock divided by 2

s )
CPU clock

c t(
Internal reset

d u
Timer clock
r o
Counter register
FFFD FFFE FFFF 0000

e P
0001 0002 0003

Timer Overflow Flag (TOF)

le t
s o
b
Figure 27. Counter timing diagram, internal clock divided by 4
O
CPU clock
) -
t ( s
c
Internal reset

du
Timer clock

r o Counter register FFFC FFFD 0000 0001

P
ete
Timer Overflow Flag (TOF)

o l
s Figure 28. Counter timing diagram, internal clock divided by 8

Ob CPU clock

Internal reset

Timer clock

Counter register FFFC FFFD 0000

Timer Overflow Flag (TOF)

Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is
running.

52/139
ST7260xx Watchdog timer (WDG)

Input capture
In this section, the index, i, may be 1 or 2 because there are two input capture functions in
the 16-bit timer.
The two 16-bit input capture registers (IC1R/IC2R) are used to latch the value of the free
running counter after a transition is detected on the ICAPi pin (see Figure 30).

Table 26. Input capture byte distribution

Register MS byte LS byte

ICiR ICiHR ICiLR

The ICiR registers are read-only registers.

s )
(CRi).
c t(
The active transition is software programmable through the IEDGi bit of Control Registers

d
Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). u
Procedure
r o
e P
To use the input capture function select the following in the CR2 register:
● Select the timer clock (CC[1:0]) (see Table 32).
le t
●
o
Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2

s
pin must be configured as floating input or input with pull-up without interrupt if this
configuration is available).
O b
●
) -
Select the following in the CR1 register:
Set the ICIE bit to generate an interrupt after an input capture coming from either the

t ( s
ICAP1 pin or the ICAP2 pin
●
c
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
u
ICAP1pin must be configured as floating input or input with pull-up without interrupt if

o d
this configuration is available).

P r
When an input capture occurs:

e
●
t
●
e
ICFi bit is set.

o l The ICiR register contains the value of the free running counter on the active transition
on the ICAPi pin (see Figure 30).

Obs ● A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC
register. Otherwise, the interrupt remains pending until both conditions become true.
Clearing the Input Capture interrupt request (that is, clearing the ICFi bit) is done in two
steps:
1. Reading the SR register while the ICFi bit is set
2. An access (read or write) to the ICiLR register

53/139
 Watchdog timer (WDG) ST7260xx

Note: 1 After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never
be set until the ICiLR register is also read.
2 The ICiR register contains the free running counter value which corresponds to the most
recent input capture.
3 The two input capture functions can be used together even if the timer also uses the two
output compare functions.
4 In One pulse mode and PWM mode only Input Capture 2 can be used.
5 The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any
transitions on these pins activates the input capture function.
Moreover if one of the ICAPi pins is configured as an input and the second one as an output,
an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set.
This can be avoided if the input capture function i is disabled by reading the ICiHR (see
s )
note 1).

c t(
6 The TOF bit can be used with interrupt generation in order to measure events that go
beyond the timer range (FFFFh).
d u
r o
Figure 29. Input capture block diagram

e P
ICAP1

le t (Control register 1) CR1

so
pin
Edge Detect Edge Detect ICIE IEDG1

b
circuit 2 circuit 1
ICAP2

O
pin (Status register) SR

IC2R register

) -
IC1R register ICF1 ICF2 0 0 0

( s
16-bit

u ct (Control register 2) CR2

o d
16-bit free running counter
CC1 CC0 IEDG2

P r
e te
o l Figure 30. Input capture timing diagram

b s
O Timer clock

Counter register FF01 FF02 FF03

ICAPi pin

ICAPi flag

ICAPi register FF03

Note: The rising edge is the active edge.

54/139
ST7260xx Watchdog timer (WDG)

Output compare
In this section, the index, i, may be 1 or 2 because there are two output compare functions in
the 16-bit timer.
This function can be used to control an output waveform or indicate when a period of time
has elapsed.
When a match is found between the Output Compare register and the free running counter,
the output compare function:
– Assigns pins with a programmable value if the OCiE bit is set
– Sets a flag in the status register
– Generates an interrupt if enabled

s )
t(
Two 16-bit registers Output Compare register 1 (OC1R) and Output Compare register 2

c
(OC2R) contain the value to be compared to the counter register each timer clock cycle.

u
Table 27. Output compare byte distribution
o d
Register MS byte
P r LS byte

OCiR OCiHR

e t e OCiLR

reset event changes the OCiR value to 8000h.

o l
These registers are readable and witable and are not affected by the timer hardware. A

b s
Timing resolution is one count of the free running counter: (fCPU/CC[1:0]).
Procedure
- O
( s )
To use the Output Compare function, select the following in the CR2 register:

ct
● Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output
compare i signal.
●
d u
Select the timer clock (CC[1:0]) (see Table 32).

r o
And select the following in the CR1 register:
●
P
Select the OLVLi bit to applied to the OCMPi pins after the match occurs.
e
let
● Set the OCIE bit to generate an interrupt if it is needed.
When a match is found between OCRi register and CR register:

so ● OCFi bit is set

Ob
● The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset)
● A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is
cleared in the CC register (CC).
The OCiR register value required for a specific timing application can be calculated using
the following formula:
Δt * fCPU
Δ OCiR =
PRESC

Where:
Δt = Output compare period (in seconds)
fCPU = CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits; see Table 32)

55/139
 Watchdog timer (WDG) ST7260xx

If the timer clock is an external clock, the formula is:

Δ OCiR = Δt * fEXT

Where:
Δt = Output compare period (in seconds)
fEXT = External timer clock frequency (in hertz)

Clearing the output compare interrupt request (that is, clearing the OCFi bit) is done by:
1. Reading the SR register while the OCFi bit is set.
2. An access (read or write) to the OCiLR register.

s )
t(
The following procedure is recommended to prevent the OCFi bit from being set between
the time it is read and the write to the OCiR register:
● Write to the OCiHR register (further compares are inhibited).
u c
●
od
Read the SR register (first step of the clearance of the OCFi bit, which may be already

●
set).
P r
Write to the OCiLR register (enables the output compare function and clears the OCFi
bit).
t e
Note: 1
le
After a processor write cycle to the OCiHR register, the output compare function is inhibited
o
2
until the OCiLR register is also written.

b s
If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not
O
appear when a match is found but an interrupt could be generated if the OCIE bit is set.
-
3

( s )
In both internal and external clock modes, OCFi and OCMPi are set while the counter value
equals the OCiR register value (see Figure 32 on page 57 for an example with fCPU/2 and
t
Figure 33 on page 57 for an example with fCPU/4). This behavior is the same in OPM or
c
4
PWM mode.

d u
The output compare functions can be used both for generating external events on the

r o
OCMPi pins even if the input capture mode is also used.
5
P
The value in the 16-bit OCiR register and the OLVi bit should be changed after each
e
l e t
successful comparison in order to control an output waveform or establish a new elapsed
timeout.

s o Forced output compare capability

O b When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit
has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit = 1). The
OCFi bit is then not set by hardware, and thus no interrupt request is generated.
The FOLVLi bits have no effect in both one pulse mode and PWM mode.

56/139
 ST7260xx Watchdog timer (WDG)

Figure 31. Output compare block diagram

16-bit free running counter OC1E OC2E CC1 CC0

(Control Register 2) CR2

16-bit

(Control Register 1) CR1

Output compare circuit OCIE FOLV2FOLV1 OLVL2 OLVL1 Latch

1 OCMP1
Pin

16-bit 16-bit
Latch
2 OCMP2

)
OC1R register Pin
OCF1 OCF2 0 0 0

t( s
c
OC2R register
(Status register) SR

d u
Figure 32. Output compare timing diagram, fTIMER = fCPU/2
r o
e P
Internal CPU clock

le t
Timer clock

s o
Counter register
b
2ECF 2ED0 2ED1 2ED2 2ED3 2ED4

-O
Output Compare register i (OCRi) 2ED3

( s )
Output Compare flag i (OCFi)

ct
OCMPi pin (OLVLi = 1)

d u
o
Figure 33. Output compare timing diagram, fTIMER = fCPU/4
r
e P
l e t Internal CPU clock

s o Timer clock

O b Counter register

Output Compare register i (OCRi)

2ECF 2ED0 2ED1 2ED2 2ED3 2ED4

2ED3

Output Compare flag i (OCFi)

OCMPi pin (OLVLi = 1)

57/139
Watchdog timer (WDG) ST7260xx

One pulse mode

One Pulse mode enables the generation of a pulse when an external event occurs. This
mode is selected via the OPM bit in the CR2 register.
The one pulse mode uses the Input Capture1 function and the Output Compare1 function.
Procedure
To use One Pulse mode:
1. Load the OC1R register with the value corresponding to the length of the pulse (see the
formula below).
2. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the
s )
t(
pulse.
–
c
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the
pulse.
u
–
od
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the

3.
ICAP1 pin must be configured as floating input).
Select the following in the CR2 register: P r
–
t e
Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1
function.
o le
–
–
Set the OPM bit.

b s
Select the timer clock CC[1:0] (see Table 32).

Figure 34. One pulse mode cycle

- O
( s )
c t
u When ICR1 = Counter

d
event occurs OCMP1 = OLVL2
on ICAP1

o Counter is reset

Pr
to FFFCh
ICF1 bit is set

ete
When
counter =

o l OC1R OCMP1 = OLVL1

s
Ob
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is
loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R
register.
Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the
ICIE bit is set.
Clearing the Input Capture interrupt request (that is, clearing the ICFi bit) is done in two
steps:
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.

58/139
 ST7260xx Watchdog timer (WDG)

The OC1R register value required for a specific timing application can be calculated using
the following formula:

t f -5
OCiR value = * CPU
PRESC

Where:
t = Pulse period (in seconds)
fCPU = CPU clock frequnency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits; see Table 32)
If the timer clock is an external clock the formula is:

s )
t(
OCiR = t * fEXT - 5

Where:
u c
t = Pulse period (in seconds)
o d
fEXT = External timer clock frequency (in hertz)
P r
e
When the value of the counter is equal to the value of the contents of the OC1R register, the
t
le
OLVL1 bit is output on the OCMP1 pin (see Figure 35).
Note: 1
o
The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate
an Output Compare interrupt.
s
2
O b
When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.

) -
3
4
t ( s
If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin.
The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to
c
perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take
u
o d
care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can
also generates interrupt if ICIE is set.
5
P r
When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and

te
OCF2 can be used to indicate a period of time has been elapsed but cannot generate an
output waveform because the level OLVL2 is dedicated to the one pulse mode.
e
o l Figure 35. One Pulse mode timing example(1)

b s
O IC1R 01F8 2ED3

01F8 FFFC FFFD FFFE 2ED0 2ED1 2ED2 FFFC FFFD

Counter
2ED3

ICAP1

OLVL2 OLVL1 OLVL2

OCMP1
Compare1

1. IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1

59/139
 Watchdog timer (WDG) ST7260xx

Figure 36. Pulse width modulation mode timing example with two output compare
functions(1)(2)

Counter 34E2 FFFC FFFD FFFE 2ED0 2ED1 2ED2 34E2 FFFC

OCMP1 OLVL2 OLVL1 OLVL2

compare2 compare1 compare2

1. OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1

s )
2. On timers with only one Output Compare register, a fixed frequency PWM signal can be generated using
the output compare and the counter overflow to define the pulse length.

c t(
Pulse width modulation mode

d u
and pulse length determined by the value of the OC1R and OC2R registers.
r o
Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency

P
Pulse Width Modulation mode uses the complete Output Compare 1 function plus the
e
t
OC2R register, and so this functionality can not be used when PWM mode is activated.

le
s o
In PWM mode, double buffering is implemented on the output compare registers. Any new
values written in the OC1R and OC2R registers are taken into account only at the end of the
b
PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1).
O
Procedure

) -
1.
t s
To use Pulse Width Modulation mode:
(
Load the OC2R register with the value corresponding to the period of the signal using
the formula below.
u c
2.
d
Load the OC1R register with the value corresponding to the period of the pulse if
o
3.
P r
(OLVL1 = 0 and OLVL2 = 1) using the formula in the opposite column.
Select the following in the CR1 register:

e t e– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with the OC1R register.

o l – Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a

b s successful comparison with the OC2R register.

O 4. Select the following in the CR2 register:

– Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.
– Set the PWM bit.
– Select the timer clock (CC[1:0]) (see Table 32).

60/139
ST7260xx Watchdog timer (WDG)

Figure 37. Pulse width modulation cycle

When
counter OCMP1 = OLVL1
= OC1R

When OCMP1 = OLVL2

counter counter is reset
= OC2R to FFFCh
ICF1 bit is set

s )
OC2R and OC1R registers.
c t(
If OLVL1 = 1 and OLVL2 = 0, the length of the positive pulse is the difference between the

If OLVL1 = OLVL2, a continuous signal will be seen on the OCMP1 pin.

d u
r o
The OC1R register value required for a specific timing application can be calculated using
the following formula:
e P
t f
OCiR value = * CPU
le t
-5

s o
PRESC

Where:
O b
t
fCPU
) -
= Signal or pulse period (in seconds)
= CPU clock frequnency (in hertz)

( s
PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits; see Table 32)
t
c
If the timer clock is an external clock the formula is:
u
o d OCiR = t * fEXT - 5

P
Where:
r
e
t te = Signal or pulse period (in seconds)

o l fEXT = External timer clock frequency (in hertz)

bs
The Output Compare 2 event causes the counter to be initialized to FFFCh (see Figure 36).

O
Note: 1 After a write instruction to the OCiHR register, the output compare function is inhibited until
the OCiLR register is also written.
2 The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
3 The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce
a timer interrupt if the ICIE bit is set and the I bit is cleared.
4 In PWM mode the ICAP1 pin can not be used to perform input capture because it is
disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be
set and IC2R can be loaded) but the user must take care that the counter is reset each
period and ICF1 can also generates interrupt if ICIE is set.
5 When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.

61/139
 Watchdog timer (WDG) ST7260xx

12.4.4 Low power modes

Table 28. Effect of low power modes on 16-bit timer

Mode Description

No effect on 16-bit timer.

Wait
Timer interrupts cause the device to exit from Wait mode.
16-bit timer registers are frozen.
In Halt mode, the counter stops counting until Halt mode is exited. Counting resumes
from the previous count when the MCU is woken up by an interrupt with Exit from Halt
mode capability or from the counter reset value when the MCU is woken up by a reset.
Halt

armed. Consequently, when the MCU is woken up by an interrupt with Exit from Halt
s )
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is

mode is captured into the ICiR register.

c t(
mode capability, the ICFi bit is set, and the counter value present when exiting from Halt

d u
12.4.5 Interrupts
r o
Table 29. 16-bit timer interrupt control/wake-up capability
e P (1)

Interrupt event Event flag Enable control bit

le t Exit from Wait Exit from Halt

Input Capture 1 event/counter

ICF1
s o
reset in PWM mode
Input Capture 2 event ICF2
O b ICIE

Output Compare 1 event

) -
OCF1 Yes No
(not available in PWM mode)

t ( s OCIE
Output Compare 2 event

u
(not available in PWM mode) c OCF2

o d
Timer Overflow event TOF TOIE

P r
1. The 16-bit timer interrupt events are connected to the same interrupt vector (see Section 8: Interrupts).
These events generate an interrupt if the corresponding Enable Control bit is set and the interrupt mask in

e t e
the CC register is reset (RIM instruction).

o l
b s
O

62/139
 ST7260xx Watchdog timer (WDG)

12.4.6 Summary of timer modes

Table 30. Summary of timer modes

Timer resources
Mode
Input Input Output Output
capture 1 capture 2 compare 1 compare 2

Input Capture
(1 and/or 2)
Yes Yes Yes Yes
Output Compare
(1 and/or 2)
One Pulse mode Not recommended(1)
s )
Partially(2)
No
recommended(3)
No
t(
uc
PWM mode Not No

d
1. See note 4 in One pulse mode on page 58.
2. See note 5 in One pulse mode on page 58.

r o
3. See note 4 in Pulse width modulation mode on page 60.

e P
et
12.4.7 16-bit timer registers

o l
Each timer is associated with three control and status registers, and with six pairs of data

counter and the alternate counter. b s

registers (16-bit values) relating to the two input captures, the two output compares, the

Control Register 1 (CR1)

- O
( s )
ct
CR1 Reset value: 0000 0000 (00h)

du
7 6 5 4 3 2 1 0

ICIE

P
R/W
ro
OCIE

R/W
TOIE

R/W
FOLV2

R/W
FOLV1

R/W
OLVL2

R/W
IEDG1

R/W
OLVL1

R/W

e tM
e
o l Table 31.
Bit Name
CR1 register description
Function

b s Input Capture Interrupt Enable

O 7 ICIE 0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is
set.
Output Compare Interrupt Enable
0: Interrupt is inhibited.
6 OCIE
1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register
is set.
Timer Overflow Interrupt Enable
5 TOIE 0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.

63/139
Watchdog timer (WDG) ST7260xx

Table 31. CR1 register description (continued)

Bit Name Function

Forced Output compare 2

This bit is set and cleared by software.
4 FOLV2 0: No effect on the OCMP2 pin.
1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and
even if there is no successful comparison.
Forced Output compare 1
This bit is set and cleared by software.
3 FOLV1 0: No effect on the OCMP1 pin.
1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if
there is no successful comparison.
s )
Output Level 2

c t(
2 OLVL2

d u
This bit is copied to the OCMP2 pin whenever a successful comparison occurs with
the OC2R register and OCxE is set in the CR2 register. This value is copied to the
OCMP1 pin in One Pulse mode and Pulse Width modulation mode.
r o
Input Edge 1

e P
This bit determines which type of level transition on the ICAP1 pin will trigger the
1 IEDG1 capture.
0: A falling edge triggers the capture.
le t
o
1: A rising edge triggers the capture.
s
0 OLVL1
Output Level 1

O b
The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison

-
occurs with the OC1R register and the OC1E bit is set in the CR2 register.

)
Control Register 2 (CR2)
t ( s
u c
CR2

o d Reset value: 0000 0000 (00h)

Pr
7 6 5 4 3 2 1 0

OC1E OC2E OPM PWM CC[1:0] IEDG2 EXEDG

e t e R/W R/W R/W R/W R/W R/W R/W

l
so
M

Table 32. CR2 register description

Ob
Bit Name Function

Output Compare 1 Pin Enable

This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in
Output Compare mode, both OLV1 and OLV2 in PWM and One-Pulse mode).
7 OCIE Whatever the value of the OC1E bit, the Output Compare 1 function of the timer
remains active.
0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
Output Compare 2 Pin Enable
This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in
Output Compare mode). Whatever the value of the OC2E bit, the Output Compare 2
6 OC2E
function of the timer remains active.
0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.

64/139
ST7260xx Watchdog timer (WDG)

Table 32. CR2 register description (continued)

Bit Name Function

One Pulse Mode

0: One Pulse mode is not active.
5 OPM 1: One Pulse mode is active, the ICAP1 pin can be used to trigger one pulse on the
OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the
generated pulse depends on the contents of the OC1R register.
Pulse Width Modulation
0: PWM mode is not active.
4 PWM 1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the
length of the pulse depends on the value of OC1R register; the period depends on
the value of OC2R register.
s )
Clock Control

c t(
The timer clock mode depends on these bits.
00: Timer clock = fCPU/4
d u
3:2 CC[1:0]
01: Timer clock = fCPU/2
10: Timer clock = fCPU/8
r o
11: Timer clock = external clock (where available)

e P
configuration stops the counter.
le t
Note: If the external clock pin is not available, programming the external clock

Input Edge 2
s o
1 IEDG2 capture.
O b
This bit determines which type of level transition on the ICAP2 pin will trigger the

0: A falling edge triggers the capture.

-
1: A rising edge triggers the capture.
)
External Clock Edge
t ( s
0 EXEDG c
This bit determines which type of level transition on the external clock pin EXTCLK

u
will trigger the counter register.

d
0: A falling edge triggers the counter register.

o
P r 1: A rising edge triggers the counter register.

Control/Status Register (CSR)

e t e
o l CSR Reset value: xxxx x0xx (xxh)

bs
7 6 5 4 3 2 1 0

O ICF1

RO
OCF1

RO
TOF

RO
ICF2

RO
OCF2

RO
TIMD

R/W
Reserved

-
M

Table 33. CSR register description

Bit Name Function

Input Capture Flag 1

0: No Input Capture (reset value).
7 ICF1 1: An Input Capture has occurred on the ICAP1 pin or the counter has reached the
OC2R value in PWM mode. To clear this bit, first read the SR register, then read or
write the low byte of the IC1R (IC1LR) register.

65/139
 Watchdog timer (WDG) ST7260xx

Table 33. CSR register description (continued)

Bit Name Function

Output Compare Flag 1

0: No match (reset value).
6 OCF1 1: The content of the free running counter has matched the content of the OC1R
register. To clear this bit, first read the SR register, then read or write the low byte of
the OC1R (OC1LR) register.
Timer Overflow Flag
0: No timer overflow (reset value).
5 TOF 1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first
read the SR register, then read or write the low byte of the CR (CLR) register.
Note: Reading or writing the ACLR register does not clear TOF.
s )
Input Capture Flag 2

c t(
4 ICF2 0: No input capture (reset value).

d u
1: An Input Capture has occurred on the ICAP2 pin. To clear this bit, first read the SR

o
register, then read or write the low byte of the IC2R (IC2LR) register.
r
Output Compare Flag 2
0: No match (reset value).
e P
3 OCF2
t
1: The content of the free running counter has matched the content of the OC2R

le
register. To clear this bit, first read the SR register, then read or write the low byte of
the OC2R (OC2LR) register.
s o
Timer Disable

O b
This bit is set and cleared by software. When set, it freezes the timer prescaler and

2 TIMD -
counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce

)
power consumption. Access to the timer registers is still available, allowing the timer

( s
configuration to be changed, or the counter reset, while it is disabled.
t
u c
0: Timer enabled.
1: Timer prescaler, counter and outputs disabled.
1:0 -
o d
Reserved, must be kept cleared.

P r
Input capture 1 high register (IC1HR)

t e
This is an 8-bit register that contains the high part of the counter value (transferred by the
e
o l input capture 1 event).

b s IC1HR Reset value: undefined

O 7

MSB
6 5 4 3 2 1 0

LSB

RO RO RO RO RO RO RO RO

66/139
 ST7260xx Watchdog timer (WDG)

Input capture 1 low register (IC1LR)

This is an 8-bit register that contains the low part of the counter value (transferred by the
input capture 1 event).

IC1LR Reset value: undefined

7 6 5 4 3 2 1 0

MSB LSB

RO RO RO RO RO RO RO RO

Output compare 1 high register (OC1HR)

s )
register.
c t(
This is an 8-bit register that contains the high part of the value to be compared to the CHR

d u
OC1HR
r o
Reset value: 1000 0000 (80h)
7 6 5 4 3

e P
2 1 0

MSB

le t LSB

so
R/W R/W R/W R/W R/W R/W R/W R/W

Output compare 1 low register (OC1LR)

O b
This is an 8-bit register that contains the low part of the value to be compared to the CLR
register.
) -
( s
OC1LR
ct Reset value: 0000 0000 (00h)

du
7 6 5 4 3 2 1 0

MSB
r o LSB

e
R/W P R/W R/W R/W R/W R/W R/W R/W

e t
ol
Output compare 2 high register (OC2HR)

b s This is an 8-bit register that contains the high part of the value to be compared to the CHR
register.

O OC2HR Reset value: 1000 0000 (80h)

7 6 5 4 3 2 1 0

MSB LSB

R/W R/W R/W R/W R/W R/W R/W R/W

67/139
Watchdog timer (WDG) ST7260xx

Output compare 2 low register (OC2LR)

This is an 8-bit register that contains the low part of the value to be compared to the CLR
register.

OC2LR Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1 0

MSB LSB

R/W R/W R/W R/W R/W R/W R/W R/W

Counter high register (CHR)

s )
This is an 8-bit register that contains the high part of the counter value.

c t(
CHR
d u
Reset value: 1111 1111 (FFh)
7 6 5 4 3 2
r o 1 0

MSB

e P LSB

RO RO RO RO RO
le t RO RO RO

Counter low register (CLR)

s o
O b
This is an 8-bit register that contains the low part of the counter value. A write to this register
resets the counter. An access to this register after accessing the CSR register clears the
TOF bit.
) -
t ( s
CLR
c Reset value: 1111 1100 (FCh)

du
7 6 5 4 3 2 1 0

MSB
r o LSB

RO
e P RO RO RO RO RO RO RO

e t
ol
Alternate counter high register (ACHR)

bs
This is an 8-bit register that contains the high part of the counter value.

O ACHR
7 6 5 4 3 2
Reset value: 1111 1111 (FFh)
1 0

MSB LSB

RO RO RO RO RO RO RO RO

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ST7260xx Watchdog timer (WDG)

Alternate counter low register (ACLR)

This is an 8-bit register that contains the low part of the counter value. A write to this register
resets the counter. An access to this register after an access to CSR register does not clear
the TOF bit in the CSR register.

ACLR Reset value: 1111 1100 (FCh)

7 6 5 4 3 2 1 0

MSB LSB

RO RO RO RO RO RO RO RO

Input capture 2 high register (IC2HR)

s )
c t(
This is an 8-bit register that contains the high part of the counter value (transferred by the
Input Capture 2 event).
d u
1C2HR
r o Reset value: undefined
7 6 5 4 3
e P
2 1 0

e t
ol
MSB LSB

bs
RO RO RO RO RO RO RO RO

Input capture 2 low register (IC2LR)

- O
Input Capture 2 event).
( s )
This is an 8-bit register that contains the low part of the counter value (transferred by the

c t
du
1C2LR Reset value: undefined
7

r o 6 5 4 3 2 1 0

e
MSB
P LSB

l e t RO RO RO RO RO RO RO RO

s o
Ob

69/139
 Watchdog timer (WDG) ST7260xx

Table 34. 16-bit timer register map and reset values

Address Register
7 6 5 4 3 2 1 0
(Hex.) label

CR1 ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

11
Reset value 0 0 0 0 0 0 0 0
CR2 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
12
Reset value 0 0 0 0 0 0 0 0
CSR ICF1 OCF1 TOF ICF2 OCF2 TIMD - -
13
Reset value x x x x x 0 x x
IC1HR MSB LSB
14
Reset value x x x x x x x
s )
x

15
IC1LR
Reset value
MSB
x x x x x x x
c t( LSB
x
OC1HR MSB
d u LSB
16
Reset value 1 0 0 0 0
r0
o 0 0

17
OC1LR
Reset value
MSB
0 0 0 0 0
e P 0 0
LSB
0

18
CHR MSB
le t LSB
Reset value 1 1 1

s o
1 1 1 1 1

19
CLR
Reset value
MSB
1 1 1
O b 1 1 1 0
LSB
0

1A
ACHR
Reset value
MSB
1 1
) -1 1 1 1 1
LSB
1
ACLR MSB
t ( s LSB
1B
Reset value 1
u c 1 1 1 1 1 0 0

1C
IC2HR

o d
MSB LSB

1D P
IC2LR r
Reset value x
MSB
x x x x x x x
LSB

e te
Reset value x x x x x x x x

1E
o l OC2HR
Reset value
MSB
1 0 0 0 0 0 0
LSB
0

b s 1F
OC2LR
Reset value
MSB
0 0 0 0 0 0 0
LSB
0
O

70/139
 ST7260xx Serial communications interface (SCI)

13 Serial communications interface (SCI)

13.1 Introduction
The Serial Communications Interface (SCI) offers a flexible means of full-duplex data
exchange with external equipment requiring an industry standard NRZ asynchronous serial
data format. The SCI offers a very wide range of baud rates using two baud rate generator
systems.

13.2 Main features

s )
●
●
Full duplex, asynchronous communications
NRZ standard format (Mark/Space)
c t(
●
d u
Independently programmable transmit and receive baud rates up to 250K baud.
● Programmable data word length (8 or 9 bits)
r o
●
P
Receive buffer full, Transmit buffer empty and End of Transmission flags

e
● Two receiver wake-up modes:
– Address bit (MSB)
le t
– Idle line
s o
●
●
O b
Muting function for multiprocessor configurations
Separate enable bits for Transmitter and Receiver
● Four error detection flags:
) -
– Overrun error
t ( s
–
–
Noise error

u
Frame error c
–
o d
Parity error
●
P r
Six interrupt sources with flags:

e t e – Transmit data register empty

o l –
–
Transmission complete
Receive data register full

b s – Idle line received

O –
–
Overrun error detected
Parity error
● Parity control:
– Transmits parity bit
– Checks parity of received data byte
● Reduced power consumption mode

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 Serial communications interface (SCI) ST7260xx

13.2.1 General description

The interface is externally connected to another device by two pins (see Figure 39):
● TDO: Transmit Data Output. When the transmitter and the receiver are disabled, the
output pin returns to its I/O port configuration. When the transmitter and/or the receiver
are enabled and nothing is to be transmitted, the TDO pin is at high level.
● RDI: Receive Data Input is the serial data input. Oversampling techniques are used for
data recovery by discriminating between valid incoming data and noise.
Through these pins, serial data is transmitted and received as frames comprising:
● An Idle Line prior to transmission or reception
● A start bit
● A data word (8 or 9 bits) least significant bit first
s )
● A Stop bit indicating that the frame is complete.
c t(
This interface uses two types of baud rate generator:
d u
● A conventional type for commonly-used baud rates.
r o
e P
le t
s o
O b
) -
t ( s
u c
o d
P r
e t e
o l
b s
O

72/139
 ST7260xx Serial communications interface (SCI)

Figure 38. SCI block diagram

Write Read (DATA REGISTER) DR

Transmit Data Register (TDR) Received Data Register (RDR)

TDO

Transmit Shift Register Received Shift Register

RDI
CR1
R8 T8 SCID M WAKE PCE PS PIE

s )
c t(
d u
ro
WAKE
TRANSMIT UP RECEIVER RECEIVER
CLOCK

P
CONTROL UNIT CONTROL

CR2

et e SR
TIE TCIE RIE ILIE TE RE RWU SBK
l
TDRE TC RDRF IDLE OR

o
NF FE PE

SCI
b s
INTERRUPT
CONTROL
- O
TRANSMITTER

( s )
ct
CLOCK
TRANSMITTER RATE

du
CONTROL
fCPU
/16 /PR

ro
BRR

e P SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0

l e t RECEIVER RATE

s o CONTROL

O b BAUD RATE GENERATOR

13.2.2 Functional description

The block diagram of the Serial Control Interface, is shown in Figure 38. It contains 6
dedicated registers:
● Two control registers (SCICR1 & SCICR2)
● A status register (SCISR)
● A baud rate register (SCIBRR)
Refer to the register descriptions in Section 13.3 for the definitions of each bit.

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 Serial communications interface (SCI) ST7260xx

Serial data format

Word length may be selected as being either 8 or 9 bits by programming the M bit in the
SCICR1 register (see Figure 38).
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next
frame which contains data.
A Break character is interpreted on receiving “0”s for some multiple of the frame period. At
the end of the last break frame the transmitter inserts an extra “1” bit to acknowledge the
start bit.

s )
Transmission and reception are driven by their own baud rate generator.

c t(
Figure 39. Word length programming
d u
r o
9-bit Word length (M bit is set)

e
Possible
Parity P Next Data Frame

Start
Bit Bit0 Bit1
Data Frame

Bit2 Bit3 Bit4 Bit5 Bit6

le t
Bit7
Bit
Bit8
Next
Stop Start
Bit

o
Bit

Idle Frame
b s Start
Bit

- O Start

)
Break Frame Extra
’1’ Bit

t ( s
c
8-bit Word length (M bit is reset)

du
Possible Next Data Frame
Data Frame Parity
Bit

ro
Next
Start Stop Start
Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit
Bit

e P Start

l e t Idle Frame Bit

s o Break Frame Extra Start

’1’ Bit

O b Transmitter
The transmitter can send data words of either 8 or 9 bits depending on the M bit status.
When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the
T8 bit in the SCICR1 register.
Character Transmission
During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this
mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the
transmit shift register (see Figure 38).

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 ST7260xx Serial communications interface (SCI)

Procedure
● Select the M bit to define the word length.
● Select the desired baud rate using the SCIBRR and the SCIETPR registers.
● Set the TE bit to assign the TDO pin to the alternate function and to send a idle frame
as first transmission.
● Access the SCISR register and write the data to send in the SCIDR register (this
sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted.
Clearing the TDRE bit is always performed by the following software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
The TDRE bit is set by hardware and it indicates:
s )
● The TDR register is empty.
c t(
●
●
The data transfer is beginning.
d u
data.
r o
The next data can be written in the SCIDR register without overwriting the previous

P
This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR
e
register.

le t
s o
When a transmission is taking place, a write instruction to the SCIDR register stores the
data in the TDR register and which is copied in the shift register at the end of the current
transmission.

O b
) -
When no transmission is taking place, a write instruction to the SCIDR register places the
data directly in the shift register, the data transmission starts, and the TDRE bit is
immediately set.
t ( s
u c
When a frame transmission is complete (after the stop bit or after the break frame) the TC
bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the CCR
register.
o d
P r
Clearing the TC bit is performed by the following software sequence:
1.

e
2.t eAn access to the SCISR register
A write to the SCIDR register
Note:
o l The TDRE and TC bits are cleared by the same software sequence.

b s Break characters

O Setting the SBK bit loads the shift register with a break character. The break frame length
depends on the M bit (see Figure 39).
As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this
bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the
recognition of the start bit of the next frame.
Idle characters
Setting the TE bit drives the SCI to send an idle frame before the first data frame.
Clearing and then setting the TE bit during a transmission sends an idle frame after the
current word.

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Serial communications interface (SCI) ST7260xx

Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit is set i.e. before writing the next byte in
the SCIDR.

Receiver
The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9
bits and the MSB is stored in the R8 bit in the SCICR1 register.
Character reception
During a SCI reception, data shifts in least significant bit first through the RDI pin. In this
mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the
received shift register (see <Blue HT>Figure 38).

s )
t(
Procedure
● Select the M bit to define the word length.
u c
● Select the desired baud rate using the SCIBRR and the SCIERPR registers.

o d
●
r
Set the RE bit, this enables the receiver which begins searching for a start bit.
When a character is received:
P
●
t e
The RDRF bit is set. It indicates that the content of the shift register is transferred to the

●
RDR.

o le
An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register.
●
b s
The error flags can be set if a frame error, noise or an overrun error has been detected
during reception.

- O
Clearing the RDRF bit is performed by the following software sequence done by:
1.
( s )
An access to the SCISR register
2.
c t
A read to the SCIDR register

d u
The RDRF bit must be cleared before the end of the reception of the next character to avoid

o
an overrun error.
r
P
Break Character

e
l e t
When a break character is received, the SCI handles it as a framing error.
Idle Character
o
bs
When a idle frame is detected, there is the same procedure as a data received character
plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR register.
O Overrun Error
An overrun error occurs when a character is received when RDRF has not been reset. Data
can not be transferred from the shift register to the RDR register as long as the RDRF bit is
not cleared.
When a overrun error occurs:
● The OR bit is set.
● The RDR content will not be lost.
● The shift register will be overwritten.
● An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register.
The OR bit is reset by an access to the SCISR register followed by a SCIDR register read
operation.

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 ST7260xx Serial communications interface (SCI)

Noise error
Oversampling techniques are used for data recovery by discriminating between valid
incoming data and noise. Normal data bits are considered valid if three consecutive samples
(8th, 9th, 10th) have the same bit value, otherwise the NF flag is set. In the case of start bit
detection, the NF flag is set on the basis of an algorithm combining both valid edge
detection and three samples (8th, 9th, 10th). Therefore, to prevent the NF flag getting set
during start bit reception, there should be a valid edge detection as well as three valid
samples.
When noise is detected in a frame:
● The NF flag is set at the rising edge of the RDRF bit.
● Data is transferred from the Shift register to the SCIDR register.

s )
t(
● No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt.

u c
The NF flag is reset by a SCISR register read operation followed by a SCIDR register read
operation.
o d
P r
During reception, if a false start bit is detected (e.g. 8th, 9th, 10th samples are
011,101,110), the frame is discarded and the receiving sequence is not started for this

t e
frame. There is no RDRF bit set for this frame and the NF flag is set internally (not

frame is received.
o le
accessible to the user). This NF flag is accessible along with the RDRF bit when a next valid

Note:
b s
If the application Start Bit is not long enough to match the above requirements, then the NF

- O
Flag may get set due to the short Start Bit. In this case, the NF flag may be ignored by the
application software when the first valid byte is received.
See also Noise error causes.
( s )
Framing Error
c t
d u
A framing error is detected when:
●
r o
The stop bit is not recognized on reception at the expected time, following either a de-

●
e P
synchronization or excessive noise.
A break is received.

l e t
When the framing error is detected:

s o ● The FE bit is set by hardware

O b ●
●
Data is transferred from the Shift register to the SCIDR register.
No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt.
The FE bit is reset by a SCISR register read operation followed by a SCIDR register read
operation.

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Serial communications interface (SCI) ST7260xx

Baud rate generation

The baud rate for the receiver and transmitter (Rx and Tx) are set independently and
calculated as follows:
fCPU fCPU
Tx = Rx =
(16*PR)*TR (16*PR)*RR

with:
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64,128
(see SCT[2:0] bits)

s )
t(
RR = 1, 2, 4, 8, 16, 32, 64,128
(see SCR[2:0] bits)
u c
All these bits are in the SCIBRR register.
o d
receive baud rates are 38400 baud.
P r
Example: If fCPU is 8 MHz (normal mode) and if PR=13 and TR=RR=1, the transmit and

Note:
t e
The baud rate registers MUST NOT be changed while the transmitter or the receiver is
enabled.
o le
Receiver muting and wake-up feature
b s
- O
In multiprocessor configurations it is often desirable that only the intended message
recipient should actively receive the full message contents, thus reducing redundant SCI

s )
service overhead for all non addressed receivers.
(
t
The non addressed devices may be placed in sleep mode by means of the muting function.
c
u
Setting the RWU bit by software puts the SCI in sleep mode:
d
r o
All the reception status bits can not be set.

P
All the receive interrupts are inhibited.

e
l ●
t
A muted receiver may be awakened by one of the following two ways:
e by Idle Line detection if the WAKE bit is reset,
o
bs
● by Address Mark detection if the WAKE bit is set.
Receiver wakes-up by Idle Line detection when the Receive line has recognised an Idle
O Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set.
Receiver wakes-up by Address Mark detection when it received a “1” as the most significant
bit of a word, thus indicating that the message is an address. The reception of this particular
word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the
receiver to receive this word normally and to use it as an address word.
Caution: In Mute mode, do not write to the SCICR2 register. If the SCI is in Mute mode during the
read operation (RWU=1) and a address mark wake up event occurs (RWU is reset) before
the write operation, the RWU bit will be set again by this write operation. Consequently the
address byte is lost and the SCI is not woken up from Mute mode.

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ST7260xx Serial communications interface (SCI)

Parity control
Parity control (generation of parity bit in transmission and parity checking in reception) can
be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length
defined by the M bit, the possible SCI frame formats are as listed in Table 35.

Table 35. Frame formats

M bit PCE bit SCI frame

0 0 | SB | 8 bit data | STB |

0 1 | SB | 7-bit data | PB | STB |
1 0 | SB | 9-bit data | STB |

s )
t(
1 1 | SB | 8-bit data PB | STB |

Legend: SB = Start Bit, STB = Stop Bit,

u c
PB = Parity Bit

o d
Note:
r
In case of wake up by an address mark, the MSB bit of the data is taken into account and
not the parity bit
P
t e
Even parity: the parity bit is calculated to obtain an even number of “1s” inside the frame

le
made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.

o
b s
Ex: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (PS bit = 0).
Odd parity: the parity bit is calculated to obtain an odd number of “1s” inside the frame
O
made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
-
( s )
Ex: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (PS bit = 1).

t
Transmission mode: If the PCE bit is set then the MSB bit of the data written in the data
c
d u
register is not transmitted but is changed by the parity bit.
Reception mode: If the PCE bit is set then the interface checks if the received data byte

r o
has an even number of “1s” if even parity is selected (PS=0) or an odd number of “1s” if odd

e P
parity is selected (PS=1). If the parity check fails, the PE flag is set in the SCISR register
and an interrupt is generated if PIE is set in the SCICR1 register.

l e t
SCI clock tolerance
o
Obs During reception, each bit is sampled 16 times. The majority of the 8th, 9th and 10th
samples is considered as the bit value. For a valid bit detection, all the three samples should
have the same value otherwise the noise flag (NF) is set. For example: if the 8th, 9th and
10th samples are 0, 1 and 1 respectively, then the bit value will be “1”, but the Noise Flag bit
is be set because the three samples values are not the same.
Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples
have the desired bit value. This means the clock frequency should not vary more than 6/16
(37.5%) within one bit. The sampling clock is resynchronized at each start bit, so that when
receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed
3.75%.
Note: The internal sampling clock of the microcontroller samples the pin value on every falling
edge. Therefore, the internal sampling clock and the time the application expects the
sampling to take place may be out of sync. For example: If the baud rate is 15.625 kbaud (bit
length is 64 µs), then the 8th, 9th and 10th samples will be at 28 µs, 32 µs & 36 µs
respectively (the first sample starting ideally at 0µs). But if the falling edge of the internal

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Serial communications interface (SCI) ST7260xx

clock occurs just before the pin value changes, the samples would then be out of sync by
~4 µs. This means the entire bit length must be at least 40 µs (36µs for the 10th sample +
4 µs for synchronization with the internal sampling clock).

Clock deviation causes

The causes which contribute to the total deviation are:
● DTRA: Deviation due to transmitter error (Local oscillator error of the transmitter or the
transmitter is transmitting at a different baud rate).
● DQUANT: Error due to the baud rate quantisation of the receiver.
● DREC: Deviation of the local oscillator of the receiver: This deviation can occur during
the reception of one complete SCI message assuming that the deviation has been
compensated at the beginning of the message.
s )
●
t(
DTCL: Deviation due to the transmission line (generally due to the transceivers)
c
u
All the deviations of the system should be added and compared to the SCI clock tolerance:
d
DTRA + DQUANT + DREC + DTCL < 3.75%
r o
Noise error causes
e P
t
See also description of Noise error in Receiver on page 76.
le
Start bit
s o
Note: 1
b
The noise flag (NF) is set during start bit reception if one of the following conditions occurs:

O
A valid falling edge is not detected. A falling edge is considered to be valid if the 3
-
consecutive samples before the falling edge occurs are detected as '1' and, after the falling
)
7 is detected as a “1”.
t ( s
edge occurs, during the sampling of the 16 samples, if one of the samples numbered 3, 5 or

2
u c
During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is detected as
a “1”.
o d
P r
Therefore, a valid Start Bit must satisfy both the above conditions to prevent the Noise Flag
getting set.

t e
Data bits
e
o l The noise flag (NF) is set during normal data bit reception if the following condition occurs:

bs
● During the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not
the same. The majority of the 8th, 9th and 10th samples is considered as the bit value.
O Therefore, a valid Data Bit must have samples 8, 9 and 10 at the same value to prevent the
Noise Flag getting set.

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ST7260xx Serial communications interface (SCI)

Figure 40. Bit sampling in reception mode

RDI LINE

sampled values
Sample
clock 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

6/16

7/16 7/16
One bit time

s )
13.2.3 Low power modes
c t(
d u
Table 36. Effect of low power modes on SCI
r o
Mode Description

e P
Wait
No effect on SCI.
SCI interrupts cause the device to exit from Wait mode.
le t
Halt
SCI registers are frozen.
s o
b
In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.

O
13.2.4 Interrupts
) -
t ( s
The SCI interrupt events are connected to the same interrupt vector.

c
These events generate an interrupt if the corresponding Enable Control bit is set and the
u
d
interrupt mask in the CC register is reset (RIM instruction).

o
Table 37.
Pr SCI interrupt control/wake-up capability

ete
Interrupt event Event flag Enable control bit Exit from Wait Exit from Halt

ol
Transmit data register empty TDRE TIE Yes No

bs
Transmission complete TC TCIE Yes No
Received data ready to be read RDRF Yes No

O Overrun error detected OR

RIE
Yes No
Idle line detected IDLE ILIE Yes No
Parity error PE PIE Yes No

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 Serial communications interface (SCI) ST7260xx

13.3 Register description

13.3.1 Status register (SCISR)

SCISR Reset value: 1100 0000 (C0h)

7 6 5 4 3 2 1 0

TDRE TC RDRF IDLE OR NF FE PE

R R R R R R R R

Table 38. SCISR register description

s )
t(
Bit Name Function

Transmit Data Register Empty

u c
o d
This bit is set by hardware when the content of the TDR register has been transferred
into the shift register. An interrupt is generated if the TIE bit = 1 in the SCICR2
7 TDRE
followed by a write to the SCIDR register). r
register. It is cleared by a software sequence (an access to the SCISR register

P
0: Data is not transferred to the shift register.
t e
le
1: Data is transferred to the shift register.
Note: Data will not be transferred to the shift register unless the TDRE bit is cleared.
Transmission Complete
s o
O b
This bit is set by hardware when transmission of a frame containing data is complete.
An interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared by a
6 TC
) -
software sequence (an access to the SCISR register followed by a write to the

t ( s
SCIDR register).
0: Transmission is not complete

u c
1: Transmission is complete
Note: TC is not set after the transmission of a Preamble or a Break.

o d
Received Data Ready Flag

P r This bit is set by hardware when the content of the RDR register has been
transferred to the SCIDR register. An interrupt is generated if RIE = 1 in the SCICR2

e t
5
eRDRF register. It is cleared by a software sequence (an access to the SCISR register
followed by a read to the SCIDR register).

o l 0: Data is not received

b s 1: Received data is ready to be read

Idle line detect

O This bit is set by hardware when a Idle Line is detected. An interrupt is generated if
the ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access
to the SCISR register followed by a read to the SCIDR register).
4 IDLE
0: No idle line is detected
1: Idle line is detected
Note: The IDLE bit is not reset until the RDRF bit has itself been set (that is, a new
idle line occurs).

82/139
 ST7260xx Serial communications interface (SCI)

Table 38. SCISR register description (continued)

Bit Name Function

Overrun error
This bit is set by hardware when the word currently being received in the shift register
is ready to be transferred into the RDR register while RDRF = 1. An interrupt is
generated if RIE = 1 in the SCICR2 register. It is cleared by a software sequence (an
3 OR access to the SCISR register followed by a read to the SCIDR register).
0: No overrun error
1: Overrun error is detected
Note: When this bit is set RDR register content is not lost but the shift register is
overwritten.
Noise Flag
s )
t(
This bit is set by hardware when noise is detected on a received frame. It is cleared

2 NF SCIDR register). c
by a software sequence (an access to the SCISR register followed by a read to the

u
0: No noise is detected

o d
1: Noise is detected

P r
Note: This bit does not generate interrupt as it appears at the same time as the
RDRF bit which itself generates an interrupt.
Framing Error
t e
le
This bit is set by hardware when a desynchronization, excessive noise or a break
o
b s
character is detected. It is cleared by a software sequence (an access to the SCISR
register followed by a read to the SCIDR register).
1 FE

- O
0: No framing error is detected
1: Framing error or break character is detected

s )
Note: This bit does not generate interrupt as it appears at the same time as the
RDRF bit which itself generates an interrupt. If the word currently being transferred
(
be set.
c t
causes both Frame Error and Overrun error, it is transferred and only the OR bit will

d u
Parity Error

r o This bit is set by hardware when a parity error occurs in receiver mode. It is cleared
0

e P
PE by a software sequence (a read to the status register followed by an access to the
SCIDR data register). An interrupt is generated if PIE = 1 in the SCICR1 register.

l e t 0: No parity error
1: Parity error

s o
O b

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Serial communications interface (SCI) ST7260xx

13.3.2 Control register 1 (SCICR1)

SCICR1 Reset value: x000 0000 (x0h)

7 6 5 4 3 2 1 0

R8 T8 SCID M WAKE PCE PS PIE

R/W R/W R/W R/W R/W R/W R/W R/W

Table 39. SCICR1 register description

Bit Name Function

7 R8
Receive data bit 8

s )
t(
This bit is used to store the 9th bit of the received word when M = 1.

6 T8
Transmit data bit 8
u c
d
This bit is used to store the 9th bit of the transmitted word when M = 1.

o
Disabled for low power consumption

P r
When this bit is set the SCI prescalers and outputs are stopped and the end of the
5 SCID
cleared by software. e
current byte transfer in order to reduce power consumption.This bit is set and

t
0: SCI enabled
1: SCI prescaler and outputs disabled
o le
Word length
b s
4 M
O
This bit determines the word length. It is set or cleared by software.

-
0: 1 Start bit, 8 data bits, 1 Stop bit

( s )
1: 1 Start bit, 9 data bits, 1 Stop bit
Note: The M bit must not be modified during a data transfer (both transmission and

c
reception).
t
u
Wake-Up method
d
3
r
WAKE
o
This bit determines the SCI Wake-Up method, it is set or cleared by software.
0: Idle line

e P 1: Address mark

let
Parity Control Enable
This bit selects the hardware parity control (generation and detection). When the

s o parity control is enabled, the computed parity is inserted at the MSB position (9th bit
if M = 1; 8th bit if M = 0) and parity is checked on the received data. This bit is set

Ob 2 PCE
and cleared by software. Once it is set, PCE is active after the current byte (in
reception and in transmission).
0: Parity control disabled
1: Parity control enabled

84/139
ST7260xx Serial communications interface (SCI)

Table 39. SCICR1 register description (continued)

Bit Name Function

Parity Selection
This bit selects the odd or even parity when the parity generation/detection is
enabled (PCE bit set). It is set and cleared by software. The parity will be selected
1 PS
after the current byte.
0: Even parity
1: Odd parity
Parity Interrupt Enable
This bit enables the interrupt capability of the hardware parity control when a parity
0 PIE error is detected (PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
s )
t(
1: Parity error interrupt enabled

13.3.3 Control register 2 (SCICR2) u c

o d
SCICR2
P r
Reset value: 0000 0000 (00h)
7 6 5 4 3

e t e 2 1 0

ol
TIE TCIE RIE ILIE TE RE RWU SBK

bs
R/W R/W R/W R/W R/W R/W R/W R/W

Table 40.
O
SCICR2 register description
-
Bit Name

( s ) Function

c t
Transmitter Interrupt Enable
This bit is set and cleared by software.
7 TIE
u
0: Interrupt is inhibited
d
o 1: An SCI interrupt is generated whenever TDRE = 1 in the SCISR register.

Pr Transmission Complete Interrupt Enable

This bit is set and cleared by software.

ete
6 TCIE
0: Interrupt is inhibited

o l 1: An SCI interrupt is generated whenever TC = 1 in the SCISR register.

s Receiver interrupt Enable

Ob
This bit is set and cleared by software.
5 RIE 0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR = 1 or RDRF = 1 in the SCISR
register.
Idle Line Interrupt Enable
This bit is set and cleared by software.
4 ILIE
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE = 1 in the SCISR register.

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Serial communications interface (SCI) ST7260xx

Table 40. SCICR2 register description (continued)

Bit Name Function

Transmitter Enable
This bit enables the transmitter. It is set and cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
3 TE Notes:
- During transmission, a ‘0’ pulse on the TE bit (‘0’ followed by ‘1’) sends a preamble
(Idle line) after the current word.
- When TE is set there is a 1 bit-time delay before the transmission starts.
Caution: The TDO pin is free for general purpose I/O only when the TE and RE bits
are both cleared (or if TE is never set).

s )
t(
Receiver Enable
This bit enables the receiver. It is set and cleared by software.
0: Receiver is disabled
u c
2 RE 1: Receiver is enabled and begins searching for a start bit

o d
P r
Note: Before selecting Mute mode (setting the RWU bit), the SCI must first receive
some data, otherwise it cannot function in Mute mode with Wake-Up by Idle line
detection.
Receiver Wake-Up
t e
le
This bit determines if the SCI is in mute mode or not. It is set and cleared by
o
1 RWU
s
software and can be cleared by hardware when a wake-up sequence is recognized.
0: Receiver in Active mode
b
1: Receiver in Mute mode
Send Break
- O
s )
This bit set is used to send break characters. It is set and cleared by software.

(
0 SBK
c t
0: No break character is transmitted.
1: Break characters are transmitted.

d u
Note: If the SBK bit is set to ‘1’ and then to ‘0’, the transmitter will send a Break word
at the end of the current word.

r o
13.3.4 P
Data register (SCIDR)
e
l e t
SCIDR Reset value: undefined (xxh)

o
bs
7 6 5 4 3 2 1 0

O DR7

R/W
DR6

R/W
DR5

R/W
DR4

R/W
DR3

R/W
DR2

R/W
DR1

R/W
DR0

R/W

Contains the Received or Transmitted data character, depending on whether it is read from
or written to.
The Data register performs a double function (read and write) since it is composed of two
registers, one for transmission (TDR) and one for reception (RDR).
The TDR register provides the parallel interface between the internal bus and the output
shift register (see Figure 38).
The RDR register provides the parallel interface between the input shift register and the
internal bus (see Figure 38).

86/139
 ST7260xx Serial communications interface (SCI)

13.3.5 Baud rate register (SCIBRR)

SCIBRR Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1 0

SCP[1:0] SCT[2:0] SCR[2:0]

R/W R/W R/W

Table 41. SCIBRR register description

Bit Name Function

First SCI Prescaler

s )
7:6 SCP[1:0]
These 2 prescaling bits allow several standard clock division ranges.
00: PR prescaling factor = 1
c t(
01: PR prescaling factor = 3
10: PR prescaling factor = 4
d u
11: PR prescaling factor = 13
r o
SCI Transmitter rate divisor

e P
le t
These 3 bits, in conjunction with the SCP1 and SCP0 bits, define the total division
applied to the bus clock to yield the transmit rate clock in conventional baud rate
generator mode.
000: TR dividing factor = 1
s o
5:3 SCT[2:0] 001: TR dividing factor = 2
010: TR dividing factor = 4
O b
) -
011: TR dividing factor = 8
100: TR dividing factor = 16

( s
101: TR dividing factor = 32

t
110: TR dividing factor = 64
c
111: TR dividing factor = 128
u
d
SCI Receiver rate divisor
o
P r These 3 bits, in conjunction with the SCP[1:0] bits, define the total division applied
to the bus clock to yield the receive rate clock in conventional baud rate generator

e t e mode.
000: RR dividing factor = 1

o l 2:0 SCR[2:0] 001: RR dividing factor = 2

010: RR dividing factor = 4

b s 011: RR dividing factor = 8

100: RR dividing factor = 16

O 101: RR dividing factor = 32

110: RR dividing factor = 64
111: RR dividing factor = 128

Table 42. SCI register map and reset values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

SCISR TDRE TC RDRF IDLE OR NF FE PE

20
Reset Value 1 1 0 0 0 0 0 0
SCIDR DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
21
Reset Value x x x x x x x x

87/139
 Serial communications interface (SCI) ST7260xx

Table 42. SCI register map and reset values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

SCIBRR SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0

22
Reset Value 0 0 x x x x x x
SCICR1 R8 T8 SCID M WAKE PCE PS PIE
23
Reset Value x x 0 x x 0 0 0
SCICR2 TIE TCIE RIE ILIE TE RE RWU SBK
24
Reset Value 0 0 0 0 0 0 0 0

s )
c t(
d u
r o
e P
le t
s o
O b
) -
t ( s
u c
o d
P r
e te
o l
b s
O

88/139
 ST7260xx USB interface (USB)

14 USB interface (USB)

14.1 Introduction
The USB Interface implements a low-speed function interface between the USB and the
ST7 microcontroller. It is a highly integrated circuit which includes the transceiver, 3.3
voltage regulator, SIE and DMA. No external components are needed apart from the
external pull-up on USBDM for low speed recognition by the USB host. The use of DMA
architecture allows the endpoint definition to be completely flexible. Endpoints can be
configured by software as in or out.

s )
14.2 Main features
c t(
● USB specification version 1.1 compliant
d u
●
●
Supports Low-Speed USB protocol
r o
feature list and register map)
e P
Two or three Endpoints (including default one) depending on the device (see device

●
●
t
CRC generation/checking, NRZI encoding/decoding and bit-stuffing
le
●
USB Suspend/Resume operations
DMA data transfers
s o
● On-chip 3.3V regulator
O b
● On-chip USB transceiver

) -
t ( s
14.3 Functional description
u c
d
The block diagram in Figure 41, gives an overview of the USB interface hardware.
o
P r
For general information on the USB, refer to the “Universal Serial Bus Specifications”
document available at http//:www.usb.org.

t e
Serial interface engine
e
o l The SIE (Serial Interface Engine) interfaces with the USB, via the transceiver.

b s The SIE processes tokens, handles data transmission/reception, and handshaking as

O required by the USB standard. It also performs frame formatting, including CRC generation
and checking.
Endpoints
The Endpoint registers indicate if the microcontroller is ready to transmit/receive, and how
many bytes need to be transmitted.
DMA
When a token for a valid Endpoint is recognized by the USB interface, the related data
transfer takes place, using DMA. At the end of the transaction, an interrupt is generated.
Interrupts
By reading the Interrupt Status register, application software can know which USB event has
occurred.

89/139
USB interface (USB) ST7260xx

Figure 41. USB block diagram

6 MHz

ENDPOINT
REGISTERS CPU

USBDM
Transceiver Address,
SIE DMA
USBDP data buses
and interrupts

3.3V
s )
t(
USBVCC Voltage INTERRUPT
Regulator

c
REGISTERS MEMORY

d u
USBGND

r o
e P
14.4 Register description
le t
s o
14.4.1 DMA address register (DMAR)

O b
DMAR
) - Reset value: undefined (xxh)
7 6

t ( s 5 4 3 2 1 0
DA15 DA14

u c DA13 DA12 DA11 DA10 DA9 DA8

R/W

o d
R/W R/W R/W R/W R/W R/W R/W

P r
Bits 7:0=DA[15:8] DMA address bits 15-8.
Software must write the start address of the DMA memory area whose most significant bits

te
are given by DA15-DA6. The remaining 6 address bits are set by hardware. See the

e
description of the IDR register and Figure 42.

o l
bs
14.4.2 Interrupt/DMA register (IDR)

O IDR Reset value: xxxx 0000 (x0h)

7 6 5 4 3 2 1 0
DA7 DA6 EP1 EP0 CNT3 CNT2 CNT1 CNT0
R/W R/W R/W R/W R/W R/W R/W R/W

Bits 7:6 = DA[7:6] DMA address bits 7-6.

Software must reset these bits. See the description of the DMAR register and Figure 42.
Bits 5:4 = EP[1:0] Endpoint number (read-only). These bits identify the endpoint which
required attention.
00: Endpoint 0
01: Endpoint 1
10: Endpoint 2

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 ST7260xx USB interface (USB)

When a CTR interrupt occurs (see register ISTR) the software should read the EP bits to
identify the endpoint which has sent or received a packet.
Bits 3:0 = CNT[3:0] Byte count (read only).
This field shows how many data bytes have been received during the last data reception.
Note: Not valid for data transmission.

Figure 42. DMA buffers

101111
Endpoint 2 TX
101000
100111

100000
Endpoint 2 RX

s )
011111
Endpoint 1 TX
c t(
011000
010111
Endpoint 1 RX
d u
010000
r o
001111
P
Endpoint 0 TX

e
001000
000111
le t
Endpoint 0 RX
DA15-6,000000 000000
s o
14.4.3 PID register (PIDR) O b
) -
PIDR
t ( s Reset value: xxxx 0000 (x0h)
7 6
u c 5 4 3 2 1 0

TP3
o d
TP2 0 0 0
RX_
RXD 0

PR
r R R R R
SEZ
R R R

te
Bits 7:6 = TP[3:2] Token PID bits 3 & 2.
e
o l USB token PIDs are encoded in four bits. TP[3:2] correspond to the variable token PID bits

b s
Note:
3 & 2.
PID bits 1 & 0 have a fixed value of 01.
O When a CTR interrupt occurs (see register ISTR) the software should read the TP3 and TP2
bits to retrieve the PID name of the token received.
The USB standard defines TP bits as:

Table 43. TP bits

TP3 TP2 PID name

0 0 OUT
1 0 IN
1 1 SETUP

Bits 5:3 Reserved. Forced by hardware to 0.

91/139
 USB interface (USB) ST7260xx

Bit 2 = RX_SEZ Received single-ended zero

This bit indicates the status of the RX_SEZ transceiver output.
0: No SE0 (single-ended zero) state
1: USB lines are in SE0 (single-ended zero) state
Bit 1 = RXD Received data
0: No K-state
1: USB lines are in K-state
This bit indicates the status of the RXD transceiver output (differential receiver output).
Note: If the environment is noisy, the RX_SEZ and RXD bits can be used to secure the
application. By interpreting the status, software can distinguish a valid End Suspend event
from a spurious wake-up due to noise on the external USB line. A valid End Suspend is
followed by a Resume or Reset sequence. A Resume is indicated by RXD=1, a Reset is
s )
indicated by RX_SEZ=1.
c t(
Bit 0 = Reserved. Forced by hardware to 0.
d u
14.4.4 Interrupt status register (ISTR)
r o
e P
ISTR

le t Reset value: 0000 0000 (00h)

so
7 6 5 4 3 2 1 0
SUSP DOVR CTR ERR IOVR ESUSP RESET SOF
R/W R/W R/W
O b
R/W R/W R/W R/W R/W

) -
When an interrupt occurs these bits are set by hardware. Software must read them to

s
determine the interrupt type and clear them after servicing.
(
Note:
ct
These bits cannot be set by software.

u
o d
Bit 7 = SUSP Suspend mode request.
This bit is set by hardware when a constant idle state is present on the bus line for more

P r
than 3 ms, indicating a suspend mode request from the USB bus. The suspend request
check is active immediately after each USB reset event and its disabled by hardware when

te
suspend mode is forced (FSUSP bit of CTLR register) until the end of resume sequence.
e
o l Bit 6 = DOVR DMA over/underrun.

b s This bit is set by hardware if the ST7 processor can’t answer a DMA request in time.
0: No over/underrun detected

O 1: Over/underrun detected
Bit 5 = CTR Correct Transfer. This bit is set by hardware when a correct transfer operation is
performed. The type of transfer can be determined by looking at bits TP3-TP2 in register
PIDR. The Endpoint on which the transfer was made is identified by bits EP1-EP0 in register
IDR.
0: No Correct Transfer detected
1: Correct Transfer detected
Note: A transfer where the device sent a NAK or STALL handshake is considered not correct (the
host only sends ACK handshakes). A transfer is considered correct if there are no errors in
the PID and CRC fields, if the DATA0/DATA1 PID is sent as expected, if there were no data
overruns, bit stuffing or framing errors.
Bit 4 = ERR Error.
This bit is set by hardware whenever one of the errors listed below has occurred:

92/139
ST7260xx USB interface (USB)

0: No error detected
1: Timeout, CRC, bit stuffing or nonstandard
framing error detected
Bit 3 = IOVR Interrupt overrun.
This bit is set when hardware tries to set ERR, or SOF before they have been cleared by
software.
0: No overrun detected
1: Overrun detected
Bit 2 = ESUSP End suspend mode.
This bit is set by hardware when, during suspend mode, activity is detected that wakes the
USB interface up from suspend mode.

s )
This interrupt is serviced by a specific vector, in order to wake up the ST7 from HALT mode.
0: No End Suspend detected
1: End Suspend detected
c t(
Bit 1 = RESET USB reset.
d u
r o
This bit is set by hardware when the USB reset sequence is detected on the bus.
0: No USB reset signal detected
1: USB reset signal detected
e P
Note:
le t
The DADDR, EP0RA, EP0RB, EP1RA, EP1RB, EP2RA and EP2RB registers are reset by a
USB reset.
s o
Bit 0 = SOF Start of frame.

O b
This bit is set by hardware when a low-speed SOF indication (keep-alive strobe) is seen on

0: No SOF signal detected

) -
the USB bus. It is also issued at the end of a resume sequence.

1: SOF signal detected

t ( s
Note:
c
To avoid spurious clearing of some bits, it is recommended to clear them using a load
u
o d
instruction where all bits which must not be altered are set, and all bits to be cleared are
reset. Avoid read-modify-write instructions like AND , XOR..

14.4.5 P r
Interrupt mask register (IMR)

e te
o l IMR Reset value: 0000 0000 (00h)

bs
7 6 5 4 3 2 1 0

O SUSPM
R/W
DOVRM
R/W
CTRM
R/W
ERRM
R/W
IOVRM
R/W
ESUSPM
R/W
RESETM
R/W
SOFM
R/W

Bits 7:0 = These bits are mask bits for all interrupt condition bits included in the ISTR.
Whenever one of the IMR bits is set, if the corresponding ISTR bit is set, and the I bit in the
CC register is cleared, an interrupt request is generated. For an explanation of each bit,
please refer to the corresponding bit description in ISTR.

93/139
USB interface (USB) ST7260xx

14.4.6 Control register (CTLR)

CTLR Reset value: 0000 0110 (06h)

7 6 5 4 3 2 1 0
0 0 0 0 RESUME PDWN FSUSP FRES
R/W R/W R/W R/W R/W R/W R/W R/W

Bits 7:4 = Reserved. Forced by hardware to 0.

Bit 3 = RESUME Resume.
This bit is set by software to wake-up the Host when the ST7 is in suspend mode.
0: Resume signal not forced
s )
t(
1: Resume signal forced on the USB bus.
Software should clear this bit after the appropriate delay.
u c
Bit 2 = PDWN Power down.
o d
external pull-up resistor and the transceiver.
P r
This bit is set by software to turn off the 3.3V on-chip voltage regulator that supplies the

0: Voltage regulator on
1: Voltage regulator off
t e
Note:
o le
After turning on the voltage regulator, software should allow at least 3 µs for stabilisation of
the power supply before using the USB interface.
b s
Bit 1 = FSUSP Force suspend mode.

- O
This bit is set by software to enter Suspend mode. The ST7 should also be halted allowing

0: Suspend mode inactive

( s )
at least 600 ns before issuing the HALT instruction.

1: Suspend mode active

c t
d u
When the hardware detects USB activity, it resets this bit (it can also be reset by software).

r o
Bit 0 = FRES Force reset.

e P
This bit is set by software to force a reset of the USB interface, just as if a RESET sequence
came from the USB.

l e t
0: Reset not forced
1: USB interface reset forced.
o
bs
The USB is held in RESET state until software clears this bit, at which point a “USB-RESET”
interrupt will be generated if enabled.
O

94/139
ST7260xx USB interface (USB)

14.4.7 Device address register (DADDR)

DADDR Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1 0
0 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
R/W R/W R/W R/W R/W R/W R/W R/W

Bit 7 = Reserved. Forced by hardware to 0.

Bits 6:0 = ADD[6:0] Device address, 7 bits.
Software must write into this register the address sent by the host during enumeration.

s )
t(
Note: This register is also reset when a USB reset is received from the USB bus or forced through
bit FRES in the CTLR register.

u c
14.4.8 Endpoint n register A (EPnRA)
o d
EPnRA P r
Reset value: 0000 xxxx (0xh)

t e
le
7 6 5 4 3 2 1 0

so
ST_ DTOG STAT STAT
TBC3 TBC2 TBC1 TBC0
OUT _TX _TX1 _TX0
R/W R/W R/W
O b
R/W R/W R/W R/W R/W

) -
These registers (EP0RA, EP1RA and EP2RA) are used for controlling data transmission.

s
They are also reset by the USB bus reset.
(
Note:
ct
Endpoint 2 and the EP2RA register are not available on some devices (see device feature

u
list and register map).

o d
Bit 7 = ST_OUT Status out.

P r
This bit is set by software to indicate that a status out packet is expected: in this case, all
nonzero OUT data transfers on the endpoint are STALLed instead of being ACKed. When

te
ST_OUT is reset, OUT transactions can have any number of bytes, as needed.

e
o l
bs
Bit 6 = DTOG_TX Data Toggle, for transmission transfers.
It contains the required value of the toggle bit (0=DATA0, 1=DATA1) for the next transmitted
O data packet. This bit is set by hardware at the reception of a SETUP PID. DTOG_TX toggles
only when the transmitter has received the ACK signal from the USB host. DTOG_TX and
also DTOG_RX (see EPnRB) are normally updated by hardware, at the receipt of a relevant
PID. They can be also written by software.

Bits 5:4 = STAT_TX[1:0] Status bits, for transmission transfers.

These bits contain the information about the endpoint status, which are listed below:

95/139
 USB interface (USB) ST7260xx

Table 44. STAT_TX bits

STAT_TX1 STAT_TX0 Meaning

DISABLED: transmission transfers cannot be

0 0
executed.
STALL: the endpoint is stalled and all transmission
0 1
requests result in a STALL handshake.
NAK: the endpoint is naked and all transmission
1 0
requests result in a NAK handshake.
1 1 VALID: this endpoint is enabled for transmission.

These bits are written by software. Hardware sets the STAT_TX bits to NAK when a correct
s )
t(
transfer has occurred (CTR=1) related to a IN or SETUP transaction addressed to this

c
endpoint; this allows the software to prepare the next set of data to be transmitted.

u
o d
Bits 3:0 = TBC[3:0] Transmit byte count for Endpoint n.

P r
Before transmission, after filling the transmit buffer, software must write in the TBC field the
transmit packet size expressed in bytes (in the range 0-8).
t e
Caution:
le
Any value outside the range 0-8 willinduce undesired effects (such as continuous data
transmission).
o
14.4.9 Endpoint n register B (EPnRB) b s
- O
EPnRB

( s ) Reset value: 0000 xxxx (0xh)

7 6

c t 5 4 3 2 1 0

du
DTOG STAT STAT
CTRL EA3 EA2 EA1 EA0
_RX _RX1 _RX0
R/W
r o R/W R/W R/W R/W R/W R/W R/W

e P
These registers (EP1RB and EP2RB) are used for controlling data reception on Endpoints 1
t
and 2. They are also reset by the USB bus reset.
e
Note:
s ol Endpoint 2 and the EP2RB register are not available on some devices (see device feature
list and register map).

O b Bit 7 = CTRL Control.

This bit should be 0.
Note: If this bit is 1, the Endpoint is a control endpoint. (Endpoint 0 is always a control Endpoint,
but it is possible to have more than one control Endpoint).

Bit 6 = DTOG_RX Data toggle, for reception transfers.

It contains the expected value of the toggle bit (0=DATA0, 1=DATA1) for the next data
packet. This bit is cleared by hardware in the first stage (Setup Stage) of a control transfer
(SETUP transactions start always with DATA0 PID). The receiver toggles DTOG_RX only if it
receives a correct data packet and the packet’s data PID matches the receiver sequence bit.
Bits 5:4 = STAT_RX [1:0] Status bits, for reception transfers.
These bits contain the information about the endpoint status, which are listed below:

96/139
 ST7260xx USB interface (USB)

Table 45. STAT_RX bits

STAT_RX1 STAT_RX0 Meaning

DISABLED: reception transfers cannot be

0 0
executed.
STALL: the endpoint is stalled and all reception
0 1
requests result in a STALL handshake.
NAK: the endpoint is naked and all reception
1 0
requests result in a NAK handshake.
1 1 VALID: this endpoint is enabled for reception.

These bits are written by software. Hardware sets the STAT_RX bits to NAK when a correct
s )
t(
transfer has occurred (CTR=1) related to an OUT or SETUP transaction addressed to this

a new transaction.
u c
endpoint, so the software has the time to elaborate the received data before acknowledging

Bits 3:0 = EA[3:0] Endpoint address.

o d
P r
Software must write in this field the 4-bit address used to identify the transactions directed to
this endpoint. Usually EP1RB contains “0001” and EP2RB contains “0010”.

t e
14.4.10 Endpoint 0 register B (EP0RB)
o le
EP0RB
b s Reset value: 1000 0000 (80h)

-O
7 6 5 4 3 2 1 0

(s)
DTOG STAT STAT
1 0 0 0 0
RX RX1 RX0
R/W R/W
c tR/W R/W R/W R/W R/W R/W

d u
This register is used for controlling data reception on Endpoint 0. It is also reset by the USB
bus reset.
r o
P
Bit 7 = Forced by hardware to 1.
e
l e t
Bits 6:4 = Refer to the EPnRB register for a description of these bits.

s o Bits 3:0 = Forced by hardware to 0.

b
O14.5 Programming considerations
The interaction between the USB interface and the application program is described below.
Apart from system reset, action is always initiated by the USB interface, driven by one of the
USB events associated with the Interrupt Status Register (ISTR) bits.

14.5.1 Initializing the registers

At system reset, the software must initialize all registers to enable the USB interface to
properly generate interrupts and DMA requests.

97/139
 USB interface (USB) ST7260xx

1. Initialize the DMAR, IDR, and IMR registers (choice of enabled interrupts, address of
DMA buffers). Refer the paragraph titled initializing the DMA Buffers.
2. Initialize the EP0RA and EP0RB registers to enable accesses to address 0 and
endpoint 0 to support USB enumeration. Refer to the paragraph titled Endpoint
Initialization.
3. When addresses are received through this channel, update the content of the DADDR.
4. If needed, write the endpoint numbers in the EA fields in the EP1RB and EP2RB
register.

14.5.2 Initializing DMA buffers

The DMA buffers are a contiguous zone of memory whose maximum size is 48 bytes. They

s
can be placed anywhere in the memory space to enable the reception of messages. The 10)
t(
most significant bits of the start of this memory area are specified by bits DA15-DA6 in
c
d
Each buffer is filled starting from the bottom (last 3 address bits=000) up.u
registers DMAR and IDR, the remaining bits are 0. The memory map is shown in Figure 42.

r o
14.5.3 Endpoint initialization
e P
To be ready to receive:
le t
o
Set STAT_RX to VALID (11b) in EP0RB to enable reception.
s
To be ready to transmit:
1.
O b
Write the data in the DMA transmit buffer.
2.
) -
In register EPnRA, specify the number of bytes to be transmitted in the TBC field
3.
( s
Enable the endpoint by setting the STAT_TX bits to VALID (11b) in EPnRA.
t
Note:
c
Once transmission and/or reception are enabled, registers EPnRA and/or EPnRB
u
(respectively) must not be modified by software, as the hardware can change their value on
the fly.
o d
P r
When the operation is completed, they can be accessed again to enable a new operation.

14.5.4 t e
Interrupt handling
e
o l
b s Start of frame (SOF)
The interrupt service routine may monitor the SOF events for a 1 ms synchronization event
O to the USB bus. This interrupt is generated at the end of a resume sequence and can also
be used to detect this event.

USB reset (RESET)

When this event occurs, the DADDR register is reset, and communication is disabled in all
endpoint registers (the USB interface will not respond to any packet). Software is
responsible for reenabling endpoint 0 within 10 ms of the end of reset. To do this, set the
STAT_RX bits in the EP0RB register to VALID.

Suspend (SUSP)
The CPU is warned about the lack of bus activity for more than 3 ms, which is a suspend
request. The software should set the USB interface to suspend mode and execute an ST7
HALT instruction to meet the USB-specified power constraints.

98/139
 ST7260xx USB interface (USB)

End suspend (ESUSP)

The CPU is alerted by activity on the USB, which causes an ESUSP interrupt. The ST7
automatically terminates HALT mode.

Correct transfer (CTR)

1. When this event occurs, the hardware automatically sets the STAT_TX or STAT_RX to
NAK.
Note: Every valid endpoint is NAKed until software clears the CTR bit in the ISTR register,
independently of the endpoint number addressed by the transfer which generated the CTR
interrupt.
Note: If the event triggering the CTR interrupt is a SETUP transaction, both STAT_TX and
s )
STAT_RX are set to NAK.
2.
c t(
Read the PIDR to obtain the token and the IDR to get the endpoint number related to
the last transfer.
d u
Note:
r o
When a CTR interrupt occurs, the TP3-TP2 bits in the PIDR register and EP1-EP0 bits in

3. Clear the CTR bit in the ISTR register.

e P
the IDR register stay unchanged until the CTR bit in the ISTR register is cleared.

le t
Table 46.
Address
USB register map and reset values

s o
(Hex.)
Register
name
7 6 5

O b 4 3 2 1 0

25
PIDR TP3 TP2
) - 0 0 0 RX_SEZ RXD 0
Reset Value x x

t ( s 0 0 0 0 0 0

26
DMAR
Reset Value
DA15
x
u c
DA14
x
DA13
x
DA12
x
DA11
x
DA10
x
DA9
x
DA8
x
IDR
o d
DA7 DA6 EP1 EP0 CNT3 CNT2 CNT1 CNT0
27
Reset Value
P r x x x x 0 0 0 0

28
t
ISTR
e
Reset Value
e
SUSP
0
DOVR
0
CTR
0
ERR
0
IOVR
0
ESUSP
0
RESET
0
SOF
0

o l IMR SUSPM DOVRM CTRM ERRM IOVRM

ESUSP RESET
SOFM

b s
29
Reset Value 0 0 0 0 0
M
0
M
0
0

O 2A
CTLR 0 0 0 0
RESUM
E
PDWN FSUSP FRES
Reset Value 0 0 0 0 1 1 0
0
DADDR 0 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
2B
Reset Value 0 0 0 0 0 0 0 0
EP0RA ST_OUT DTOG_TX STAT_TX1 STAT_TX0 TBC3 TBC2 TBC1 TBC0
2C
Reset Value 0 0 0 0 x x x x
STAT_RX STAT_RX
EP0RB 1 DTOG_RX 0 0 0 0
2D 1 0
Reset Value 1 0 0 0 0 0
0 0

99/139
 USB interface (USB) ST7260xx

Table 46. USB register map and reset values (continued)

Address Register
7 6 5 4 3 2 1 0
(Hex.) name

EP1RA ST_OUT DTOG_TX STAT_TX1 STAT_TX0 TBC3 TBC2 TBC1 TBC0

2E
Reset Value 0 0 0 0 x x x x
STAT_RX STAT_RX
EP1RB CTRL DTOG_RX EA3 EA2 EA1 EA0
2F 1 0
Reset Value 0 0 x x x x
0 0
EP2RA ST_OUT DTOG_TX STAT_TX1 STAT_TX0 TBC3 TBC2 TBC1 TBC0
30
Reset Value 0 0 0 0 x x x x
STAT_RX STAT_RX
s )
31
EP2RB
Reset Value
CTRL
0
DTOG_RX
0
1 0
EA3
x
EA2
x
EA1
x
c t( EA0
x
0 0

d u
r o
e P
le t
s o
O b
) -
t ( s
u c
o d
P r
e t e
o l
b s
O

100/139
 ST7260xx Instruction set

15 Instruction set

15.1 ST7 addressing modes

The ST7 Core features 17 different addressing modes which can be classified in 7 main
groups:

Table 47. Addressing mode groups

Addressing mode Example

Inherent nop

s )
t(
Immediate ld A,#$55
Direct ld A,$55

u c
Indexed ld A,($55,X)

o d
Indirect
Relative
ld A,([$55],X)
jrne loop
P r
Bit operation bset
t e
byte,#5

o le
The ST7 Instruction set is designed to minimize the number of bytes required per

called long and short: b s

instruction: To do so, most of the addressing modes may be subdivided in two sub-modes

●
- O
Long addressing mode is more powerful because it can use the full 64 Kbyte address

●
( )
space, however it uses more bytes and more CPU cycles.

s
Short addressing mode is less powerful because it can generally only access page

c t
zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All

d u
memory to memory instructions use short addressing modes only (CLR, CPL, NEG,
BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)

r o
The ST7 Assembler optimizes the use of long and short addressing modes.

e P
Table 48.
l e t
ST7 addressing mode overview

s o Mode Syntax Destination/ Pointer Pointer Length

O b
Inherent nop
source address size
+0
(bytes)

Immediate ld A,#$55 +1
Short Direct ld A,$10 00..FF +1
Long Direct ld A,$1000 0000..FFFF +2
+ 0 (with X register)
No Offset Direct Indexed ld A,(X) 00..FF
+ 1 (with Y register)
Short Direct Indexed ld A,($10,X) 00..1FE +1
Long Direct Indexed ld A,($1000,X) 0000..FFFF +2
Short Indirect ld A,[$10] 00..FF 00..FF byte +2
Long Indirect ld A,[$10.w] 0000..FFFF 00..FF word +2

101/139
 Instruction set ST7260xx

Table 48. ST7 addressing mode overview (continued)

Mode Syntax Destination/ Pointer Pointer Length

source address size (bytes)
Short Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte +2
Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word +2
Relative Direct jrne loop PC-128/PC+127(1) +1
(1)
Relative Indirect jrne [$10] PC-128/PC+127 00..FF byte +2
Bit Direct bset $10,#7 00..FF +1
Bit Indirect bset [$10],#7 00..FF 00..FF byte +2
Bit Direct Relative btjt $10,#7,skip 00..FF +2
s )
Bit Indirect Relative btjt [$10],#7,skip 00..FF 00..FF byte +3
c t(
u
1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.

d
15.1.1 Inherent
r o
P
All Inherent instructions consist of a single byte. The opcode fully specifies all the required
e
information for the CPU to process the operation.

le t
Table 49. Inherent instructions
s o
Instruction
b Function

NOP
-O No operation

(s)
TRAP S/W Interrupt

ct
WFI Wait For Interrupt (Low Power Mode)

du
HALT Halt Oscillator (Lowest Power Mode)
RET

r o Sub-routine Return
IRET
P Interrupt Sub-routine Return

ete
SIM Set Interrupt Mask

ol
RIM Reset Interrupt Mask

b s SCF
RCF
Set Carry Flag
Reset Carry Flag

O RSP Reset Stack Pointer

LD Load
CLR Clear
PUSH/POP Push/Pop to/from the stack
INC/DEC Increment/Decrement
TNZ Test Negative or Zero
CPL, NEG 1 or 2 Complement
MUL Byte Multiplication

102/139
 ST7260xx Instruction set

Table 49. Inherent instructions

Instruction Function

SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations

SWAP Swap Nibbles

15.1.2 Immediate
Immediate instructions have two bytes, the first byte contains the opcode, the second byte
contains the operand value.

Table 50. Immediate instructions

s )
t(
Instruction Function

LD Load
u c
CP Compare
o d
BCP Bit Compare
P r
AND, OR, XOR
e
Logical Operations

t
le
ADC, ADD, SUB, SBC Arithmetic Operations

15.1.3 Direct s o
O b
In Direct instructions, the operands are referenced by their memory address.

) -
The direct addressing mode consists of two sub-modes:

Direct (short)
t ( s
u c
The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF

o
addressing space. d
P r
Direct (long)

e t e
The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after

o l the opcode.

b s
15.1.4 Indexed (no offset, short, long)
O In this mode, the operand is referenced by its memory address, which is defined by the
unsigned addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three sub-modes:

Indexed (no offset)

There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space.

Indexed (short)
The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE
addressing space.

103/139
 Instruction set ST7260xx

Indexed (long)
The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the
opcode.

15.1.5 Indirect (short, long)

The required data byte to do the operation is found by its memory address, located in
memory (pointer).
The pointer address follows the opcode. The indirect addressing mode consists of two sub-
modes:

Indirect (short)
s )
space, and requires 1 byte after the opcode.
c t(
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing

d u
Indirect (long)
r o
space, and requires 1 byte after the opcode.
e P
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing

le t
15.1.6 Indirect indexed (short, long)
s o
O b
This is a combination of indirect and short indexed addressing modes. The operand is
referenced by its memory address, which is defined by the unsigned addition of an index

the opcode.
) -
register value (X or Y) with a pointer value located in memory. The pointer address follows

t ( s
The indirect indexed addressing mode consists of two sub-modes:

u c
Indirect indexed (short)

o d
P r
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing
space, and requires 1 byte after the opcode.

e t e
Indirect indexed (long)

o l The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing

b s space, and requires 1 byte after the opcode.

104/139
ST7260xx Instruction set

Table 51. Instructions supporting direct, indexed, indirect and indirect indexed
addressing modes
Instructions Function

LD Load
CP Compare
AND, OR, XOR Logical Operations
Long and short instructions
Arithmetic Addition/subtraction
ADC, ADD, SUB, SBC
operations
BCP Bit Compare
CLR Clear
s )
INC, DEC Increment/Decrement
c t(
TNZ
u
Test Negative or Zero

d
CPL, NEG
o
1 or 2 Complement
r
Short instructions only BSET, BRES

e P
Bit Operations
BTJT, BTJF

e t Bit Test and Jump Operations

ol
SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations

bs
SWAP Swap Nibbles
CALL, JP Call or Jump subroutine

- O
15.1.7 Relative mode (direct, indirect)
( s )
t
This addressing mode is used to modify the PC register value by adding an 8-bit signed
c
offset to it.

d u
Table 52.
r o
Available relative direct/indirect instructions

e P Instructions Function

let
JRxx Conditional Jump
CALLR Call Relative

so
Ob
The relative addressing mode consists of two sub-modes:

Relative (direct)
The offset follows the opcode.

Relative (indirect)
The offset is defined in memory, of which the address follows the opcode.

15.2 Instruction groups

The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions
may be subdivided into 13 main groups as illustrated in the following table:

105/139
 Instruction set ST7260xx

Table 53. Instruction groups

Group Instruction

Load and Transfer LD CLR

Stack operation PUSH POP RSP
Increment/Decrement INC DEC
Compare and Tests CP TNZ BCP
Logical operations AND OR XOR CPL NEG
Bit Operation BSET BRES
Conditional Bit Test and Branch BTJT BTJF

s )
Arithmetic operations ADC ADD SUB SBC MUL
t(
uc
Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA

od
Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET
Conditional Branch
Interruption management
JRxx
TRAP WFI HALT P
IRET
r
Condition Code Flag modification SIM RIM SCF
e t e
RCF

o l
Using a pre-byte

b s
The instructions are described with one to four bytes.

- O
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three

they precede.
(s )
different prebyte opcodes are defined. These prebytes modify the meaning of the instruction

c t
The whole instruction becomes:
PC-2
d u
End of previous instruction
PC-1 r o Prebyte
PC
e P Opcode

l e t
PC+1 Additional word (0 to 2) according to the number of bytes required to compute

s o the effective address

O b These prebytes enable instruction in Y as well as indirect addressing modes to be

implemented. They precede the opcode of the instruction in X or the instruction using direct
addressing mode. The prebytes are:
PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent
addressing mode by a Y one.
PIX 92 Replace an instruction using direct, direct bit, or direct relative addressing
mode to an instruction using the corresponding indirect addressing mode.
It also changes an instruction using X indexed addressing mode to an
instruction using indirect X indexed addressing mode.
PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.

106/139
 ST7260xx Instruction set

Table 54. Instruction set

Mnemo Description Function/Example Dst Src H I N Z C

ADC Add with Carry A=A+M+C A M H N Z C

ADD Addition A=A+M A M H N Z C
AND Logical And A=A.M A M N Z
BCP Bit compare A, Memory tst (A . M) A M N Z
BRES Bit Reset bres Byte, #3 M
BSET Bit Set bset Byte, #3 M
BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M

( s ) C

ct
BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C
CALL Call subroutine
CALLR Call subroutine relative
d u
o
Pr
CLR Clear reg, M 0 1
CP Arithmetic Compare tst(Reg - M) reg M N Z C
CPL One Complement A = FFH-A reg, M
e t e N Z 1
DEC Decrement dec Y
o
reg, Ml N Z
s
Ob
HALT Halt 0
IRET Interrupt routine return Pop CC, A, X, PC H I N Z C
INC Increment inc X
) - reg, M N Z
JP Absolute Jump
t (s
jp [TBL.w]

c
JRA
JRT
Jump relative always
Jump relative
d u
JRF Never jump
r o jrf *
JRIH
e P
Jump if ext. interrupt = 1
JRIL
l e t
Jump if ext. interrupt = 0
JRH
s o Jump if H = 1 H=1?

O b
JRNH
JRM
Jump if H = 0
Jump if I = 1
H=0?
I=1?
JRNM Jump if I = 0 I=0?
JRMI Jump if N = 1 (minus) N=1?
JRPL Jump if N = 0 (plus) N=0?
JREQ Jump if Z = 1 (equal) Z=1?
JRNE Jump if Z = 0 (not equal) Z=0?
JRC Jump if C = 1 C=1?
JRNC Jump if C = 0 C=0?
JRULT Jump if C = 1 Unsigned <
JRUGE Jump if C = 0 Jmp if unsigned >=

107/139
 Instruction set ST7260xx

Table 54. Instruction set (continued)

Mnemo Description Function/Example Dst Src H I N Z C

JRUGT Jump if (C + Z = 0) Unsigned >

JRULE Jump if (C + Z = 1) Unsigned <=
LD Load dst <= src reg, M M, reg N Z
MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0
NEG Negate (2's compl) neg $10 reg, M N Z C
NOP No Operation
OR OR operation A=A+M A M N Z

s )
t(
POP Pop from the Stack pop reg reg M

uc
pop CC CC M H I N Z C
PUSH Push onto the Stack push Y M reg, CC

o d
RCF
RET
Reset carry flag
Subroutine Return
C=0

P r 0

RIM Enable Interrupts I=0

et e 0
RLC Rotate left true C C <= Dst <= C
o
reg, Ml N Z C

s
Ob
RRC Rotate right true C C => Dst => C reg, M N Z C
RSP Reset Stack Pointer S = Max allowed
SBC Subtract with Carry A=A-M-C

( s )- A M N Z C
SCF
SIM
Set carry flag
Disable Interrupts
C=1

c
I=1t 1
1

SLA Shift left Arithmetic

d u
C <= Dst <= 0 reg, M N Z C
o
Pr
SLL Shift left Logic C <= Dst <= 0 reg, M N Z C
SRL Shift right Logic 0 => Dst => C reg, M 0 Z C
SRA
e t e
Shift right Arithmetic Dst7 => Dst => C reg, M N Z C
SUB
s ol Subtraction A=A-M A M N Z C

O b
SWAP SWAP nibbles
Dst[7..4] <=>
Dst[3..0]
reg, M N Z

TNZ Test for Neg & Zero tnz lbl1 N Z

TRAP S/W trap S/W interrupt 1
WFI Wait for Interrupt 0
XOR Exclusive OR A = A XOR M A M N Z

108/139
 ST7260xx Electrical characteristics

16 Electrical characteristics

16.1 Parameter conditions

Unless otherwise specified, all voltages are referred to VSS.

16.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA=25°C and TA=TAmax (given by the
selected temperature range).
s )
t(
Data based on characterization results, design simulation and/or technology characteristics
c
d u
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the

o
mean value plus or minus three times the standard deviation (mean±3s).
r
16.1.2 Typical values
e P
le t
Unless otherwise specified, typical data are based on TA=25°C, VDD=5V. They are given
only as design guidelines and are not tested.
s o
16.1.3 Typical curves
O b
-
Unless otherwise specified, all typical curves are given only as design guidelines and are
)
not tested.

t ( s
16.1.4 Loading capacitor
u c
o d
The loading conditions used for pin parameter measurement are shown in Figure 43.

P r
Figure 43. Pin loading conditions

e te
o l ST7 PIN

b s CL

O
16.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 44.

109/139
 Electrical characteristics ST7260xx

Figure 44. Pin input voltage

ST7 PIN

VIN

s )
ct(
d u
r o
e P
le t
s o
O b
) -
t ( s
u c
o d
P r
e t e
o l
b s
O

110/139
 ST7260xx Electrical characteristics

16.2 Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.

Table 55. Voltage characteristics

Symbol Ratings Maximum value Unit

VDD - VSS Supply voltage 6.0

Input voltage on true open drain pins VSS-0.3 to 6.0 V
VIN(1) & (2)
s )
t(
Input voltage on any other pin VSS-0.3 to VDD+0.3

VESD(HBM)
Electro-static discharge voltage (Human Body
c
See “Absolute maximum

u
ratings (electrical sensitivity)”
Model)

o don page 119.

P r
1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional
internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a

e
corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up
way to VDD or VSS according to their reset configuration.

le t
or pull-down resistor (typical: 4.7kΩ for RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same

Table 56. Current characteristics

s o
Symbol

O b
Ratings

Total current into VDD power lines (source) (1)

Maximum value Unit

IVDD
IVSS
) -
Total current out of VSS ground lines (sink) (1)
80
80

t ( s
Output current sunk by any standard I/O and

u c
control pin
25
IIO

o d Output current sunk by any high sink I/O pin 50

Pr
Output current source by any I/Os and control pin - 25
mA
Injected current on VPP pin ±5

e t e Injected current on RESET pin ±5

ol
IINJ(PIN) (2)
Injected current on OSCIN and OSCOUT pins ±5

b s Injected current on any other pin (3) & (4) ±5

O ΣIINJ(PIN) (2)
Total injected current (sum of all I/O and control
pins) (3)
± 20

IINJ(PIN) (2) Negative injected current to PB0(10mA) pin - 80 µA

1. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads,
there is no positive injection current, and the corresponding VIN maximum must always be respected
3. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
4. True open drain I/O port pins do not accept positive injection.

111/139
Electrical characteristics ST7260xx

Table 57. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range -65 to +150 °C

TJ Maximum junction temperature: See Section 17.1.1 on page 130 for TJmax

16.3 Operating conditions

16.3.1 General operating conditions

Table 58. General operating condition

s )
t(
uc
Symbol Parameter Conditions Min Typ Max Unit

od
VDD Operating supply voltage fCPU = 8 MHz 4 5 5.5

Pr
VDDA Analog supply voltage VDD VDD V
VSSA Analog supply voltage VSS VSS

t
fOSC = 24 MHze 8
fCPU Operating frequency

o le
fOSC = 12 MHz 4
MHz

TA Ambient temperature range

b s 0 70 °C

O
Figure 45. fCPU maximum operating frequency versus VDD supply voltage
-
( s )
t
fCPU [MHz]

u c
o d 8
FUNCTIONALITY

P r GUARANTEED
FROM 4 TO 5.5 V

e t e 4

l
FUNCTIONALITY
NOT GUARANTEED 2

o IN THIS AREA

bs
0
2.5 3.0 3.5 4 4.5 5 5.5 SUPPLY VOLTAGE [V]

112/139
 ST7260xx Electrical characteristics

16.3.2 Operating conditions with low voltage detector (LVD)

Subject to general operating conditions for VDD, fCPU, and TA. Refer to Figure 9 on page 26.

Table 59. Operating conditions at power-up/power-down

Symbol Parameter Conditions Min Typ Max Unit

Low Voltage Reset Threshold VDD Max. Variation

VIT+ 3.4 3.7 4.0 V
(VDD rising) 50 V/ms
Low Voltage Reset Threshold VDD Max. Variation
VIT- 3.2 3.5 3.8 V
(VDD falling) 50 V/ms
Vhyst Hysteresis (VIT+ - VIT-) (1) 100 175 220 mV

( s ) V/m
VtPOR VDD rise time rate (2) 0.5

c t 50
s
1. Guaranteed by characterization - not tested in production

d u
in production.
r o
2. The VDD rise time rate condition is needed to insure a correct device power-on and LVD reset. Not tested

e P
16.4 Supply current characteristics
o l et
The following current consumption specified for the ST7 functional operating modes over

b s
temperature range does not take into account the clock source current consumption. To get

for which the clock is stopped).

- O
the total device consumption, the two current values must be added (except for Halt mode

Table 60. Supply current consumption

( s )
Symbol Parameter

u ct Conditions Typ Max Unit

ΔIDD(ΔTa)
o d
Supply current variation vs.
Constant VDD and fCPU 10 (1) %

r
temperature

P fCPU = 4 MHz 7.5 9 (2)(1)

e t e
CPU RUN mode I/Os in input mode
fCPU = 8 MHz 10.5 13 (2)
mA

o lCPU WAIT mode

fCPU = 4 MHz 6 8 (1)
mA

b sIDD
CPU HALT mode (3)
fCPU = 8 MHz 8.5 11 (2)
40 (1) μA
O USB Suspend mode (4)
LVD disabled
LVD disabled
25
100 120
μA
LVD enabled 230
1. Not tested in production, guaranteed by characterization.
2. Oscillator and watchdog running. All others peripherals disabled.
3. USB Transceiver is powered down.
4. CPU in Halt mode. Current consumption of external pull-up (1.5 Kohms to USBVCC) and pull-down (15 Kohms to
VSSA) not included.

113/139
 Electrical characteristics ST7260xx

Figure 46. Typ. IDD in RUN at 4 and 8 Figure 47. Typ. IDD in WAIT at 4 and 8
MHz fCPU MHz fCPU

Idd Run (mA) at fcpu=4 and 8MHz Idd WFI (mA) at fcpu=4 and 8MHz

12 10

10
8

Idd WFI (mA)

Idd Run (mA)

6
6

4
4

8MHz
8MHz 2
2
4MHz

)
4MHz
0
4 4.2 4.4 4.6 4.8
Vdd (V)
5 5.2 5.4
0
4 4.2 4.4 4.6 4.8
Vdd (V)
5

t( s
5.2 5.4

u c
o d
16.5 Clock and timing characteristics
Subject to general operating conditions for VDD, fCPU, and TA. P r
t e
16.5.1 General timings
o le
Table 61. CPU timings
b s
-O
Symbol Parameter Conditions Min Typ (1) Max Unit

(s)
2 3 12 tCPU
tc(INST) Instruction cycle time fCPU=8 MHz

ct
250 375 1500 ns

du
Interrupt reaction time (2) 10 22 tCPU
tv(IT) fCPU=8 MHz
tv(IT) = Δtc(INST) + 10 tCPU

ro
1.25 2.75 μs

e P
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. Δtc(INST) is the number of tCPU cycles

l e t needed to finish the current instruction execution.

16.5.2
s o Control timing characteristics

O b
Table 62. Control timings
Value
Symbol Parameter Conditions Unit
Min Typ Max

fOSC Oscillator frequency 24 MHz

fCPU Operating frequency 8 MHz
External RESET
tRL 2520 ns
input pulse width
tPORL Internal power reset duration 4096 tCPU
Watchdog or low voltage reset
tDOGL 200 300 ns
output pulse width

114/139
 ST7260xx Electrical characteristics

Table 62. Control timings (continued)

Value
Symbol Parameter Conditions Unit
Min Typ Max

49152 3145728 tCPU

tDOG Watchdog time-out
fCPU = 8 MHz 6.144 393.216 ms
Crystal oscillator
tOXOV 20(1) 30 40(1) ms
start-up time
tDDR Power up rise time from VDD = 0 to 4 V 100(1) ms
1. Not tested in production, guaranteed by characterization.

s )
c t(
d u
r o
e P
le t
s o
O b
) -
t ( s
u c
o d
P r
e t e
o l
b s
O

115/139
 Electrical characteristics ST7260xx

16.5.3 External clock source

Table 63. External clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

OSCIN input pin high level

VOSCINH 0.7xVDD VDD
voltage
V
OSCIN input pin low level
VOSCINL VSS 0.3xVDD
voltage
see Figure 48
tw(OSCINH)
OSCIN high or low time (1) 15
tw(OSCINL)
tr(OSCIN)
OSCIN rise or fall time(1) 15
( s )
ns

tf(OSCIN)
OSCx Input leakage
c t
IL
current
VSS≤VIN≤VDD

d u ±1 μA

r
1. Data based on design simulation and/or technology characteristics, not tested in production.
o
Figure 48. Typical application with an external clock source
e P
VOSCINH
90%

o l et
10%

b s
O
VOSCINL

tr(OSCIN)
) -
tf(OSCIN) tw(OSCINH) tw(OSCINL)

( s
ct
du
OSCOUT
Not connected internally

r o fOSC

e P
EXTERNAL
CLOCK SOURCE
IL

t
OSCIN

ol e ST72XXX

b s Figure 49. Typical application with a crystal resonator

O i2

fOSC
CL1 OSCIN

RESONATOR RF
CL2
OSCOUT
ST72XXX

116/139
 ST7260xx Electrical characteristics

16.6 Memory characteristics

Subject to general operating conditions for fCPU, and TA unless otherwise specified.

16.6.1 RAM and hardware registers

Table 64. RAM and hardware registers

Symbol Parameter Conditions Min Typ Max Unit

HALT mode (or

VRM Data retention mode (1) 2.0 V
RESET)
1. Guaranteed by design. Not tested in production.

s )
16.6.2 Flash memory
c t(
Operating Conditions: fCPU = 8 MHz.
d u
Table 65. Dual voltage Flash memory (1)
r o
Symbol Parameter Conditions
e Min P Typ Max Unit

e t
ol
Read mode 8
fCPU Operating Frequency MHz

b s Write / Erase
mode, TA=25°C
8

VPP Programming Voltage

O 4.0V ≤VDD ≤ 5.5V 11.4 12.6 V
IPP VPP Current

( s )- Write / Erase 30 mA

t
tVPP Internal VPP Stabilization Time 10 µs
tRET Data Retention
u c TA ≤ 55°C 40 years
NRW

o d
Write Erase Cycles TA=25°C 100 cycles

P r
1. Refer to the Flash Programming Reference Manual for the typical HDFlash programming and erase timing
values.

t e
Figure 50. Two typical applications with VPP pin(b)

e
o l
b s VPP
PROGRAMMING
TOOL
VPP

O
10kΩ
ST72XXX ST72XXX

b. When the ICP mode is not required by the application, VPP pin must be tied to VSS.

117/139
Electrical characteristics ST7260xx

16.7 EMC characteristics

Susceptibility and emission tests are performed on a sample basis during product
characterization.

16.7.1 Functional EMS (electromagnetic susceptibility)

Based on a simple running application on the product (toggling 2 LEDs through I/O ports),
the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
● ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 1000-4-2
standard.
s )
●
t(
FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and

c
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test
conforms with the IEC 1000-4-4 standard.
d u
r o
A device reset allows normal operations to be resumed. The test results are given in the

P
table below based on the EMS levels and classes defined in application note AN1709.

e
16.7.2 Designing hardened software to avoid noise problems
le t
o
EMC characterization and optimization are performed at component level with a typical
s
b
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
O
) -
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.

t ( s
c
Software recommendations:
u
d
The software flowchart must include the management of runaway conditions such as:

o
●
●
P r
Corrupted program counter
Unexpected reset

e
let
● Critical data corruption (control registers...)

so
Prequalification trials:

Ob
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behaviour is detected, the software can be
hardened to prevent unrecoverable errors occurring (see application note AN1015).

118/139
ST7260xx Electrical characteristics

Table 66. EMS data

Symbol Parameter Conditions Level/class

VDD=5 V, TA=+25 °C,

Voltage limits to be applied on any I/O pin
VFESD fOSC=8 MHz, 4B
to induce a functional disturbance
conforms to IEC 1000-4-2
Fast transient voltage burst limits to be VDD=5 V, TA=+25 °C,
VFFTB applied through 100pF on VDD and VDD fOSC=8 MHz, 4A
pins to induce a functional disturbance conforms to IEC 1000-4-4

16.7.3 Electro magnetic interference (EMI)

Based on a simple application running on the product (toggling 2 LEDs through the I/O
s )
ports), the product is monitored in terms of emission. This emission test is in line with the
norm SAE J 1752/3 which specifies the board and the loading of each pin.
c t(
d u
Table 67. EMC data
r o
P
Monitored
e
Max vs.
[fOSC/fCPU]

t
Symbol Parameter Conditions Unit
frequency band

ol e 16/8 MHz

bs
0.1 MHz to 30 MHz 36
VDD=5V, TA=+25°C,
conforming to SAE J 1752/3 30 MHz to 130 MHz 39 dBμV
SEMI Peak level (1)

- O
Note: Refer to Application Note AN1709 130 MHz to 1 GHz 26

( )
for data on other package types.

s SAE EMI Level 3.5 -

c t
1. Data based on characterization results, not tested in production.

16.7.4
d u
Absolute maximum ratings (electrical sensitivity)

r o
Based on two different tests (ESD and LU) using specific measurement methods, the
P
product is stressed in order to determine its performance in terms of electrical sensitivity.
e
16.7.5
l e t
Electrostatic discharge (ESD)
o
bs
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
O depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test
conforms to the AEC-Q100-002 standard.

Table 68. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Class Unit
value(1)

Electrostatic discharge voltage TA = +25°C, conforming

VESD(HBM) H1C 2000 V
(Human body model) to AEC-Q100-002
1. Data based on characterization results, not tested in production

119/139
 Electrical characteristics ST7260xx

Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance.
● A supply overvoltage (applied to each power supply pin) and
● A current injection (applied to each input, output and configurable I/O pin) are
performed on each sample.
This test conforms to the EIA/JESD 78 IC latch-up standard.

Table 69. Electrical sensitivities

Symbol Parameter Conditions Class

TA = +25 °C conforming to JESD 78

s )
t(
LU Static latch-up class II level A

u c
o d
P r
t e
o le
b s
- O
( s )
c t
d u
r o
e P
l e t
s o
O b

120/139
 ST7260xx Electrical characteristics

16.8 I/O port pin characteristics

16.8.1 General characteristics

Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.

Table 70. I/O port characteristics

Symbol Parameter Conditions Min Typ Max Unit

VIL Input low level voltage 0.3xVDD

V
VIH Input high level voltage 0.7xVDD
True open drain I/O
6.0
s )
t(
VIN Input voltage pins VSS V
Other I/O pins
u c VDD

Vhys
Schmitt trigger voltage

o400 d mV

IL
hysteresis
Input leakage current VSS≤VIN≤VDD
P r ±1
Static current
t e μA
IS consumption induced by
each floating input pin (1)
Floating input mode

o le 400

RPU
Weak pull-up equivalent
resistor (2)
VIN=VSS
b s
VDD=5 V 50 90 120 kΩ

CIO I/O pin capacitance

- O 5 pF

tf(IO)out
( s
Output high to low level ) 25
fall time

c t CL=50 pF
Between 10% and ns
tr(IO)out
d
rise time u
Output low to high level 90% 25

o
Pr
External interrupt pulse
tw(IT)in 1 tCPU
time (3)

e t e
1. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of

ol
the I/O for example or an external pull-up or pull-down resistor (see Figure 51). Static peak current value
taken at a fixed VIN value, based on design simulation and technology characteristics, not tested in
production. This value depends on VDD and temperature values.

b s 2. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current
characteristics described in Figure 52).

O 3. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured
as an external interrupt source.

Figure 51. Two typical applications with unused I/O pin

VDD ST72XXX
10kΩ
UNUSED I/O PORT
10kΩ
UNUSED I/O PORT

ST72XXX

121/139
 Electrical characteristics ST7260xx

Figure 52. Typ. IPU vs. VDD

Pull-up current (µA)
90

80

70

Pull-up current (µA)

60

50

40

30

20

10

s )
0
4 4.2 4.4 4.6 4.8 5 5.2 5.4

ct(
u
Vdd (V)

o d
Figure 53. Typ. RPU vs. VDD
Rpu (KOhm) P r
140

t e
120

o le
100

b s
O
Rpu (KOhm)

80

60
) -
40
t ( s
c
du
20

P ro 0
4 4.2 4.4 4.6 4.8
Vdd (V)
5 5.2 5.4

e t e
o l
b s
O

122/139
ST7260xx Electrical characteristics

16.8.2 Output driving current

Subject to general operating condition for VDD, fCPU, and TA unless otherwise specified.

Table 71. Output current characteristics

Symbol Parameter Conditions Min Max Unit

Output low level voltage for a standard

I/O pin when up to 8 pins are sunk at the
IIO=+1.6 mA 0.4
same time, Port A0, Port A(3:7), Port
C(0:2)
Output low level voltage for a high sink
VOL (1)
I/O pin when up to 4 pins are sunk at the IIO=+10 mA 1.3
)

VDD=5 V
same time, Port B(0:7)

t( s V
Output low level voltage for a very high
sink I/O pin when up to 2 pins are sunk at IIO=+25 mA
u c 1.5
the same time, Port A1, Port A2
o d
VOH (2)
Output high level voltage for an I/O pin
when up to 8 pins are sourced at same
IIO=-10 mA
P r VDD-1.3

time

e t e
IIO=-1.6 mA VDD-0.8

ports and control pins) must not exceed IVSS.

o l
1. The IIO current sunk must always respect the absolute maximum rating specified in Section 16.2 and the sum of IIO (I/O

2.
s
The IIO current sourced must always respect the absolute maximum rating specified in Section 16.2 and the sum of IIO (I/O

b
ports and control pins) must not exceed IVDD. True open drain I/O pins does not have VOH.

Figure 54. VOL standard VDD=5 V

- O Figure 55. VOL high sink VDD=5 V

(s)
Vol_2mA (mV) at Vdd=5V Vol_10mA (V) at Vdd=5V
250 1.6

c t 1.4

u
200

d
1.2

o
Vol_2mA (mV)

Vol_10mA (V)

150

r
1

P
100

e
0.8

t
0.6

e
50

o l 0
0.4

0.2

bs
1 1.5 2 2.5 3 3.5 4 5 7 9 11 13 15 17 19
Iio (mA) Iio (mA)

O Figure 56. VOL very high sink VDD=5 V

Vol_25mA (V) at Vdd=5V
Figure 57. VOL high sink vs. VDD
Vol_10mA (V) at Iio=10mA
0.6
0.95
0.59

0.58
0.85
0.57
Vol_25mA (V)

Vol_10mA (V)

0.75 0.56

0.55
0.65
0.54

0.55 0.53

0.52
0.45
0.51

0.35 0.5
15 20 25 30 35 4 4.2 4.4 4.6 4.8 5 5.2 5.4
Iio (mA) Vdd (V)

123/139
Electrical characteristics ST7260xx

Figure 58. VOL standard vs. VDD Figure 59. VOL very high sink vs. VDD
Vol_2mA (mV) at Iio=2mA Vol_25mA (V) at Iio=25mA
130 0.8

125
0.75
Vol_2mA (mV)

Vol_25mA (V)
120

0.7

115

0.65
110

105 0.6
4 4.2 4.4 4.6 4.8
Vdd (V)
5 5.2 5.4 4 4.2 4.4 4.6 4.8
Vdd (V)
5 5.2

( s ) 5.4

c t
Figure 60. |VDD-VOH| @ VDD=5 V (low
current)
Figure 61. |VDD-VOH| @ VDD=5 V (high
current)
d u
|Vdd - Voh| (V) at Vdd=5V
r o
|Vdd - Voh| (V) at Vdd=5V
0.3 2

1.8

e P
et
0.25
1.6

0.2

o l 1.4
|Vdd - Voh| (V)
|Vdd - Voh| (V)

1.2

0.15

b s 1

0.8

O
0.1
0.6

0.05

) - 0.4

0.2

0
1 1.5 2

t
2.5
( s 3 3.5 4
0
2 7 12 17

c
-Iio (mA) -Iio (mA)

Figure 62. |VDD-VOH| @ IIO=2 mA (low

d u Figure 63. |VDD-VOH| @ IIO=10mA (high
current)
r o current)

0.165
P |Vdd - Voh| (V) at Iio=-2mA
0.9
|Vdd - Voh| (V) at Iio=-10mA

ete
0.16 0.8

l 0.155 0.7

o 0.15 0.6
|Vdd - Voh| (V)
|Vdd - Voh| (V)

s 0.145 0.5

Ob
0.14 0.4

0.135 0.3

0.13 0.2

0.125 0.1

0.12 0
4 4.2 4.4 4.6 4.8 5 5.2 5.4 4 4.2 4.4 4.6 4.8 5 5.2 5.4
Vdd (V) Vdd (V)

124/139
 ST7260xx Electrical characteristics

16.9 Control pin characteristics

16.9.1 Asynchronous RESET pin

Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.

Table 72. RESET pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

VIH Input high level voltage 0.7xVDD VDD V

VIL Input low voltage VSS 0.3xVDD V
Vhys Schmitt trigger voltage hysteresis (1) 400
s ) mV
IIO=5 mA 0.8
t(
uc
VOL Output low level voltage (2) VDD=5V V
IIO=7.5 mA 1.3
RON Weak pull-up equivalent resistor (3) VIN=VSS VDD=5 V 50

r od
80 100 kΩ

tw(RSTL)out Generated reset pulse duration

External pin or
internal reset sources
e P 6
30
1/fSFOSC
μs
th(RSTL)in External reset pulse hold time (4)
l e t 5 μs

o
1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

s
b
2. The IIO current sunk must always respect the absolute maximum rating specified in Section 16.2 and the sum of IIO (I/O ports and control
pins) must not exceed IVSS.

O
3. The RON pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results, not tested in production.

-
)
4. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin. All short pulses applied on RESET pin with a duration

(s
below th(RSTL)in can be ignored.

c t
d u
r o
e P
l e t
s o
O b

125/139
Electrical characteristics ST7260xx

RESET pin protection when LVD is enabled

When the LVD is enabled, it is recommended to protect the RESET pin as shown in
Figure 64 and follow these guidelines:
1. The reset network protects the device against parasitic resets.
2. The output of the external reset circuit must have an open-drain output to drive the ST7
reset pad. Otherwise the device can be damaged when the ST7 generates an internal
reset (LVD or watchdog).
3. Whatever the reset source is (internal or external), the user must ensure that the level
on the RESET pin can go below the VIL max. level specified in Section 16.9.1.
Otherwise the reset will not be taken into account internally.
4. Because the reset circuit is designed to allow the internal RESET to be output in the
RESET pin, the user must ensure that the current sunk on the RESET pin (by an
s )
t(
external pull-up for example) is less than the absolute maximum value specified for
c
5.
IINJ(RESET) in Section 16.2 on page 111.

d u
When the LVD is enabled, it is mandatory not to connect a pull-up resistor. A 10nF pull-
down capacitor is recommended to filter noise on the reset line.
r o
6.
P
In case a capacitive power supply is used, it is recommended to connect a 1M ohm

e
pull-down resistor to the RESET pin to discharge any residual voltage induced by this

le t
capacitive power supply (this will add 5µA to the power consumption of the MCU).
Tips when using the LVD:
s o
●
b
Check that all recommendations related to reset circuit have been applied (see section
above)
O
●
-
Check that the power supply is properly decoupled (100 nF + 10 µF close to the MCU).
)
Refer to AN1709. If this cannot be done, it is recommended to put a 100 nF + 1M Ohm
pull-down on the RESET pin.
t ( s
●
c
The capacitors connected on the RESET pin and also the power supply are key to
u
avoiding any start-up marginality. In most cases, steps 1 and 2 above are sufficient for a

o d
robust solution. Otherwise: Replace 10nF pull-down on the RESET pin with a 5 µF to
r
20 µF capacitor.
P
e t e
o l Figure 64. RESET pin protection when LVD is enabled

bs
VDD ST72XXX

O Required Optional
(note 6)
RON
INTERNAL
EXTERNAL RESET
RESET Filter

0.01 μF
1 MΩ WATCHDOG
PULSE
GENERATOR
LVD RESET

126/139
ST7260xx Electrical characteristics

RESET pin protection when LVD is disabled

When the LVD is disabled, it is recommended to protect the RESET pin as shown in
Figure 65 and follow these guidelines:
1. The reset network protects the device against parasitic resets.
2. The output of the external reset circuit must have an open-drain output to drive the ST7
reset pad. Otherwise the device can be damaged when the ST7 generates an internal
reset (LVD or watchdog).
3. Whatever the reset source is (internal or external), the user must ensure that the level
on the RESET pin can go below the VIL max. level specified in Section 16.9.1.
Otherwise the reset will not be taken into account internally.
4. Because the reset circuit is designed to allow the internal RESET to be output in the
RESET pin, the user must ensure that the current sunk on the RESET pin (by an
s )
external pull-up for example) is less than the absolute maximum value specified for
c t(
IINJ(RESET) in Section 16.2 on page 111.

d u
Figure 65. RESET pin protection when LVD is disabled
r o
VDD

e P ST72XXX

RON
le t
so
INTERNAL
EXTERNAL RESET

b
RESET Filter
CIRCUIT
0.01 μF

- O PULSE
GENERATOR
WATCHDOG

Required

( s )
16.9.2
u
USB - universal bus interface ct
o d
P
Table 73.
r
Operating conditions TA = 0 to +70 °C, VDD = 4.0 to 5.25 V unless otherwise specified.

USB DC electrical characteristics

e
let
Symbol Parameter Conditions(1) Min. Max. Unit

so
VDI Differential Input Sensitivity I(D+, D-) 0.2

Ob
Differential Common Mode
VCM Includes VDI range 0.8 2.5
Range
Single Ended Receiver
VSE 0.8 2.0
Threshold
V
RL(2) of 1.5 Kohms
VOL Static Output Low 0.3
to 3.6v
RL (2) of 15 Kohms
VOH Static Output High 2.8 3.6
to VSS
USBV USBVCC: voltage level (3) VDD=5 V 3.00 3.60
1. All the voltages are measured from the local ground potential.
2. RL is the load connected on the USB drivers.
3. To improve EMC performance (noise immunity), it is recommended to connect a 100nF capacitor to the USBVCC pin.

127/139
 Electrical characteristics ST7260xx

Figure 66. USB: data signal rise and fall time

Differential
Data Lines Crossover
points
VCRS

VSS

tr

)
tf

t( s
Table 74. USB: low-speed electrical characteristics
u c
Symbol Parameter Conditions Min

o d Max Unit

Driver characteristics:
CL=50 pF (1)
P r75 ns
tr Rise time
CL=600 pF
e t
(1)e 300 ns

o l
CL=50 pF (1) 75 ns
tf Fall Time
s
Ob
(1)
CL=600 pF 300 ns
Rise/ Fall Time

)-
trfm tr/tf 80 120 %
matching

VCRS
(
Output signal

t s
Crossover Voltage
1.3 2.0 V

u c
1. For more detailed information, please refer to Chapter 7 (Electrical) of the USB specification (version 1.1).

o d
16.9.3
r
SCI - serial communications interface
P
e t e
Subject to general operating condition for VDD, fCPU, and TA unless otherwise specified.

o l Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (RDI and TDO).

b s
Table 75. SCI characteristics
O Conditions
Baud
Symbol Parameter Accuracy Standard Unit
Rate
fCPU vs. Prescaler
Standard

Conventional Mode
TR (or RR)=128, PR=13 300 ~300.48
TR (or RR)= 32, PR=13 1200 ~1201.92
TR (or RR)= 16, PR=13 2400 ~2403.84
fTx
Communication frequency 8 MHz ~0.16% TR (or RR)= 8, PR=13 4800 ~4807.69 Hz
fRx TR (or RR)= 4, PR=13 9600 ~9615.38
TR (or RR)= 16, PR= 3 10400 ~10416.67
TR (or RR)= 2, PR=13 19200 ~19230.77
TR (or RR)= 1, PR=13 38400 ~38461.54

128/139
 ST7260xx Package characteristics

17 Package characteristics

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

17.1 Package mechanical data

Figure 67. 24-pin plastic small outline package, 300-mil width

s )
t(
uc
mm inches(1)
Dim.
D Min Typ Max Min Typ Max

d
h x 45×
L A 2.35 2.65 0.0925 0.1043
A1
A
C A1 0.10

r o 0.30 0.0039 0.0118

eP
a B 0.33 0.51 0.0130 0.0201
B e
C 0.23 0.32 0.0091 0.0126

l e t D
E
e
15.20
7.40
1.27
15.60
7.60
0.5984
0.2913
0.0500
0.6142
0.2992

o
bs
H 10.00 10.65 0.3937 0.4193
h 0.25 0.75 0.098 0.0295
E H α 0° 8° 0° 8°

- O L 0.40 1.27 0.0157

Number of Pins
0.0500

( s ) N 24

t
1. Values in inches are converted from mm and
rounded to 4 decimal digits.

u c
o d
r
Figure 68. 40-lead very thin fine pitch quad flat no-lead package

P
e
A2

l e t SEATING
PLANE A1
A3
Dim.
mm inches(1)

o
Min Typ Max Min Typ Max
D

b s A
A1
0.80 0.90
0.02
1.00
0.05
0.0315 0.0354 0.0394
0.0008 0.0020

O
A2 0.65 1.00 0.0256 0.0394
A3 0.20 0.0079
b 0.18 0.25 0.30 0.0071 0.0098 0.0118
D 5.85 6.00 6.15 0.2303 0.2362 0.2421
D2
D2 2.75 2.9 3.05 0.1083 0.1142 0.1201
E 5.85 6 6.15 0.2303 0.2362 0.2421
E2 E E2 2.75 2.9 3.05 0.1083 0.1142 0.1201
e 0.50 0.0197
PIN #1 ID TYPE C
RADIUS L 0.30 0.40 0.50 0.0118 0.0157 0.0197
2 Number of Pins
1 N 40
L 1.Values in inches are converted from mm and rounded
to 4 decimal digits.
b e

129/139
 Package characteristics ST7260xx

17.1.1 Thermal characteristics

Table 76. Package thermal characteristics

Symbol Ratings Value Unit

Package thermal resistance (junction to

ambient)
RthJA °C/W
SO24 70
QFN40 34
PD Power dissipation (1) 500 mW
TJmax (2)
Maximum junction temperature 150 °C

s )
1. The maximum power dissipation is obtained from the formula PD = (TJ -TA) / RthJA. The power dissipation

t(
of an application can be defined by the user with the formula: PD=PINT+PPORT where PINT is the chip
internal power (IDDxVDD) and PPORT is the port power dissipation depending on the ports used in the
application.

u c
2. The maximum chip-junction temperature is based on technology characteristics.

o d
P r
t e
o le
b s
- O
( s )
c t
d u
r o
e P
l e t
s o
O b

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 ST7260xx Device configuration and ordering information

18 Device configuration and ordering information

Each device is available for production in user programmable versions (High Density
FLASH) as well as in factory coded versions (FASTROM).
ST72P60 devices are Factory Advanced Service Technique ROM (FASTROM) versions:
they are factory programmed FLASH devices.
ST72F60 FLASH devices are shipped to customers with a default content (FFh).
This implies that FLASH devices have to be configured by the customer using the Option
Byte while the FASTROM devices are factory-configured.

s )
18.1 Option byte
c t(
d u
The Option Byte allows the hardware configuration of the microcontroller to be selected.

r o
The Option Byte has no address in the memory map and can be accessed only in
P
programming mode using a standard ST7 programming tool. The default contents of the

e
LVD.
le t
FLASH is fixed to F7h. This means that all the options have “1” as their default value, except

Table 77. Flash option byte

s o
7

O b 0

-- -- WDG SW

) - WD HALT LVD -- OSC 24/12 FMP_R

OPT 7:6 = Reserved.

t ( s
c
OPT 5 = WDGSW Hardware or Software Watchdog
u
o d
This option bit selects the watchdog type.
0: Hardware enabled
r
1: Software enabled
P
e te
OPT 4 = WDHALT Watchdog and HALT mode
This option bit determines if a RESET is generated when entering HALT mode while the

o l Watchdog is active.

b s 0: No Reset generation when entering Halt mode

1: Reset generation when entering Halt mode

O OPT 3 = LVD Low Voltage Detector selection

This option bit selects the LVD.
0: LVD enabled
1: LVD disabled
OPT 2 = Reserved.
OPT 1 = OSC24/12 Oscillator Selection
This option bit selects the clock divider used to drive the USB interface at 6 MHz.
0: 24 MHz oscillator
1: 12 Mhz oscillator
OPT 0 = FMP_R Flash memory readout protection
This option indicates if the user flash memory is protected against readout. readout
protection, when selected, provides a protection against Program Memory content

131/139
Device configuration and ordering information ST7260xx

extraction and against write access to Flash memory. Erasing the option bytes when the
FMP_R option is selected, causes the whole user memory to be erased first and the device
can be reprogrammed. Refer to the ST7 Flash Programming Reference Manual and
Section 5.3.1 on page 18 for more details.
0: Readout protection enabled
1: Readout protection disabled

18.2 Device ordering information and transfer of customer code

Customer code is made up of the FASTROM contents and the list of the selected options (if
any). The FASTROM contents are to be sent on diskette, or by electronic means, with the
hexadecimal file in .S19 format generated by the development tool. All unused bytes must
s )
t(
be set to FFh.
The selected options are communicated to STMicroelectronics using the correctly
completed OPTION LIST appended. See page 110. u c
o d
code has been transferred.
P r
Refer to application note AN1635 for information on the counter listing returned by ST after

t e
The STMicroelectronics sales organization will be pleased to provide detailed information on
contractual points.

o le
Table 78. Supported part numbers
b s
-O
Program memory RAM
Sales type (1) Package
(bytes) (bytes)

(s)
ST72F60K2U1 384 QFN40
8 K Flash
ST72F60E2M1
c t 384 SO24
ST72F60K1U1
d u 4 K Flash
384 QFN40
ST72F60E1M1
r o 384 SO24

e P
ST72P60K2U1/xxx
8 K FASTROM
384 QFN40

let
ST72P60E2M1/xxx 384 SO24
ST72P60K1U1/xxx 384 QFN40

s o ST72P60E1M1/xxx
4 K FASTROM
384 SO24

Ob 1. /xxx stands for the ROM code name assigned by STMicroelectronics. Contact ST sales office for product
availablity of FASTROM types (shaded in table).

18.3 Development tools

STMicroelectronics offers a range of hardware and software development tools for the ST7
microcontroller family. Full details of tools available for the ST7 from third party
manufacturers can be obtain from the STMicroelectronics Internet site:
➟ http//www.st.com.
Tools from these manufacturers include C compliers, emulators and gang programmers.
STMicroelectronics Tools

132/139
 ST7260xx Device configuration and ordering information

Three types of development tool are offered by ST see Table 79 and Table 80 for more
details.

Table 79. STMicroelectronics tools features

Programming
In-Circuit Emulation Software Included
capability(1)

Yes, powerful ST7 CD ROM with:

emulation features ST7 Assembly toolchain
ST7 Emulator No
including trace/ logic STVD7 powerful Source
analyzer Level Debugger for Win 3.1,
Win 9x and NT

)
C compiler demo versions
s
ST7 Programming
Board
No Yes (All packages)
c t(
Windows Programming
Tools for Win 3.1, Win 9x
and NT

d u
1. In-Circuit Programming (ICP) interface for FLASH devices.
r o
Table 80. Dedicated STMicroelectronics development tools
e P
Supported products Evaluation board
le t
ST7 emulator
ST7 programming

s o board

ST7260 ST7MDTULS-EVAL

O b
1. Add Suffix /EU or /US for the power supply for your region.
ST7MDTU3-EMU3 ST7MDTU3-EPB (1)

) -
t ( s
u c
o d
P r
e t e
o l
b s
O

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 Device configuration and ordering information ST7260xx

ST7260 MICROCONTROLLER OPTION LIST

(Last update: January 2009)

Customer: ...........................................................
Address: ...........................................................
...........................................................
Contact: ...........................................................
Phone No: ...........................................................
Reference: ...........................................................

FASTROM code must be sent in .S19 format.

Hex extension cannot be processed.
STMicroelectronics references:

Device Type/Memory Size/Package (check only one option):

------------------------------------------------------------------------------------
FASTROM: | 4K | 8K |
s )
------------------------------------------------------------------------------------
SO24: | [ ] ST72P60E1M1 | [ ] ST72P60E2M1|
ct(
QFN40: | [ ] ST72P60K1U1 | [ ] ST72P60K2U1|

d u
Conditioning (check only one option):
r o
Packaged Product
------------------------------------------------------------------------------------

e P
[ ] Tape & Reel (SO package only)
[ ] Tube

le t
Special Marking: [ ] No
s o
[ ] Yes "_ _ _ _ _ _ _ _ _ _ _ _ _"

O b
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
For marking, one line is possible with a maximum of 13 characters.

Halt when Watchdog on:[ ] Reset

) -
Watchdog Selection: [ ] Software activation[ ] Hardware activation
[ ] No reset
LVD Reset * [ ] Disabled*

t ( s[ ] Enabled*

c
du
Oscillator Selection: [ ] 24 MHz. [ ] 12 MHz.
Readout Protection: [ ] Disabled [ ] Enabled

Date
r o ...........................................................

Signature
e P ...........................................................

e tPlease download the latest version of this option list from:

http://www.st.com/

s ol
O b

134/139
 ST7260xx Known limitations

19 Known limitations

19.1 PA2 limitation with OCMP1 enabled

Description
This limitation affects only Rev B Flash devices (with Internal Sales Type 72F60xxxxx$x7); it
has been corrected in Rev W Flash devices (with Internal Sales Type 72F60xxxxx$x9).
Refer to Figure 69 on page 137.
When Output Compare 1 function (OCMP1) on pin PA6 is enabled by setting the OC1E bit in
the TCR2 register, pin PA2 is also affected.

s )
has set it as output low. However, it can be still used as an input.
c t(
In particular, the PA2 pin is forced to be floating even if port configuration (PADDR+PADR)

d u
19.2 Unexpected reset fetch r o
e P
If an interrupt request occurs while a "POP CC" instruction is executed, the interrupt

le t
controller does not recognise the source of the interrupt and, by default, passes the RESET
vector address to the CPU.
Workaround s o
O b
To solve this issue, a "POP CC" instruction must always be preceded by a "SIM" instruction.

) -
19.3 SCI wrong break duration
t ( s
Description
u c
o d
A single break character is sent by setting and resetting the SBK bit in the SCICR2 register.

● P r
In some cases, the break character may have a longer duration than expected:
20 bits instead of 10 bits if M=0
●
e t e 22 bits instead of 11 bits if M=1

o l In the same way, as long as the SBK bit is set, break characters are sent to the TDO pin.

b s This may lead to generate one break more than expected.

O Occurrence
The occurrence of the problem is random and proportional to the baudrate. With a transmit
frequency of 19200 baud (fCPU=8 MHz and SCIBRR=0xC9), the wrong break duration
occurrence is around 1%.
Workaround
If this wrong duration is not compliant with the communication protocol in the application,
software can request that an Idle line be generated before the break character. In this case,
the break duration is always correct assuming the application is not doing anything between
the idle and the break. This can be ensured by temporarily disabling interrupts.

135/139
 Known limitations ST7260xx

The exact sequence is:

● Disable interrupts
● Reset and Set TE (IDLE request)
● Set and Reset SBK (Break Request)
● Re-enable interrupts

s )
ct(
d u
r o
e P
le t
s o
O b
) -
t ( s
u c
o d
P r
e t e
o l
b s
O

136/139
 ST7260xx Device marking

20 Device marking

The silicon revision can be identified either by Rev letter or obtained via a trace code.
Follow the procedure below:
1. Identify the silicon revision letter from either the device package or the box label.
For example, “B”, etc. Refer to Figure 69.
2. If the revision letter is not present, obtain the silicon revision by contacting your local ST
office with the trace code information printed on either the box label or the device
package.

Figure 69. Identifying silicon revision from device marking and box label
s )
c t(
Silicon Rev

d u

STMicroelectronics
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

o
Trace code xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
ST7xxxxxxxxx

r
TYPE xxxxxxxxxxx$x7

Total Qty XX

P
Trace code XXXXXXXXX XX XX

Marking
Bulk ID
B
XXXXXXXXXX Silicon Rev

e
XXXXXXXXXXXX

Device package example

le t
so
Example box label

O b
) -
( s
u ct
o d
P r
e t e
o l
b s
O

137/139
 Revision history ST7260xx

21 Revision history

Table 81. Document revision history

Date Revision Changes

13-Feb-2006 1 Initial release.

18-Oct-2006 2 Added known limitations section
Added caution in Section 7.1 on page 25
Added reference to watchdog reset pulse tDOG in Section 12.3 on
page 44

s )
Removed EMC protective circuitry in Figure 65 on page 127 (device
05-Feb-2009 3 works correctly without these components)

c t(
Modified notes below Table 76: Package thermal characteristics on
page 130
d u
Section 17 on page 129
r o
Replaced soldering information with ECOPACK reference in

e P
le t
s o
O b
) -
t ( s
u c
o d
P r
e t e
o l
b s
O

138/139
 ST7260xx

s )
Please Read Carefully:

c t(
d u
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the

time, without notice.

r o
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any

All ST products are sold pursuant to ST’s terms and conditions of sale.

e P
le t
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

s o
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products

O b
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.

) -
t ( s
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED

u c
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

d
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT

o
r
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,

P
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE

e t e
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.

o l
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void

b s
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.

O ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

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