RISC

Architecture
 Presentation Topic - RISC ARCHITECTURE

Presentation Date - 08/11/2023

Submitted by-
1. Sanchari Mandal (GCECTB-R22-2038)
2. Kankan Mondal (GCECTB-R22-2037)
3. Srijani Sinha (GCECTB-R22-2039)
4. Subha Mistry (GCECTB-R22-2040)
5. Subhradeep Sardar (GCECTB-R22-2041)
6. Arghya Biswas (GCECTB-R22-2036)

Department -Information Technology

Introduction:
RISC stands for Reduced Instruction Set Computer. It's a microprocessor
architecture that uses a small, highly-optimized set of instructions to reduce
execution time. RISC instructions generally include register-to-register operations.

RISC architecture is designed to simplify the individual instructions given to the

computer to accomplish tasks. It's built to minimize the instruction execution time
by optimizing and limiting the number of instructions.

Examples of RISC processors include:

Alpha, ARC, ARM, AVR, MIPS, PA-RISC, PIC, Power Architecture, SPARC.
History:
The Reduced Instruction Set Computer (RISC) architecture began in the late 1970s and early
1980s as a counter-approach to CISC. The term RISC was coined by David Patterson, a
computer science professor at the University of California, Berkeley.

The first RISC projects came from IBM, Stanford, and UC-Berkeley. The IBM 801, Stanford MIPS,
and Berkeley RISC 1 and 2 were all designed with a similar philosophy. The IBM 801 was never
commercialized, but it influenced a generation of RISC designs.

The first computer to benefit from RISC was IBM's PC/XT in 1980. Later, IBM's RISC
System/6000, or RS/6000, also made use of the idea. Hewlett-Packard converted their existing
minicomputer line to RISC architectures.

Some experts believe that the first modern RISC system was created by John Cocke. The
inventor's project began in 1975, and it was completed in the form of the IBM 801 processor in
1980.
Key Characteristics:
1. Simple Instructions: Instructions are kept simple and perform basic operations, allowing
them to be executed in a single clock cycle.
2. Load/Store Architecture: RISC architectures often use a load/store architecture, where
data must be loaded into registers before it can be operated upon. This minimizes the
number of instructions needed for complex operations.
3. Use of Registers: RISC processors typically have a larger number of registers for storing
data, reducing the need for frequent memory access.
4. Pipelining: RISC processors often employ pipelining, allowing multiple instructions to be in
various stages of execution simultaneously, further enhancing performance.
5. Fixed Instruction Length: Instructions in RISC architectures have a fixed length, making
the instruction decoding process simpler and faster.
Different RISC Architectures
ARM (Advanced RISC Machine): Developed in the 1980s by Acorn Computers and later refined
by ARM Holdings. It has evolved into one of the most popular RISC architectures.
Significance: Known for energy efficiency and widespread use in mobile devices, embedded
systems, and servers.

MIPS (Microprocessor without Interlocked Pipeline Stages):Created in the mid-1980s at

Stanford University, MIPS gained recognition in various applications.
Significance: Notable for its simplicity in design and early adoption in home entertainment
systems and networking equipment.
Different RISC Architectures
PowerPC: Developed jointly by Apple, IBM, and Motorola in the early 1990s. Widely used in
Macintosh computers and gaming consoles.
Significance: Known for its performance and symmetric multiprocessing support.

SPARC (Scalable Processor Architecture): Originated in the mid-1980s by Sun

Microsystems, focusing on high-performance computing and server applications.
Significance: Notable for register windows and parallel processing capabilities.

RISC-V: Emerged in the 2010s as an open-source RISC architecture designed at UC Berkeley.

Significance: Gaining popularity for its open and modular design, with applications spanning
from IoT to high-performance computing.
Advantages
1. High Performance: RISC architectures often deliver high performance due to the
simplicity of instructions, allowing for faster execution in a single clock cycle.
2. Efficient Use of Registers: With a focus on a large number of registers, RISC processors
minimize the need for accessing memory frequently, improving overall speed.
3. Simpler Pipeline Design: The instruction pipeline in RISC architecture is typically simpler,
enabling better utilization of hardware resources and facilitating pipelining for improved
performance.
4. Scalability: RISC architectures are scalable, making them suitable for a wide range of
applications from embedded systems to high-performance computing.
5. Reduced Power Consumption: The streamlined design and efficient execution of
instructions contribute to lower power consumption, making RISC architectures suitable
for mobile and battery-powered devices.
Disadvantages
1. More Instructions Needed: Simple instructions mean more of them: RISC processors use
basic instructions, which can result in needing more instructions to perform complex tasks.
This can make the programs longer.
2. Limited Flexibility: Not versatile enough: RISC focuses on simplicity, which might limit its
ability to handle certain complex tasks that require more versatile and complex instructions.
3. Transition Challenges: Switching can be tricky: If you want to move from a different
architecture (like CISC) to RISC, or vice versa, it can be challenging. Programs might not work
as expected without some adjustments.
4. Memory Bandwidth Issues: Struggles with lots of data: RISC architectures might face
challenges when dealing with tasks that require a lot of data to be moved in and out of
memory quickly.
5. Smart compilers needed: While the architecture itself is straightforward, making sure
programs run efficiently on RISC processors requires smart and complex optimization by
compilers.
Applications of RISC Architectures
1. Low-End and Mobile Systems: RISC architectures power mobile devices. ARM
dominates, used in Android, Apple products, and Raspberry Pi. PowerPC and MIPS have
found places in gaming consoles and SuperH remains relevant.
2. Desktop and Laptop Computers: RISC architectures impact desktops and laptops.
PowerPC was used in Apple's Macintosh. ARM-based platforms are adopted in some
Chromebooks, and Apple transitioned to ARM processors.
3. Workstations, Servers, and Supercomputers: RISC architectures are key in
workstations, servers, and supercomputers. MIPS and SPARC have a significant
presence, and RISC-V is emerging, as seen in Fujitsu's Fugaku supercomputer.
4. Open Source: RISC architectures are popular in open source for their simplicity.
Examples include OpenRISC, LEON, Libre-SOC, and various RISC-V implementations,
fostering innovation in computer architecture.
Conclusion:
In conclusion, RISC architectures have a widespread impact, from powering mobile devices and
desktops to driving workstations and servers. Their simplicity and adaptability make them
pivotal in open-source innovation, paving the way for future developments in computer
architecture.
Thank You