Assembler Programming of Atmega328P

(Lecture-14)

R S Ananda Murthy

Associate Professor
Department of Electrical & Electronics Engineering,
Sri Jayachamarajendra College of Engineering,
Mysore 570 006

R S Ananda Murthy Assembler Programming of Atmega328P

Specific Learning Outcomes

After completing this lecture, the student should be able to –

Describe different methods of I/O operation that can be
performed by an MCU.
Write assembly language program to use INT0 and INT1
interrupts.
Write assembly language program to use PICINTx
interrupts.

R S Ananda Murthy Assembler Programming of Atmega328P

Methods of I/O Operation

Synchronous I/O operation.

This is possible when the I/O device operates at the same
speed as that of MCU.
In this case the I/O operation with the device is performed
by the MCU assuming that the device is always ready.
Asynchronous I/O Operation.
In this case, the I/O device is very slow when compared to
the MCU. Then, it can perform I/O operation by the
following methods:
By polling.
By using interrupts.

R S Ananda Murthy Assembler Programming of Atmega328P

I/O Operation by Polling

Request device to get ready

Is
the device No
ready
?

Yes

Service the device

Polling results in waste of MCU time and power and does

not permit disabling of interrupts by devices since all
devices have to be checked.

R S Ananda Murthy Assembler Programming of Atmega328P

Polling Example

Start

Configure I/O Ports

Is
Yes No
Turn ON LED Pushbutton Turn OFF LED
pressed
?

In this case the MCU is simply wasting time monitoring the

status of the pushbutton.

R S Ananda Murthy Assembler Programming of Atmega328P

I/O Operation by Interrupts

With interrupts enabled, the MCU keeps doing some useful

operation, or it may stay in a power saving mode.
The I/O device that wants service, interrupts the MCU.
The MCU executes the current instruction, saves the return
address on the stack, and jumps to the Interrupt Service
Routine (ISR) through the Interrupt Vector Address.
At the end of ISR, the MCU executes RETI instruction to
pop back return address from the stack to the Program
Counter and resumes execution of the interrupted program.
Interrupts can be enabled or disabled dynamically.
When two interrupts occur simultaneously, the MCU
executes the ISR of higher priority.

R S Ananda Murthy Assembler Programming of Atmega328P

Interrupt Example

Start Save return address

A and data of main
program on stack
Configure I/O Ports
Enable Interrupts
Turn ON LED
for 1 second

Turn OFF LED

Restore data of main
program into registers
Keep on doing some
useful operation or Enable interrupts
No be in low-power mode
Interrupt
On
Restore return
Interrupt
A address to PC

When interrupt occurs the LED glows for 1 second.

R S Ananda Murthy Assembler Programming of Atmega328P

Default Interrupt Vectors in Atmega328P

R S Ananda Murthy Assembler Programming of Atmega328P

Interrupt Vectors in Atmega328P

Interrupt vector is a definite address in the program

memory where a JMP instruction should be written to jump
to the ISR corresponding to the interrupt.
Each interrupt vector occupies two program memory words
in order to provide space for JMP instruction.
In Atmega328P, the RESET Vector is affected by
BOOTRST fuse and the Interrupt Vector start address is
affected by IVSEL bit in the MCUCR.

R S Ananda Murthy Assembler Programming of Atmega328P

Important Points regarding Interrupts in Atmega328P

Interrupt having lower vector address has higher priority.

When the MCU is reset all interrupts are disabled.
When the MCU jumps to ISR the I-bit in SREG is
automatically cleared to disable interrupts during ISR.
When RETI is executed by the MCU the I-bit in SREG is
automatically set to enable future interrupts.

R S Ananda Murthy Assembler Programming of Atmega328P

23 Pins for Triggering Interrupts in Atmega328P

INT0 and INT1 are known as External Interrupts and

PCINTxx are known as Pin Change Interrupts.

R S Ananda Murthy Assembler Programming of Atmega328P

Enabling and Disabling Interrupts in Atmega328P

In SREG if I = 1, then all interrupts are enabled.

We can make I = 1 by using SEI instruction in ALP and
sei() function in C program.
In SREG if I = 0, then all interrupts are disabled.
We can make I = 0 by using CLI instruction in ALP and
cli() function in C program.
Upon reset I = 0 so all interrupts are disabled.

R S Ananda Murthy Assembler Programming of Atmega328P

Bits of EICRA Control Nature of INT1 and INT0

Bits 7, 6, 5, and 4 are not used and are always read as 0.

R S Ananda Murthy Assembler Programming of Atmega328P

Bits of EIMSK Mask/Unmask INT1 and INT0

Masking/unmasking means disabling/enabling respectively.

When INT1 = 1 INT1 is unmasked if I = 1 in SREG.
When INT1 = 0 INT1 is masked even if I = 1 in SREG.
When INT0 = 1 INT0 is unmasked if I = 1 in SREG.
When INT0 = 0 INT0 is masked even if I = 1 in SREG.
Activity on the pins of INT1/INT0 will cause an interrupt
request even if the corresponding pins are configured as
output pins.
Bits 2 to 7 are unused and will always be read as 0.

R S Ananda Murthy Assembler Programming of Atmega328P

Bits of EIFR Show Status of INT1 and INT0

Bits 2 to 7 are unused and will always be read as 0.

When INT1 interrupt is triggered, INTF1 becomes 1. This
flag is cleared when ISR is executed.
When INT0 interrupt is triggered, INTF0 becomes 1. This
flag is cleared when ISR is executed.
INTF1/INTF0 flags can be cleared by writing a logical 1 to
the respective bit.
INTF1/INTF0 flags are always cleared when the respective
interrupts are configured as a level interrupt.

R S Ananda Murthy Assembler Programming of Atmega328P

PCICR – Pin Change Interrupt Control Register

Bits 7:3 are unused and they are always read as zero.
WhenPCIE2 = 1 and I-bit in in SREG is 1 PCINT2 interrupt
is enabled. Then, any change on any enabled
PCINT[23:16] pin will cause an interrupt.
WhenPCIE1 = 1 and I-bit in in SREG is 1 PCINT1 interrupt
is enabled. Then, any change on any enabled PCINT[14:8]
pin will cause an interrupt.
WhenPCIE0 = 1 and I-bit in in SREG is 1 PCINT0 interrupt
is enabled. Then, any change on any enabled PCINT[7:0]
pin will cause an interrupt.

R S Ananda Murthy Assembler Programming of Atmega328P

PCIFR – Pin Change Interrupt Flag Register

Bits 7:3 are unused and they are always read as zero.
PCIF2 = 1 when a logic change on any PCINT[23:16] pin
triggers an interrupt request. This flag is cleared when the
interrupt routine is executed.
PCIF1 = 1 when a logic change on any PCINT[14:8] pin
triggers an interrupt request. This flag is cleared when the
interrupt routine is executed.
PCIF0 = 1 when a logic change on any PCINT[7:0] pin
triggers an interrupt request. This flag is cleared when the
interrupt routine is executed.
PCIFx flag can also be cleared by writing 1 into the bit.

R S Ananda Murthy Assembler Programming of Atmega328P

PCMSK2 – Pin Change Mask Register 2

Each PCINT[23:16]-bit selects whether pin change

interrupt is enabled on the corresponding I/O pin. If
PCINT[23:16] is set and the PCIE2 bit in PCICR is set, pin
change interrupt is enabled on the corresponding I/O pin. If
PCINT[23:16] is cleared, pin change interrupt on the
corresponding I/O pin is disabled.

R S Ananda Murthy Assembler Programming of Atmega328P

PCMSK1 – Pin Change Mask Register 1

Bit 7 is not used and is always read as 0.

Each PCINT[14:8]-bit selects whether pin change interrupt
is enabled on the corresponding I/O pin. If PCINT[14:8] is
set and the PCIE1 bit in PCICR is set, pin change interrupt
is enabled on the corresponding I/O pin. If PCINT[14:8] is
cleared, pin change interrupt on the corresponding I/O pin
is disabled.

R S Ananda Murthy Assembler Programming of Atmega328P

PCMSK0 – Pin Change Mask Register 0

Each PCINT[7:0] bit selects whether pin change interrupt

is enabled on the corresponding I/O pin. If PCINT[7:0] is
set and the PCIE0 bit in PCICR is set, pin change interrupt
is enabled on the corresponding I/O pin. If PCINT[7:0] is
cleared, pin change interrupt on the corresponding I/O pin
is disabled.

R S Ananda Murthy Assembler Programming of Atmega328P

Problem Statement to use INT0/INT1

Assume that a push button is connected to the INT0/PD2 pin of

Atmega328P MCU with internal pull-up resistor enabled and
that a 7-segment common cathode display is connected to
PORTB lines of the MCU through 330 Ω current limiting
resistors. Let a high-to-low logic change on this pin cause an
INT0 interrupt. Sketch a diagram showing the hardware
connections. Write an ALP to display on the LED display any
integer in the range 1 to 6, both inclusive, when ever the push
button is pressed, thus simulating throwing of a dice. Sketch a
flow chart to show the logic.

Modify the program written above to use INT1/PD3.

R S Ananda Murthy Assembler Programming of Atmega328P

Hardware for Simulating Dice

Atmega328P Common Cathode Type

h
10 PB7 g
9 PB6
19 PB5 f
INT0/PD2 18 PB4 e
4 d
17 PB3
16 PB2 c
15 PB1 b
14 PB0 a

Pin numbers correspond to DIP package of MCU.

Program for simulation of dice is given in the next slide.

R S Ananda Murthy Assembler Programming of Atmega328P

License

This work is licensed under a

Creative Commons Attribution 4.0 International License.

R S Ananda Murthy Assembler Programming of Atmega328P