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TCL Commands.

The document lists 100 essential TCL commands for physical design interviews, providing a command for various interview questions related to TCL scripting. Each command is paired with a specific task, such as setting variables, reading design files, performing routing, and generating reports. This serves as a comprehensive guide for candidates preparing for interviews in VLSI physical design.
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0% found this document useful (0 votes)
42 views7 pages

TCL Commands.

The document lists 100 essential TCL commands for physical design interviews, providing a command for various interview questions related to TCL scripting. Each command is paired with a specific task, such as setting variables, reading design files, performing routing, and generating reports. This serves as a comprehensive guide for candidates preparing for interviews in VLSI physical design.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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100 MUST-KNOW TCL COMMANDS

FOR PHYSICAL DESIGN INTERVIEW

Interview Question TCL Command

1 How do you set a variable? set var_name value

How do you print a variable’s


2 puts $var_name
value?

3 How do you do a loop in TCL? foreach item $list { puts $item }

4 How do you check conditionals? if {$a > 5} {puts "yes"}

5 How do you source a script? source script.tcl

6 How to define a procedure? proc name {args} { body }

How do you append to a


7 append a $b
variable?

How do you concatenate


8 set x [concat $a $b]
strings?

9 How do you exit the script? exit

10 How do you comment in TCL? # This is a comment

11 How do you read a design? read_verilog design.v

12 How do you read libraries? read_libs liberty.lib

13 How do you link design? link_design top

14 How do you set search path? set_app_var search_path "."

15 How to read DEF file? read_def design.def


Interview Question TCL Command

16 How to read LEF file? read_lef tech.lef

17 How to write out netlist? write_verilog out.v

18 How to write a DEF file? write_def design_out.def

19 How to get list of cells? get_cells *

20 How to get ports? get_ports

21 How do you create a floorplan? create_floorplan -core ...

create_boundary -box {x1 y1 x2


22 How do you create a boundary?
y2}

How to define power


23 add_stripes / add_rings
rings/straps?

How to define placement


24 create_placement_blockage
blockages?

How to define routing


25 create_routing_blockage
blockages?

set_attribute [get_cells
26 How to set macro orientation?
macro_name] orientation R0

set_attribute [get_cells
27 How to place macros manually?
macro_name] location {x y}

How to check floorplan


28 report_utilization
utilization?

29 How to report floorplan? report_floorplan

30 How to get area of a module? report_area

31 How to perform placement? place_design


Interview Question TCL Command

How to check placement


32 report_congestion
congestion?

33 How to check legalization? check_legality

34 How to move a cell? move_cell cell_name -to {x y}

35 How to report cell density? report_density

get_cells -filter "is_placed ==


36 How to report placed instances?
true"

get_cells -filter "is_placed ==


37 How to report unplaced cells?
false"

How to check design rule


38 report_drc
violations?

How to report placement


39 report_utilization -placement
utilization?

get_attribute [get_cells
40 How to get cell location?
cell_name] location

41 How do you run CTS? create_clock_tree

create_clock -name clk -period


42 How to define clock?
10 [get_ports clk]

set_clock_uncertainty 0.2
43 How to set clock uncertainty?
[get_clocks clk]

44 How to balance skew? report_clock_tree

get_cells -filter "is_clock_buffer


45 How to get clock buffers?
== true"

46 How to report clock latency? report_clock -latency


Interview Question TCL Command

47 How to trace clock path? trace_clock clk

48 How to buffer a clock manually? insert_buffer

49 How to check clock tree? check_clock_tree

How to disable CTS for certain


50 set_dont_touch_network
nets?

51 How to start global routing? route_design -global

52 How to start detailed routing? route_design -detail

53 How to check routing violations? report_drc -routing

54 How to fix shorts? repair_design -shorts

55 How to get routed nets? get_nets -routed

56 How to extract parasitics? extract_parasitics

57 How to perform RC extraction? rc_extract

58 How to report wirelength? report_wirelength

How to visualize congestion report_congestion -map


59
map? congestion.rpt

60 How to generate routed DEF? write_def routed.def

61 How to run timing analysis? report_timing

62 How to report critical paths? report_timing -max_paths 10

set_input_delay 2.5 -clock clk


63 How to set input delay?
[get_ports in]

set_output_delay 1.0 -clock clk


64 How to set output delay?
[get_ports out]
Interview Question TCL Command

65 How to define drive strength? set_drive 0.5 [get_ports in]

66 How to set load on output port? set_load 0.75 [get_ports out]

How to check hold/setup


67 report_constraints -all_violators
violations?

set_multicycle_path 2 -setup -
68 How to set multicycle path?
from X -to Y

69 How to set false path? set_false_path -from X -to Y

70 How to trace timing arc? report_timing -from A -to B

71 How to run power analysis? report_power

72 How to define power nets? set_power_net VDD

73 How to define ground nets? set_ground_net VSS

read_saif or
74 How to set switching activity?
set_switching_activity

75 How to get leakage power? report_power -leakage

76 How to get dynamic power? report_power -dynamic

77 How to annotate activity file? read_saif

78 How to generate power report? report_power > power.rpt

79 How to set toggle rate? set_switching_activity

How to report power per


80 report_power -hier
instance?

81 How to run DRC? report_drc

82 How to run LVS? run_lvs


Interview Question TCL Command

83 How to compare netlists? compare_netlists

84 How to check connectivity? report_connectivity

85 How to report shorts/opens? report_net_status

86 How to check missing vias? report_missing_vias

87 How to verify antenna rules? report_antennas

88 How to dump net RC? write_parasitics -format spef

89 How to list DRC violations? report_drc -violations

90 How to check final GDS? write_gds final.gds

91 How to run optimization? optimize_design

92 How to fix hold violations? repair_hold

93 How to fix setup violations? optimize_timing

94 How to report utilization? report_utilization

95 How to report area post-route? report_area

96 How to write SDF file? write_sdf final.sdf

How to export netlist for


97 write_verilog final_netlist.v
backend?

98 How to save session? save_design checkpoint.dcp

99 How to restore checkpoint? restore_design checkpoint.dcp

100 How to write all reports? report_design_summary


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