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RSA Implementation Using FPGA

This document presents the design and implementation of the RSA cryptographic algorithm using Field-Programmable Gate Arrays (FPGAs) to enhance secure communication systems. It details the process of key generation, encryption, and decryption, emphasizing the use of Verilog and the Xilinx ISE_14.7 Design Suite for hardware realization. The study highlights the trade-offs between speed, power, and space while addressing the challenges of implementing RSA modules on FPGA.

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0% found this document useful (0 votes)
6 views4 pages

RSA Implementation Using FPGA

This document presents the design and implementation of the RSA cryptographic algorithm using Field-Programmable Gate Arrays (FPGAs) to enhance secure communication systems. It details the process of key generation, encryption, and decryption, emphasizing the use of Verilog and the Xilinx ISE_14.7 Design Suite for hardware realization. The study highlights the trade-offs between speed, power, and space while addressing the challenges of implementing RSA modules on FPGA.

Uploaded by

Aditya Jha
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© © All Rights Reserved
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RSA Implementation Using FPGA

Nitin Singh Riya Sharma Nisha Chauhan


Department Of Electronics and Department Of Electronics And Department Of Electronics And
Communication Communication Communication
JSS Academy Of Technical Education, JSS Academy Of Technical Education, JSS Academy Of Technical Education,
2024 International Conference on Smart Systems for applications in Electrical Sciences (ICSSES) | 979-8-3503-6404-0/24/$31.00 ©2024 IEEE | DOI: 10.1109/ICSSES62373.2024.10561326

Noida Noida Noida


20ec094@jssaten.ac.in 20ec028@jssaten.ac.in 20ec155@jssaten.ac.in

Ms. Rajeshwari Bhat


Assistant Professor
Department Of Electronics And
Communication
JSS Academy Of Technical Education,
Noida
rajeshwaribhat2@jssaten.ac.in

Abstract— In this work, the cryptographic technique Field-Programmable Gate Arrays (FPGAs). FPGAs offer a
known as RSA is designed and implemented, with the goal unique blend of flexibility and performance, enabling
of becoming a standard in secure communication systems. hardware realization of complex cryptographic applications.
The basic idea of this algorithm is to create a confidential Its enduring popularity can be attributed to its superior
communication channel in between two parties (sender, and cryptographic properties, which ensure a degree of security
receiver). Verilog is used to code each module or block, and that is considered paramount in the modern environment of
the Xilinx ISE_14.7 Design Suite is used to synthesize and communication and data processing
simulate the code. A trade-off between speed, power, and
space is offered, and the design is geared toward speed. II. STEPS OF SECURE COMMUNICATION (DATA
FPGA is used as hardware to increase the speed and make TRANSFER)
the algorithm more secure. Our goal is to demonstrate, as a
The RSA algorithm is an asymmetric encryption algorithm
significant practical outcome, that the RSA algorithm can be
that uses two separate keys that are linked together: a public
implemented at secure bit lengths on a single piece of
key and a private key. Commonly used for encryption, the
commercial hardware—FPGA and the study covers the
design, optimization, and challenges of implementing RSA public key is the one that is widely known. Exclusively the
modules on FPGA, emphasizing modular exponentiation, private key can be used to decrypt messages encrypted using
key generation, and data handling. the public key [3]. Using the following procedures, the keys
are generated:
Keywords—Cryptography, Encryption, Decryption,
RSA, Security, Verilog, FPGA. 1. Encryption
1.1 Key Generation (Public Key)
I. INTRODUCTION 2. Data Transfer
In light of the recent explosion in electronic data 3. Decryption
communications and emerging technologies, it is critical to 3.1 Key Generation (Private Key)
create new and improved methods for ensuring the security
and safety of transferred data. Data that needs to be
encrypted and shielded from outside access can be in the
form of text, images, audio, or video. Cryptography is the
art of keeping messages safe. The use of cryptography is
essential to data security. In 1978, Adi Shamir, Leonard
Adleman, and Ron Rivest presented the RSA algorithm. It's
an extremely secure and high-quality public key
cryptography algorithm [1]. It is a means of creating digital
signatures and exchanging sensitive data, such as keys. Fig 1.0 Work-Flow Of RSA
However, the RSA algorithm's effort places computational
demands, particularly when processing very big integers, III.ENCRYPTION
which are often thousands of bits long [2]. These
Information is rendered incomprehensible to unauthorized
computational complexities pose challenges, especially
users by the process of encryption, which converts plaintext
when they need to be executed quickly and efficiently. Due into ciphertext. Encryption is essential for maintaining
to these challenges, integrating hardware acceleration has confidentiality, integrity, and authenticity since it prevents
emerged as a compelling solution to improve the
unwanted access and manipulation of sensitive data.
performance of RSA-based cryptographic systems in Encryption, which is widely used in digital communication
response to these demands, researchers and engineers have and storage, is essential to cybersecurity because it provides
explored new ways to implement RSA algorithms using a strong barrier against illegal access and data compromise.

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The foundation of contemporary cryptography, the RSA DIVIDER 16 BITS
algorithm, employs a distinct method of encryption. RSA The DIVIDER 16 BITS in the context of the RSA algorithm
employs two separate keys: a public key for encryption and plays a crucial role in breaking down the intricate
a private key for decryption, in contrast to symmetric key cryptographic processes into manageable components. In
methods. The encryption procedure is made even simpler by the realm of hardware-based RSA implementations on
the addition of complexity and security provided by this FPGAs, the DIVIDER 16 BITS stands as a fundamental
dual-key gadget. The first step in the RSA encryption arithmetic unit responsible for performing the division
process is to choose a public key, which is usually two large operation on binary data with a precision of 16 bits. To
prime numbers. These primes help generate a public key, comprehend its significance, let's delve into the logical
which is used explicitly for everyone. The public key, with underpinnings and operational intricacies of this pivotal
its associated parameter, forms the basis for plaintext component.
encryption [4].Once the public key is obtained, the The division process involves dividing a larger binary
encryption process proceeds by dividing the plain text into number (dividend) by a smaller binary number (divisor) to
smaller chunks. Each block goes through modular obtain a quotient and a remainder. The 16-bit divider
exponentiation, a basic step that uses arithmetic operations performs this operation on binary data of 16 bits each. The
to raise plaintext to public exponent powers, followed by a result of the division is typically a quotient and a remainder,
modulo of public parameters.[5]This modular both represented as 16-bit binary numbers. Here 16-bit
exponentiation operation generates ciphertext, and converts divider is utilized in RSA cryptography (using FPGA) as:
plaintext to signified characters if it is a random
sequence[6]. Encryption:
KEY GENERATION Prime numbers are generated. The 16-bit divider could be
This technique includes deciding on appropriate high used to check and ensure that the generated numbers are
numbers, computing modular mathematics, and figuring out prime.
the public and private key additives [7]. Here, we complex During the encryption process, the plaintext is typically
the key generation technique, highlighting its importance raised to the power of the public exponent modulo the
and underlying theoretical standards. public modulus (n). The modular exponentiation involves
multiple modular multiplications, where a 16-bit divider
1. Choose the prime numbers p and q, two different might be used to handle smaller chunks of the data
huge random numbers. efficiently.
2. 2. Type in n = p*q. The modulus is equal to n for Decryption:
both the public and private keys. In RSA decryption, the ciphertext is raised to the power of
3. Determine the Euler's function by computing ϕ (n) the private exponent modulo n. Similar to encryption,
= (p −1) (q −1). modular arithmetic with a 16-bit divider could be employed
4. Select an integer e so that 1<e< ϕ (n); e and ϕ in this process.
5. (n) share only one factor, which is 1 because e and
ϕ (n) are co-primes; e is revealed as the public DIVIDER 32 BITS
key's exponent. A 32-bit divider [9] is used in RSA cryptography as a
6. Find d such that ed ≡ 1 (mod φ(n)), or the component of the modular exponentiation process, which is
congruence relation de ≡ 1 (mod ϕ (n)). an essential RSA algorithm operation. Raising a base
number to the power of an exponent and calculating the
e is primarily understood as e=2^16 +1 = 65537. Certain result modulo a modulus are the steps involved in modular
applications opt for lesser values, such as e= 3, 5, 17, or 257 exponentiation. The formula for this operation is (c ≡ m ^
[8]. This is what we do to speed up encryption. The public e) mod n, where n is the modulus, e is the public exponent,
key is composed of the modulus (n) and the public exponent m is the plaintext, and c is the ciphertext. Here 32bit divider
(e). The private key is composed of the modulus (n) and is utilized in RSA cryptography (using FPGA) as:
private exponent
(d). Modular Exponentiation:
The modular exponentiation operation in RSA requires
multiple modular multiplications and divisions.
A 32-bit divider is used to efficiently compute the modular
divisions within the RSA algorithm.
FPGA Implementation:
FPGAs are programmable hardware devices that can be
configured to implement specific digital logic circuits.
The modular exponentiation operation, including the 32-bit
divider, is implemented in hardware on the FPGA.
Security Considerations:
Implementing RSA on an FPGA requires attention to
security considerations, such as protection against side-
channel attacks.
Fig 1.1 Key Generation

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The process of converting encrypted data, or ciphertext,
back into plaintext, or its original, readable form, is called
decryption. The RSA algorithm uses two keys—a public
key for encryption and a private key for decryption—and is
based on the mathematical characteristics of big prime
numbers. d.
Here's a step-by-step explanation of the decryption process
RSA:
Ciphertext Reception:
The recipient receives the ciphertext ‘C’ transmitted
securely over a communication channel. This ciphertext is
now safe and unrecognizable by any third party or any
intruder [13]. Thus, the result of encrypting the original
plaintext message using the recipient's public key.
Private Key Usage:
The recipient employs their private key ‘d’ for decryption.
Fig 1.3 32-Bit Divider Architecture The private key is generated as part of the RSA key
generation process and possesses the necessary
mathematical properties for reversing the encryption
MODULAR MULTIPLIER process.
A key element in accomplishing effective modular Modular Exponentiation:
exponentiation is the modular multiplier [10]. The creation Modular exponentiation is carried out by the recipient by
of RSA keys and the encryption and decryption procedures elevating the ciphertext c to the power of the private key 'd'
both depend on this action. modulo 'n'. The original plaintext message is effectively
The modular multiplier is important because it makes sure
recovered from the ciphertext through the use of modular
that every multiplication operation is carried out modulo n arithmetic's exponentiation mathematical property.
in the modular exponentiation equation, where "m" is the Result Validation:
plaintext, "e" is the exponent, and "n" is the modulus. After modular exponentiation, the recipient obtains the
Efficient Multiplication: decrypted plaintext message [14]. It is crucial to validate the
The modular multiplier performs the multiplication of two correctness of the decryption process by ensuring that the
numbers, typically the base m and the result from the recovered plaintext matches the original message [15] sent
previous modular multiplication step. This operation is by the sender.
conducted to minimize computational complexity.
Modular Reduction:
After multiplication, the result undergoes modular reduction V. RESULTS
by taking the remainder when divided by the modulus n. ENCRYPTION
This step prevents numerical overflow and keeps the result
within the appropriate range [0, n−1].
Iterative Process:
Starting with the least significant bit (LSB) and working its
way up to the most significant bit (MSB), the modular
multiplier loops over each bit of the exponent e. The
outcome is totaled at each stage.
Impact on RSA Performance:
The efficiency of the modular multiplier directly influences
the overall performance of RSA cryptography [11].
Key generation and encryption/decryption processes rely KEY GENERATION
heavily on modular exponentiation, making the modular
multiplier a critical factor.

III. DECRYPTION
Decryption in the RSA algorithm is a key process that
ensures secure communication by converting the ciphertext
back to the original plaintext with the help of the recipient’s
private key. This policy is especially important where
privacy is paramount, such as the transmission of sensitive
information over insecure networks. Understanding the
theoretical basis of RSA decryption provides insight into its
mathematical foundation and the security guarantee it
offers[12].

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16-BIT DIVIDER
VI . REFERENCES

[1] Cetin Kaya Koc, High-speed RSA algorithm, RSA


laboratories, version 2, 1994
[2] Perovic N.S; Popovic-Bozovic: "FPGA
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32-BIT DIVIDER [3] Sushanta Kumar Sahu, ManoranjanPradhan,
“FPGA Implementation of RSA Encryption
System”, International Journal of Computer
Applications (0975 – 8887), Volume 19– No.9,
April (2011)
[4] Lin X Sun L and Qu H, 2017 An efficient RSA-
based certificateless public key encryption scheme.
[5] https://www.slideshare.net/ijcncs/cryptosystem-an-
DECRYPTION implementation-of-rsa-using-verilog
[6] Ramzi A. Haraty, N . EI -Kassar and Bilal Shibaro,
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[7] Meng X and Zheng X, 2015 Cryptanalysis of RSA
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[8] Modular Arithmetic for RSA Cryptography.
[Courtesy:http://gtk.hopto.org:8089/MODULARRS
A.pdf]
[9] https://www.irjet.net/archives/V7/i9/IRJET-
V7I9160.pdf
[10] D. Boneh and H. Shacham, “Fast Variants of RSA”,
CryptoBytes, Vol. 5, No. 1, pp. 1-9, 2002
[11] Mohammad El-Hahidy, Danilo G. and Sevin J. K.,
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block cipher-MQQ, for FPGA Platforms", (2004),
eprint.iacr.org/2008/339.pdf
[12] G. C. Kessler, An Overview of Cryptography, Boca
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[13] Sushanta Kumar Sahu, ManoranjanPradhan,
"FPGA Implementation of RSA Encryption
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[14] Symeon (Simos) Xenitellis, “A guide to PKIs and
Open– source Implementations”, The Open–source
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[15] Md. AI i -AI-Mamun, Mohammad Motaharul I
slam, S . M. Mashihure Romman and A.H. Salah
Uddin Ahmad, " Performance Evaluation of Several
Efficient RSA Variants", IJC SN S International
Journal of Computer Science and Network Security,
8No.7, July (2008).

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