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CE 2704 - Digital Logic Design

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Dr. Ehsan Ali
Assumption University of Thailand
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ehsanali@au.edu
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Semester 2/2024
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 Contents

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1 Module 8 - Assignments Answers 2
1.1 Copyright Notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

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1.2 Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

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 Chapter 1

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Module 8 - Assignments Answers

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1.1 Copyright Notice

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This PDf file is generated by Dr. Ehsan Ali and contains the answers to all the assignments of mod-
ule 8 of CE2704 Digital Logic Design - academic semester 2/2024. The material in this PDF file is
copyrighted. and cannot be shared whatsoever to any third party or online websites, forums, etc.
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 1.2 Assignments
1. How does a Verilog model for a D-flip-flop handle treating reset as the highest priority input?
By listing the reset condition as the first item in an if/then statement. In this way, the reset condition
will always be evaluated first.

2. For a Verilog model of a D-flip-flop with a synchronous enable (EN), why isn’t EN listed in the
sensitivity list?

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Because EN is always treated as a synchronous signal so it is only evaluated when there is a
triggering edge of the clock.

3. For a Verilog model of a D-flip-flop with a synchronous enable (EN), what is the impact of listing

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EN in the sensitivity list?

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Listing EN in the sensitivity list will cause a transition on EN to trigger the process. Since the
only signals that can trigger a D-flip-flop are the clock and reset lines, EN will be OR’d with one
of these signals in order to trigger action in the D-flip-flop.

4. For a Verilog model of a D-flip-flop with a synchronous enable (EN), why is the behavior of the

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enable modeled using a nested if-else statement under the else clause handling the logic for the
clock edge input?
Listing EN in the sensitivity list will cause a transition on EN to trigger the process. Since the
only signals that can trigger a D-flip-flop are the clock and reset lines, EN will be OR’d with one
of these signals in order to trigger action in the D-flip-flop.
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5. What is the advantage of using parameters for the state when modeling a finite-state machine?
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You don’t need to worry about assigning the state codes, you instead allow the synthesizer to
assign them. This means you can design at a higher level of abstraction without worrying about
the lower-level details.
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6. What is the advantage of having to assign the state codes during the parameter declaration for the
state names when modeling a finite-state machine?
It gives you control over the exact state codes to assign the states during synthesis. This can be
advantageous when trying to optimize the design for a certain parameter. You also can change the
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encoding there.

7. When using the three-procedural block behavioral modeling approach for finite-state machines,
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does the next state logic block model combinational or sequential logic?
Combinational logic.

8. When using the three-procedural block behavioral modeling approach for finite-state machines,
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does the state memory block model combinational or sequential logic?

9. When using the three-procedural block behavioral modeling approach for finite-state machines,
does the output logic block model combinational or sequential logic?
Combinational logic.

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 10. When using the three-procedural block behavioral modeling approach for finite-state machines,
what inputs are listed in the sensitivity list of the next state logic block?
The current state and the inputs.

11. When using the three-procedural block behavioral modeling approach for finite-state machines,
what inputs are listed in the sensitivity list of the state memory block?
Clock and Reset.

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12. When using the three-procedural block behavioral modeling approach for finite-state machines,
what inputs are listed in the sensitivity list of the output logic block?
The current state and potentially the inputs.

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13. When using the three-procedural block behavioral modeling approach for finite-state machines,
how can the signals listed in the sensitivity list of the output logic block immediately indicate

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whether the FSM is a Mealy or a Moore machine?
If only the current state is listed in the sensitivity list, it is a Moore machine.

14. Why is it not a good design approach to combine the next state logic and output logic behavior
into a single-procedural block?
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Because the next state logic may be sensitive to inputs that are different from the output logic. If
one process is used, the circuitry synthesized may be sensitive to inputs that aren’t supposed to
influence particular outputs. This can lead to glitches in the outputs.

15. Design a Verilog behavioral model to implement the finite-state machine described by the state
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diagram in Fig. 1.23. Use the port definition provided in this figure for your design. Use the
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three-block approach to modeling FSMs described in this week for your design. Model the state
variables using parameters and encode the states in binary using the following state codes:
Start = "00" Midway = "01" Done = "10". As your answer include your both implementation
and simulation source code and functional simulation waveform.
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State Diagram:
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Design code:

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16. Design a Verilog behavioral model to implement the finite-state machine described by the state
diagram in Fig. 1.23. Use the port definition provided in this figure for your design. Use the
three-block approach to modeling FSMs described in this chapter for your design. Model the state
variables using parameters, and encode the states in one-hot using the following state codes:

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Start = "001", Midway = "010", Done = "100". As your answer include your both implemen-
tation and simulation source code and functional simulation waveform.
State Diagram:
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Design code:

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17. Design a Verilog behavioral model to implement the finite-state machine described by the state
diagram in Fig. 1.24. Use the port definition provided in this figure for your design. Use the
three-block approach to modeling FSMs described in this chapter for your design. Model the state
variables using parameters and encode the states in binary using the following state codes:

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S0 = "00", S1 = "01", S2 = "10", and S3 = "11". As your answer include your both implementa-
tion and simulation source code and functional simulation waveform.
State Diagram:
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Design code:

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Simulation waveform:
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18. Design a Verilog behavioral model to implement the finite-state machine described by the state
diagram in Fig. Fig. 1.24. Use the port definition provided in this figure for your design. Use the
three-block approach to modeling FSMs described in this chapter for your design. Model the state
variables using parameters and encode the states in one-hot using the following state codes:
S0 = "0001", S1 = "0010", S2 = "0100", and S3 = "1000". As your answer include your both
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implementation and simulation source code and functional simulation waveform.

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State Diagram:

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Design code:

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Simulation waveform:
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 19. Design a Verilog behavioral model for a 4-bit serial bit sequence detector similar to Example 2
in Section 1.2.1. Use the port definition provided in Fig. 1.25. Use the three-block approach to
modeling FSMs described in this chapter for your design. The input to your sequence detector
is called DIN and the output is called FOUND. Your detector will assert FOUND anytime there is
a 4-bit sequence of "0101". Model the states in this machine with parameters. Choose any state
encoding approach you wish. As your answer include your both implementation and simulation
source code and functional simulation waveform.

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State Diagram:

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Design code:

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Simulation waveform:

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20. Design a Verilog behavioral model for a 20-cent vending machine controller similar to Example 3
in Section 1.2.2. Use the port definition provided in Fig. 1.26. Use the three-block approach
to modeling FSMs described in this chapter for your design. Your controller will take in nickels
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and dimes and dispense a product anytime the customer has entered 20 cents. Your FSM has
two inputs, Nin and Din. Nin is asserted whenever the customer enters a nickel, while Din
is asserted anytime the customer enters a dime. Your FSM has two outputs, Dispense and
Change. Dispense is asserted anytime the customer has entered at least 20 cents and Change
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is asserted anytime the customer has entered more than 20 cents and needs a nickel in change.
Model the states in this machine with parameters. Choose any state encoding approach you wish.
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State Diagram:

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Design code:

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21. Design a Verilog behavioral model for a finite-state machine for a traffic light controller. Use the

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port definition provided in Fig. 1.27. This is the same problem we discussed before. This time,
you will implement the functionality using the behavioral modeling techniques presented in this

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week. Your FSM will control a traffic light at the intersection of a busy highway and a seldom
used side road. You will be designing the control signals for just the red, yellow, and green lights
facing the highway. Under normal conditions, the highway has a green light. The side road has car
detector that indicates when car pulls up by asserting a signal called CAR. When CAR is asserted,

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you will change the highway traffic light from green to yellow and then from yellow to red. Once
in the red position, a built-in timer will begin a countdown and provide your controller a signal
called TIMEOUT when 15 seconds has passed. Once TIMEOUT is asserted, you will change the
highway traffic light back to green. Your system will have three outputs GRN, YLW, and RED,
which control when the highway facing traffic lights are on (1 = ON, 0 = OFF). Model the states
in this machine with parameters. Choose any state encoding approach you wish.
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22. Design a Verilog behavioral model for a 16-bit, binary up counter using a single-procedural block.
The block diagram for the port definition is shown in Fig. 1.28.
Block Diagram:
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 23. Design a Verilog behavioral model for a 16-bit, binary up counter with enable and load using a
single-procedural block. The block diagram for the port definition is shown in Fig. 1.29.
Block Diagram:

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Design code:

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 24. In register transfer level modeling, how does the width of the register relate to the number of
D-flip-flops that will be synthesized?
Each bit within the register will result in one D-flip-flop being synthesized.

25. In register transfer level modeling, how is the synchronous data movement managed if all registers
are using the same clock?
The outputs of one register are routed to the inputs of other registers, typically through combina-

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tional logic circuitry that manipulates the data. Since all outputs are created at the same time and
there is a finite delay from the outputs to the inputs, there is sufficient delay to avoid violating the
setup requirements of the receiving register.

26. Design a Verilog RTL model of a 32-bit, synchronous register. The block diagram for the port

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definition is shown in Fig. 1.30. The register has a synchronous enable. The register should be
modeled using a single-procedural block.

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Block Diagram:

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Design code:
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 Simulation waveform:

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27. Design a Verilog RTL model of an 8-stage, 16-bit shift register. The block diagram for the port
definition is shown in Fig. 1.31. Each stage of the shift register will be provided as an output of the
system (A, B, C, D, E, F, G, and H). The shift register should be modeled using a single-procedural
block.
Block Diagram:
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 Design code:

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 28. Design a Verilog RTL model of the multi-drop bus topology in Fig. 1.32. Each of the 16-bit
registers (RegA, RegB, RegC, and RegD) will latch the contents of the 16-bit data bus if their
enable line is asserted. Each register should be modeled using an individual procedural block.
Block Diagram:

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Design code:

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