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CE 2704 - Digital Logic Design
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Dr. Ehsan Ali
Assumption University of Thailand
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ehsanali@au.edu
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Semester 2/2024
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Contents
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1 Module 5 - Assignments Answers 2
1.1 Copyright Notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
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1.2 Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
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Chapter 1
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Module 5 - Assignments Answers
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1.1 Copyright Notice
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This PDf file is generated by Dr. Ehsan Ali and contains the answers to all the assignments of mod-
ule 5 of CE2704 Digital Logic Design - academic semester 2/2024. The material in this PDF file is
copyrighted. and cannot be shared whatsoever to any third party or online websites, forums, etc.
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1.2 Assignments
1. Design a 4-to-16 one-hot decoder by hand. The block diagram and truth table for the decoder are
given below. Give the minimized logic expressions for each output (i.e., F0 , F1 ,... , F15 ) and the
full logic diagram for the system.
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2. Design a Verilog model for a 4-to-16 one-hot decoder using continuous assignment and gate-
level primitives. Use the module port definition given in Listing. 1.8 and submit your functional
simulation waveform obtained from Xilinx ISE 14.7 that ensures your design is correct.
Answer:
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3. Design a Verilog model for a 4-to-16 one-hot decoder using continuous assignment and logical op-
erators. Use the module port definition given in Listing. 1.8 and submit your functional simulation
waveform obtained from Xilinx ISE 14.7 that ensures your design is correct.
Answer:
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4. Design a Verilog model for a 4-to-16 one-hot decoder using continuous assignment and condi-
tional operators. Use the module port definition given in Listing. 1.8 and submit your functional
simulation waveform obtained from Xilinx ISE 14.7 that ensures your design is correct.
Answer:
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5. Design a 4-input, 7-segment HEX character decoder by hand. The system has four inputs called
A, B, C, and D. The system has seven outputs called Fa , Fb , Fc , Fd , Fe , Ff , and Fg . These
outputs drive the individual LEDs within the display. A logic 1 on an output corresponds to the
LED being ON. The display will show the HEX characters 0-9, A, b, c, d, E, and F corresponding
to the 4-bit input code on A. A template for creating the truth tables for this system is provided in
Fig. 1.14. Provide the minimized logic expressions for each of the seven outputs and the overall
logic diagram for the decoder.
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Answer:
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Part 2 K-maps are omitted, but you must have them in your answer. Check your K-map against
the below equations.
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6. Design a Verilog model for a 4-input, 7-segment HEX character decoder using continuous assign-
ment and logical operators. Use the module port definition given in Listing 1.9 for your design
and submit your functional simulation waveform obtained from Xilinx ISE 14.7 that ensures your
design is correct. The system has a 4-bit input vector called ABCD and a 7-bit output vector called
F. The individual scalars within the output vector (i.e., F[6:0]) correspond to the character
display segments a, b, c, d, e, f, and g, respectively. A logic 1 on an output corresponds to the
LED being ON. The display will show the HEX characters 0-9, A, b, c, d, E, and F corresponding
to the 4-bit input code on A. A template for creating the truth table is provided in Fig. 1.14. The
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signals in this table correspond to the ports in this problem as follows: Fa = F(6), Fb = F(5), Fc =
F(4), Fd = F(3), Fe = F(2), Ff = F(1), and Fg = F(0).
Answer:
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7. Design an 8-to-3 binary encoder by hand. The block diagram and truth table for the encoder are
given in Fig. 1.15. Give the logic expressions for each output and the full logic diagram for the
system.
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8. Design a Verilog model for an 8-to-3 binary encoder using continuous assignment and gate-level
primitives. Use the module port definition given in Listing 1.10 and submit your functional simu-
lation waveform obtained from Xilinx ISE 14.7 that ensures your design is correct.
Answer:
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9. Design a Verilog model for an 8-to-3 binary encoder continuous assignment and logical opera-
tors. Use the module port definition given in Listing 1.10 and submit your functional simulation
waveform obtained from Xilinx ISE 14.7 that ensures your design is correct.
Answer:
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10. Design a Verilog model for an 8-to-3 binary encoder continuous assignment and conditional oper-
ators. Use the module port definition given in Listing 1.10 and submit your functional simulation
waveform obtained from Xilinx ISE 14.7 that ensures your design is correct.
Answer:
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11. Design an 8-to-1 multiplexer by hand. The block diagram and truth table for the multiplexer are
given in Fig. 1.16. Give the minimized logic expressions for the output and the full logic diagram
for the system.
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12. Design a Verilog model for an 8-to-1 multiplexer using continuous assignment and gate-level prim-
itives. Use the module port definition given in Listing 1.11 and submit your functional simulation
waveform obtained from Xilinx ISE 14.7 that ensures your design is correct.
Answer:
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13. Design a Verilog model for an 8-to-1 multiplexer continuous assignment and logical operators. Use
the module port definition given in Listing 1.11 and submit your functional simulation waveform
obtained from Xilinx ISE 14.7 that ensures your design is correct.
Answer:
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14. Design a Verilog model for an 8-to-1 multiplexer continuous assignment and conditional opera-
tors. Use the module port definition given in Listing 1.11 and submit your functional simulation
waveform obtained from Xilinx ISE 14.7 that ensures your design is correct.
Answer:
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15. Design a 1-to-8 demultiplexer by hand. The block diagram and truth table for the demultiplexer
are given in Fig. 1.17. Give the minimized logic expressions for each output and the full logic
diagram for the system.
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16. Design a Verilog model for a 1-to-8 demultiplexer using continuous assignment and gate-level
primitives. Use the module port definition given in Listing 1.12 for your design.
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17. Design a Verilog model for a 1-to-8 demultiplexer using continuous assignment and logical op-
erators. Use the module port definition given in Listing 1.12 for your design and submit your
functional simulation waveform obtained from Xilinx ISE 14.7 that ensures your design is correct.
Answer:
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18. Design a Verilog model for a 1-to-8 demultiplexer using continuous assignment and conditional
operators. Use the module port definition given in Listing 1.12 for your design and submit your
functional simulation waveform obtained from Xilinx ISE 14.7 that ensures your design is correct.
Answer:
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