EE 214 Project Report Fall 2007 A 3V Gain-Boosted Fast Settling 4.

95 mW 90 dB Dynamic Range CMOS OTA design Saihua Lin

Outline: 1, Design Approach and Decisions 2, OTA Schematics 3, Design process and Equations 4, Simulation Plots

* Modified from Saihua Lin, Hai Wei, A 3V Gain-Boosted Fast Settling 5.52 mW 91.09 dB Dynamic Range CMOS OTA design, EE214 project report, fall 2007

1, Design Approach and Decisions The static error of 0.025% requires the open loop gain to be larger than about 16000. To satisfy this requirement, we need to build an amplifier with at least 3 transistor stages in its signal path or by using gain-boosting techniques. For those with only 2 transistor stages in path, it is hard to meet the specs. For example, we have tried to modify the project example to meet the spec by using L = 1.1 m for PMOS transistors and L = 0.65 m for NMOS transistors. However, the static error is still 0.05% with power 27.56 mW and settling time 39.5 ns. There are mainly two options to implement the desired OTA in order to meet the specs. One is the two-stage circuit with the first stage telescopic to provide high gain and the second stage common source to provide high swing. The other one is the gain boosted OTA. The other topologies such as folded cascode OTA can also be considered. However, generally it is worse than the two-stage OTA in terms of output swing. It is still worse than the gain boosted OTA in terms of power. Table 1, Amplifier comparison between two-stage circuit and gain boosted circuit Amplifier Topology Comparison Topology two-stage gain boost Gain gmro^3 gmro^3-4 Output Swing VDD-2Vdsat VDD-5Vdsat NF >1.3 ~1.3 DR Large Small Procedure Easy Complex Power Large Small Linear Settling Fast Slow

Table 1 summarizes our observations of these two topologies. Two-stage amplifier design is easy especially we can use MATHCAD, MATLAB, and HSPICE extensively to find the minimum power consumption point without much SPICE Monkeying. If offers a large output swing and thus the dynamic range can be made quite high. In addition, the linear settling speed is generally faster than the gain boosted OTA. This is an important consideration though many designers may ignore [1]. For 0.025% dynamic settling error, the linear settling time of the two-stage amplifier with 75 degree phase margin is 41% smaller than that of the gain boosted amplifier whose phase margin is typically around 90 degree [2]. If slew is not considered, this means the current of the main amplifier of the gain boosted circuit has to be increased by 2.78. From this standpoint, the two-stage amplifier is still comparable to or even better than the gain boosted amplifier in terms of power consumption. However, in reality slew does happen and even plays a very important role for power reduction. We can find that with more slew, the total power can be reduced more, thereby making the faster linear settling speed effect of the two-stage OTA negligible. As a result, the drawback of two-stage amplifier is still the large power consumption problem. Compared to the gain boosted telescopic amplifier, it has 4 current legs while the gain boosted telescopic amplifier has only 2 current legs. As a result, the power of two-stage amplifier is often larger than the gain boosted amplifier. Actually we have designed a two-stage OTA that meets all the specifications (DR = 90.08 dB, settling time = 39.94 ns, settling accuracy < 0.01%). The power consumption is as large as 12.17 mW. We can further show that the minimum power consumption of two-stage OTA is around 12 mW qualitatively. Yet gain boosted amplifier design is complex. We have to manage the inherent doublet [3][4] and the optimization procedure is not quite clear. As a result, we may end up with lots of manual circuit tweaking. In this project, however, we still chose to design a gain boosted OTA because of low power consideration. Since the gain-boosting techniques decouples the DC gain and frequency response of the amplifier. It allows us to attain very high gain while maintaining the bandwidth, which is crucial to the small settling time. Finally, by combining MATHCAD optimization and circuit tweaking, we achieved a 5.52 mW gain boosted OTA in nominal corner. We can further show qualitatively that the minimum power consumption is around 6 mW under single pole approximation.

2, OTA Schematics
29/0.35 M=5 Mbpa gmid a,b=10.3 29/0.35 M=5 Mbpb gmid=9.5Mbpc 29/0.35 29/0.35 Mcpc gmid=9.5 29/0.35 M0cc gmid=11.2 142.3A 87.13A 85.9A M0f gmid=11.4 29/0.35 gmid=10.3 M0c M0d gmid=3.2 29/0.35 6/0.35 500k
Well resistance 10k/squar e

290/0.35 Mcpa

+ P+ B

10p

290/0.35 Mcpb

gmid=13.97 gmid=15.4 Mcna 123/0.35

gmid=13.97 gmid=15.4

459A

N +B +

Mcnb 123/0.35

1.5V

gmid=9.3 Mcnc

12/0.35 80A 20/0.35 M1c Mbnc M0b gmid=12.12 19/0.5 M0e

500k

10p

250/0.35 gmid a,b=17.75 M1a

250/0.35 M1b

gmid=4.6

gmid=12.18

Mbn gmid=12.18 19/0.5 M=10 19/0.5

M0a 19/0.5

gmid=12.06 19/0.5

gmid=12.4

P-Booster
Mpbpa 29/0.35 gmid=10. 3 Mpcpa Mpbpb 29/0.35 gmid=10. 3 Mpcpb Mnbpa 14.5/0.35 gmid=10. 3 Mncpa 11.2/0.35 gmid=10.5

N-Booster
Mnbpb gmid=10. 1 Mn0a 29/0.35 Mn0b 82.8A 9.6/0.35 gmid=7.5 44.5A Mn1a,b gmid=16. 2 44/0.35 gmid=16. 2 44/0.35 14.5/0.35 gmid=10. 3 Mncpb 11.2/0.35 gmid=10.5

26/0.35 26/0.35 22.5/0.35 22.5/0.35 Mp1a,b gmid=13.6 gmid=13.6 gmid=18.8 gmid=18.8 Mpcna 9.6/0.35 gmid=15.1 9.6/0.35 gmid=11.5 38.1A Mp0a 75.8A gmid=12.4 Mp0b 19/0.5 Mpcnb 9.6/0.35 gmid=15.1

Mncna 5/0.35 gmid=10.6

Mncnb 5/0.35 gmid=10.6

9.5/0.5 gmid=12.4 Mpbna

9.5/0.5 gmid=12.4 Mpbnb

19/0.5 gmid=12.4 Mnbna

19/0.5 Mnbnb gmid=12.4

CMFB circuits are not shown. For the main amplifier, g is 35 mS ; for the booster amplifiers, g is 1.06 mS. They are designed not to pull any current from the ground. The maximum current mirror ratio is 17 The maximum gm/id is 18.8, occurring in P-Booster differential pair Use only NMOS, PMOS, ideal capacitors, ideal resistors, single current source, and controlled sources in CMFB circuit. Vocdes is generated by resistor divider like in Flash ADC way.

3, Design process and Equations 3.1 Specification and Considerations In this section, we give out the project specification and our design considerations on the OTA design. Prepare .bat or script files that are used for HSPICE files and MATLAB files respectively. This would help accelerate the simulation procedure. Prepare MATHCAD tables and all kinds of technology related functions. gm/ID > 20 is assumed to be impractical throughout the design because then the circuit would be too sensitive to process variations.
Reference:N:\mos\tables.xmcd

Dynamic Range Supply voltage Close Loop Gain

DRdB := 90

Static Settling Error Dynamic Settling Error Settling Time Total Settling Error Noise factor

s := 0.025% d := 0.025%
ts := 40 10
9

VDD := 3V Acl := 1
Tr := 300K 23 J k B := 1.38 10 K

Boltzman Constant

tot := s + d 2 := 3

3.2 Dynamic Range Consideration Here, we choose the maximum output swing is 2.0 V. Its reasonable for a telescopic gain-boosted circuit since there are 5 transistors stacking on one vdd to ground path.
DRdB

Dynamic Range Output swing Noise Power

DR := 10

10

DR = 1 10

Vomax := 2V
Pn := Ps DR

Signal Power
Pn = 4.472 10
5

Ps := 0.5 Vomax

3.3 Capacitances In order to minimize noise effect of the active loads, the Vdsat,loads/Vdsat,in should be maximized. However, this value can not be too large because of output swing limitation. In telescopic gain-boosted circuit, the output swing is very cherishing.
Suppose Vdsat1 := 100mV Vdsat2 := 300mV 8 1 kB Tr CLmin := 3 est Pn

est = 0.333
CLmin = 1.104 10
11

Vdsat1 1 kB Tr Ntot := 2 + 1 Vdsat2 est CL

Considering the noise contribution of boost amplifier and cascode transistor, we set CL = 12.5 pF to give margin. Then the feedback capacitance is chosen as 5 pF by considering the DR margin and feed forward effect: Vodstep 1 1 should be small = CL / C f 1 + CL / C f Vidstep Cin 1+ + C f 1 + CL / C f We can calculate the loop gain is 4000 and the open loop gain is about 16000. This means we need one stage gain about 178 in signal path. Since small length can offer higher speed, therefore in the main amplifier the input differential pair and the cascode transistors are chosen to have the minimum lengths. Although this would reduce

the intrinsic gain, the gain boost amplifier can effectively cope with this not-enough-gain problem (~gmro^4). 3.4 Main Stage Current Selection This would be the most important part to design a low power gain boosted OTA. By using the equation
ts = Vxstep 2.8 /( g m / I D ) ln( d ) we can derive: for gain boosted circuit single pole analysis

SR
ID =

ln ( d ) 1 Vxstep 2.8 / ( g m / I D ) CLeff C ( g m / I D ) Leff ts 2

ID =

ln ( d ) 1 Vxstep 2.8 / ( g m / I D ) Cc 0.574 Cc for two-stage circuit (PM = 75 degree) 2 ( gm / I D ) ts

By choosing gm/ID in the range 15-20, -3 x 10 3 we can find the minimum current required 2.9 2.8 gain-boosted OTA by gain boosted circuit is about 700 A. For 2.7 2.6 two-stage OTA two-stage circuit, the corresponding 2.5 2.4 2.3 minimum current is about 780 A. The 2.2 2.1 second stage current is about 800 2 1.9 A(1+CLeff/Cc)=1.13 mA. So the minimum 1.8 1.7 1.6 power consumption for two-stage OTA 1.5 1.4 should be about 12 mW. This prediction is 1.3 1.2 very close to our MATHCAD optimization 1.1 1 and final implementation of the two-stage 0.9 0.8 0.7 amplifier. So we can predict that the 0.6 0.5 minimum power of the gain boosted circuit 0 5 10 15 20 25 under single pole analysis is only around 6 gm/id mW, half of that of the two-stage circuit. Suppose ID is 750 A, and choose the different gm/id or Vdsat to satisfy the output swing limitation:
Current (A)

30

Active Load 210 mV, gmid=9.5 PMOS cascode 167 mV, gmid=12

W 4 := W3 :=

pidwfuc Lp , gmid4 ID 12 pidwfuc Lp , V

ID

W 4 = 1.493 10
W3 = 2.794 10

NMOS cascode 150 mV, gmid=13

W2 :=

W2 = 1.297 10

Input pair 120 mV, gmid=16

W 1 :=

nidwfuc Ln , gmid1 ID nidwfuc 0.5m,

ID

)
V

W 1 = 2.416 10

Tail current source 210 mV, gmid=9.5

W5 := 2

9.5

W5 = 1.972 10

Similarly we can calculate all the other width and length by using MATHCAD functions and lookup tables.

3.5 Settling Time Consideration and Booster Decision

tslew :=

2.8 Vxstep gmid1 2 ID CLeff

tslew = 1.954 10
ln d

Vxstep = 1.114V
7 1 fc = 6.453 10 s

tlin := 4010

s tslew

fc :=

( )

2tlin

For booster design, we choose folded cascode differential pair circuit because it can provide large common mode input range. In addition, since the local feedback can introduce doublet effect, the bandwidth of the amplifier should be optimized according to u , main booster p 2, main [3]. 3.6 Common Feed Back Consideration The CMFB unity-gain bandwidth should be A times larger than the differential unit gain bandwidth. We can derive: gmcfb>=A*2**gm1, where A is a coefficient and is generally larger than 0.5. In the final version, we choose gmcfb=17 mS (corresponding to A = 2.4, PM=88) for the main amplifier, gmcfb=0.725 mS for the booster amplifiers. With a large A, the common mode output voltage can be settled very fast. However, A can not be too large. Otherwise, the phase margin will not be enough, thereby causing ringing effect (equation see corner analysis part). 3.7 Performance Summary Performance parameter ID1(A) DR (dB) at Vomax PM (degree) Loop gain Unit gain bandwidth fc(MHz) Total output noise (V) Settling time (ns) Static Settling accuracy Power without bias (mW) Total Power (mW) First Run* 812 92.59 87.96 15217 68.44 34.86 37.86 <0.01% 7.12 8.95 Hand 1st 750 90 90 >4000 64.5 44.7 40 0.025% 6.3 Error of first run 8.27% 2.88% -2.27% 6.1% -22.01% -5.35% 13.2% Final Run** 459 90.01 87.8 20451 39.08 37.95 38.65 <0.01% 3.76 4.95

* First run means we implement the circuit according to the above W/L and I parameters without any tweaking ** Final run means we reduce the bias current to reduce power(this implies gm/id of transistors can be increased) The reason why the ID1 and DR are larger in the first run is understandable. This is due to channel length modulation and our over selection of the load capacitance (40% larger than minimum). As a result, the total noise is 34.86 V, 22% smaller than the initial calculation. This also implies the cascode transistor and the gain boosting amplifiers contribute some noise. From the table we can see fc is 6.1% larger than the calculation. This is mainly due to the current increase of the differential pair (8.27% increases) and the W/L increase (we choose 250/0.35, 4.2% larger than calculated 241.6/0.35). As a result, the linear settling time is smaller than 40 ns (5.35% reduction). Another reason why the linear settling time is reduced from the calculation is the effect of the non-dominant pole. Since the phase margin is 87.96 degree, the linear settling time speed up is 0.967. Thus linear settling time can be reduced by 3.3%. Finally, the three methods to obtain an ultra low power OTA used are: 1, use relatively large gm/ID; 2, enhance slew settling time; 3, optimize the common mode loop effect.

4, Differential AC loop frequency Response

fc =39.08MHz, PM=87.80deg, T0=20451

Magnitude [dB]

50

-50 10 f [MHz] 0 Phase [degrees] -50 -100 -150 -200

10 f [MHz]

5, Vod Response and Settling Time

1500 Vod [mV] 1000 500 0 0

10

20

30 Time [ns]

40

50

es=-0.00%, ts=38.65ns 0.05 Error [%]

-0.05 34 36 38 40 Time [ns] 42

6, Common Mode Output and Differential Voltage and Current

1510 1508 1506 1504 1502 0 1000

Voc [mV]

10

20

30 Time [ns]

40

50

Vid [mV]

500 0 0

10

20

30 Time [ns]

40

50

I od [mA]

1
slew

Linear settling

0.5 0 0

10

20

30 Time [ns]

40

50

7, Noise Performance

10 PSD [V2/Hz]

-15

10

-20

10

10

10

f [Hz] Integral=37.95uVrms, DR=90.01dB (for Vodmax=1.70V) Sqrt(Integral) [Vrms] 40 30 20 10 0 10

10 f [Hz]

8, Output Range

x 10

Avo0=51.25k, Avo30=35.87k, Vod30=2.158V

Vod/Vsd [V/V]

0 -3 -2 -1 0 Vod [V] 1 2 3

9, Corner Analysis Performance parameter ID1(A) DR (dB) at Vomax=1.9 PM (degree) Loop gain Open loop gain at Vod=0 (10 ) Unit gain bandwidth fc(MHz) Total noise (V) Settling time (ns) Static settling accuracy Total Power (mW)
3

Nominal 459 90.01 87.8 20451 51.25 39.08 37.95 38.65 <0.01% 4.95

Slow,125 451.4 88.58 87.95 19532 54.86 29.6 44.75 62.98 <0.01% 4.84

Error (%) -1.6558 -1.5887 0.1708 -4.4937 7.0439 -24.2579 17.9183 62.9495 -2.2222

Fast, 0 475 90.41 87.7 15038 34.44 45.53 36.26 50.48 <0.01% 5.17

Error (%) 3.4858 0.4444 -0.1139 -26.4681 -32.8000 16.5046 -4.4532 30.6080 4.4444

From above table we can find in fast corner and slow corner, the settling time increased largely from the nominal corner. This may due to 1: corner effect (process variation effect); 2, the doublet effect; 3 the common mode feedback effect. We first investigate the common mode feedback effect. In nominal corner, the gm of the input differential pair is 8.15 mS and the main stage common mode feedback g is 35 mS, so
g mcfb 2 g m1
4CL g m1 1 5.36 , PM = arctan 2C + C db , bn + C gd , bn g mcfb gs1 = 89

In fast corner, this factor is reduced to 4.6 and in slow corner this factor is increased to 7.2 (89 degree). So we can see clearly that this factor is large enough in slow corner. This implies the common mode feedback circuit should have not much impact on the time response. The figure shown below confirms our guess, i.e. there is no more ringing on Voc. So we have to consider another reason: the corner effect. This means the transistor parameters are different in different corners (process variations), like mobility, threshold voltage etc. By using .OP analysis, we find that the tail current source of the main amplifier is in linear region. In addition, since the unit gain bandwidth is also low compared to the nominal corner, the linear settling time is increased and the slew time is reduced. As a result, the total settling time is increased.
Slow corner
Voc [mV]
1510 1505 0 1000 500 0 0 20 40 60 80 20 40 60 80

Slow corner

Vod [mV]

1000

Time [ns] es =-0.00%, t s =62.98ns Error [%]

Vid [mV]

20

40

60

80

Time [ns]

Time [ns] Iod [mA]

0 -0.05 58 60 62 64 66

Time [ns]

Time [ns]

In order to solve/mitigate this problem, it would be better to design a CMOS circuit that provides the input common mode voltage so that the input common mode voltage can change corresponding to different corners. As

a result, the input differential pair and the tail current source transistor can operate in the active region. When turning to the fast corner analysis, the above analysis is not true since all the transistors operates correctly and the unit gain bandwidth is larger than that in the nominal corner. The common feedback loop bandwidth is also large enough. Since gm input is larger, the phase margin is also larger (about 89 degree). However, from the transient waveform, we can find there is overshoot. This is the reason why the settling time is increased.
Fast corner

Fast corner Voc [mV]

Vod [mV]

1000

Time [ns] es =-0.01%, ts =50.84ns Error [%]

Vid [mV]

20

40

60

1000 500 0 0 20

Time [ns]

40

60

Time [ns] Iod [mA]

0 -0.05

1 0.5 0 0 20 40 60

Time [ns]

Time [ns]

The reason can be the pole-zero double effect. As has been analyzed in [2][3], a pole-zero doublet can degrade the settling performance and can also cause overshoot. In order to solve this problem, we can add compensation capacitances to push the doublet frequency beyond the close-loop dominant pole frequency of the amplifier. So

u , main booster p 2, main . This technique is originally proposed by K. Bult and G. Geelen [4].
From the above table, we can also find that the dynamic range does not satisfy the spec in slow corner situation where the noise is increased by 17.9%. Given the expression:

Vdsat1 1 kB Tr Ntot := 2 + 1 Vdsat2 est CL

10, Comments and Conclusion In this project, we have tried three structures and implemented a gain-boosted OTA which satisfies all the specs in 0.35 m CMOS technology with 3 V supply for project conclusion. The power is only 4.95 mW in nominal corner by HSPICE simulation, with the core amplifier power 3.76 mW and bias power 1.18 mW respectively. The settling time is 38.65 ns and the dynamic range is 90.01 dB with an input equals to 1.7V. Although there is still room to reduce power, we try to over design a bit to sustain performance in other corners. The three methods to obtain an ultra low power OTA used in this project are: 1, use relatively large gm/ID; 2, enhance slew settling time; 3, optimize the common mode loop effect. There are several issues which should be addressed in real design. The first thing is that the design should meet all the specs in all the fast/slow/nominal cases. In this project, we dont need to meet these specifications. The second thing is that the bandwidth of the common mode loop is larger than the differential signal path in this project to improve the settling time. In [2], it is said that the bandwidth of the common mode loop is about 30% of the differential bandwidth, so A should be 0.3. However, we think this is not a concrete rule that every design has to follow. By using our analysis and the PM equation, it is quite safe if A is chosen large because we have a relatively large CL here. The parasitic capacitance is just in the range of hundreds of fF. So we dont have to worry much about that. In fact, we have designed several versions of circuit with different A: Circuit parameter 1 2 3 A 2.4 1.58 0.56 Settling time (ns) 39.51 37.96 39.74 DR (dB) 91.09 91.61 92.26 Power (mW) 5.52 6.06 6.29

The third thing is that PSRR, CMRR are not calculated in this project. However, in real design these specifications are also very important. PMOS input pair helps to improve CMRR but in this design, due to speed and power efficiency considerations, we use NMOS input pair in our first stage. We also use high swing bias circuit in this amplifier design by using Magic Battery. This would help improve PSRR. Again, since PSRR is not considered, we just design a resistive divider voltage reference for Vocdes. It is sensitive to VDD variation. Another thing to note is that throughout the design, we have submitted lots of times because we initially found the results given by the server are sometimes different from ours. After many times of try, we find the reason is that we used HSPICE200609 on PC and the server is using HSPICE200102. When doing transient simulation, HSPICE200102 in server gives more data points than HSPICE200609 and as a result the transient simulation results are different.

11, References: 1, Jason S. and Anshi L., A low power two-stage telescopic amplifer with 90 dB dynamic range and 200 ns settling time, UC Berkeley EE240 Project Report, 2004 2, Boris Murmann, EE214 Lecture Notes, Stanford University 3, Yun Chiu, Ken Wojciechowski, A gain-boosted 90-dB dynamic range fast settling OTA with 7.8 mW power consumption, UC Berkeley EE240 Final Project Report, 2000 4, K. Bult and G. Geelen, The CMOS gain-boosting technique, Analog Integrated Circuits and Signal Processing, vol. 1, no. 2, Oct. 1991, pp. 119-135.