Scribd Logo
Upload

Welcome to Scribd!

  • 86 views

    ECE 301 - Digital Electronics: Sequential Logic Circuits: FSM Design

    Uploaded by

    Suman Bhardwaj
    The document discusses finite state machine (FSM) design using Moore machines. It provides procedures for FSM design, examples of sequence detectors that detect patterns in input data, and state diagrams and tables for FSM examples that detect various patterns.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd

    ECE 301 - Digital Electronics: Sequential Logic Circuits: FSM Design

    Uploaded by

    Suman Bhardwaj
    86 views27 pages
    The document discusses finite state machine (FSM) design using Moore machines. It provides procedures for FSM design, examples of sequence detectors that detect patterns in input data, and state diagrams and tables for FSM examples that detect various patterns.

    Original Description:

    ppt

    Original Title

    Lecture 18

    Copyright

    © Attribution Non-Commercial (BY-NC)

    Available Formats

    PPT, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    The document discusses finite state machine (FSM) design using Moore machines. It provides procedures for FSM design, examples of sequence detectors that detect patterns in input data, and state diagrams and tables for FSM examples that detect various patterns.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    86 views27 pages

    ECE 301 - Digital Electronics: Sequential Logic Circuits: FSM Design

    Uploaded by

    Suman Bhardwaj
    The document discusses finite state machine (FSM) design using Moore machines. It provides procedures for FSM design, examples of sequence detectors that detect patterns in input data, and state diagrams and tables for FSM examples that detect various patterns.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    You are on page 1of 27

    ECE 301 Digital Electronics

    Sequential Logic Circuits: FSM Design


    (Lecture #18)

    FSM Design: Procedure


    Understand specifications Derive state diagram Create state table

    Perform state minimization (if necessary)


    Encode states (state assignment) Create state-assigned table Select type of Flip-Flop to use Determine Flip-Flop input equations and FSM output equation(s) Draw logic diagram
    ECE 301 - Digital Electronics 2

    FSM Design

    Moore Machines

    ECE 301 - Digital Electronics

    FSM Design (Moore)


    Example:
    Design a FSM that detects a sequence of three or more consecutive ones on an input bit stream. The FSM should output a 1 when the sequence is detected, and a 0 otherwise.
    A circuit that detects the occurrence of a particular pattern on its input is referred to as a sequence detector.

    ECE 301 - Digital Electronics

    FSM Design: Example (Moore)

    Input:

    011101011011101

    Output:

    000100000000100

    ECE 301 - Digital Electronics

    FSM Design: Example (Moore)

    State Diagram

    ECE 301 - Digital Electronics

    FSM Design: Example (Moore)

    QA

    QB

    QA+

    QB+

    State Table
    ECE 301 - Digital Electronics 7

    FSM Design: Example (Moore)

    The choice of Flip-Flop determines the complexity of the combinational logic required in the design of the state machine.

    Each type of Flip-Flop has a unique characteristic equation.

    SR Flip-Flop

    JK Flip-Flop

    Q+ = S + R'.Q

    Q+ = J.Q' + K'.Q

    D Flip-Flop

    T Flip-Flop

    Q+ = D

    Q+ = T '.Q + T.Q'

    ECE 301 - Digital Electronics

    FSM Design (Moore)

    Synthesis using D Flip-Flops


    (Q+ = D)

    ECE 301 - Digital Electronics

    FSM Design: Example (Moore)


    Flip-Flop Input

    QA

    QB

    Q A+

    QB+

    DA

    DB

    Q+ = D
    next state flip-flop input

    ECE 301 - Digital Electronics

    10

    FSM Design: Example (Moore)

    ECE 301 - Digital Electronics

    11

    FSM Design: Example (Moore)


    QA

    QB Q'B

    ECE 301 - Digital Electronics

    12

    FSM Design (Moore)

    Synthesis using JK Flip-Flops


    (Q+ = J.Q' + K'.Q)

    ECE 301 - Digital Electronics

    13

    FSM Design: Example (Moore)

    Excitation Table

    ECE 301 - Digital Electronics

    14

    FSM Design: Example (Moore)


    QA QB QA+ QB+

    Q+ = J.Q' + K'.Q
    next state flip-flop inputs

    ECE 301 - Digital Electronics

    15

    FSM Design: Example (Moore)

    ECE 301 - Digital Electronics

    16

    FSM Design: Example (Moore)


    QA

    Q'A

    QB

    Q'B

    ECE 301 - Digital Electronics

    17

    FSM Design (Moore)


    Example:
    Design a Finite State Machine (FSM) that meets the following specifications:
    1. The circuit has one input, w, and one output, z. 2. All changes in the circuit occur on the positive edge of the clock. 3. The output z is equal to 1 if the pattern 101 is detected on the input w. Otherwise, the value of z is equal to 0. Overlapping sequences should not be detected.
    This is another example of a sequence detector.
    ECE 301 - Digital Electronics 18

    FSM Design: Example (Moore)

    Input (w): 0 0 0 1 0 1 0 1 1 0 1 1 0 1 1

    Output (z): 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0

    ECE 301 - Digital Electronics

    19

    FSM Design: Example (Moore)


    Start State

    State Diagram
    End State

    ECE 301 - Digital Electronics

    20

    FSM Design (Moore)


    Example:
    Design a Finite State Machine (FSM) that meets the following specifications:
    1. The circuit has one input, w, and one output, z. 2. All changes in the circuit occur on the positive edge of the clock. 3. The output z is equal to 1 if the pattern 101 is detected on the input w. Otherwise, the value of z is equal to 0. Overlapping sequences should be detected.
    This is another example of a sequence detector.
    ECE 301 - Digital Electronics 21

    FSM Design: Example (Moore)

    Input (w): 0 0 0 1 0 1 0 1 1 0 1 1 0 1 1

    Output (z): 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0

    ECE 301 - Digital Electronics

    22

    FSM Design: Example (Moore)


    Start State

    State Diagram
    End State

    ECE 301 - Digital Electronics

    23

    FSM Design (Moore)


    Example:
    Design a Finite State Machine (FSM) that meets the following specifications:
    1. The circuit has one input, w, and one output, z. 2. All changes in the circuit occur on the positive edge of the clock. 3. The output z is equal to 1 if the pattern 110 or the pattern 010 is detected on the input w. Otherwise, the value of z is equal to 0. Overlapping sequences should be detected.
    This is example of a sequence detector that can detect 2 sequences.
    ECE 301 - Digital Electronics 24

    FSM Design: Example (Moore)

    Input (w): 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1

    Output (z): 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0

    ECE 301 - Digital Electronics

    25

    FSM Design: Example (Moore)

    State Diagram

    ECE 301 - Digital Electronics

    26

    Acknowledgments

    The slides used in this lecture were taken, with permission, from those provided by Pearson Prentice Hall for Digital Design (4th Edition). They are the property of and are copyrighted by Pearson Education.

    ECE 301 - Digital Electronics

    27

    You might also like