Seminar Presentation BLDC
Seminar Presentation BLDC
Seminar Presentation BLDC
Outline
Abstract INTRODUCTION BRUSHLESS DC MOTOR DRIVE
STRATEGIES DIGITAL PWM CONTROL OF BLDC DRIVES CONTROLLER DESIGN DESCRIPTION OF EXPERIMENTAL SETUP SIMULATION RESULTS AND EXPERIMENTAL VERIFICATION CONCLUSION
Abstract
Development of advanced motor drives has yielded
refrigerators and air conditioning systems use conventional motor drive technology.
reluctant to replace the conventional motor drives with the advanced motor drives (BLDC) due to their higher cost.
Experimental verification is carried out using fieldprogrammable gate arrays to validate the claims presented.
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INTRODUCTION
An ELECTRIC motor is defined as a transducer that
BLDC system is only allowed to operate at a low duty (DL) or a high duty (DH).
In addition, this technique utilizes only one current sensor in
the dc link. This helps reduce the cost and complexity of motor control hardware.
Computer simulations and experimental results are presented
shown in Fig. 1.
constant output torque, current is driven through a motor winding during the flat portion of the back-EMF waveform. shown in Fig. 2.
Fig. 2. Back EMF and phase current variation with rotor electrical angle.
required for commutation can be put in the form of a state table as shown in Table I.
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verification of a novel constant-frequency digital PWM controller which has been designed for a BLDC motor drive system. shown in Fig. 6.
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observer. Fig. 7 shows the proposed digital controller. Fig. 8 shows the complete block diagram of the motor drive system.
Fig. 8. Block diagram for digital PWM control for a BLDC motor drive system.
limit.
The minimum value of Ilimit decides the steady-state error.
The proportional constant K for a desired speed ripple can be
calculated as follows. In steady state, |err 2|. In the worst case, = |err 2|. For the desired speed ripple , a constant Kset can be defined as
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As long as
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are switched simultaneously. Both high- and low-side diodes conduct. The waveforms for this type of switching are shown in Fig. 9.
CONTROLLER DESIGN
The value of D can be expressed as a function of the motor
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Hall effect signals. The schematic of the controller simulated in the FPGA is shown in Fig. 13.
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Fig. 13. Block diagram showing operations and functions implemented in FPGA device.
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Fig. 14. Simulated duty, speed, and current response for a commanded speed of 2500 r/min for full-load operation.
Fig. 15. Experimental results for a reference speed of 2500 r/min under no load condition.
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Fig. 16. Experimental results for a reference speed of 2500 r/min. Load is 30% of rated value.
Fig. 17. Experimental results for a reference speed of 1500 r/min under no load condition.
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Fig. 18. Experimental results for a reference speed of 1500 r/min. Load is 30% of rated value.
Fig. 19. Experimental results for a reference speed of 2100 r/min under full load.
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Fig. 20. Speed response for change in load torque and for a reference speed of 2000 r/min.
Fig. 21. Experimental results for a change in reference speed from 2200 to 1300 r/min under no-load condition.
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CONCLUSION
The aim of this paper is to develop a low-cost controller for
Under dynamic load conditions, the proposed controller was found to be capable of regulating speed without the use of an observer.
This results in a considerable reduction of size and the cost of the
system.
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