Implementation of Control Unit

COMPARISON OF CONTROL UNIT IMPLEMENTATIONS

Control Unit Implementation
Combinational Logic Circuits (Hard-wired)
Control Data Memory

IR

Status F/Fs

Control Unit's State Timing State Ins. Cycle State

Combinational Logic Circuits

Control Points

CPU

Microprogram
M e m o r y
Control Data IR Status F/Fs

Next Address Generation Logic

C S A R

Control Storage (-program memory)

C S D R

C P s

CPU

TERMINOLOGY
Control signals Group of bits used to select paths in multiplexers, decoders, arithmetic logic units Control variables Binary variables specify microoperations Certain microoperations initiated while others idle Control word String of 1s and 0s represent control variables Microprogram - Program stored in memory that generates all the control signals required to execute the instruction set correctly - Consists of microinstructions Microinstruction - Contains a control word and a sequencing word Control Word - All the control information required for one clock cycle Sequencing Word - Information needed to decide the next microinstruction address - Vocabulary to write a microprogram Control Memory(Control Storage: CS) - Storage in the microprogrammed control unit to store the microprogram Writeable Control Memory(Writeable Control Storage:WCS) - CS whose contents can be modified -> Allows the microprogram can be changed -> Instruction set can be changed or modified Dynamic Microprogramming - Computer system whose control unit is implemented with a microprogram in WCS - Microprogram can be changed by a systems programmer or a user

Microprogrammed Control Organization

External input
Next Address Generator (sequencer)
CA R

Control Memory (ROM)

CDR

Control word

Control memory Contains microprograms (set of microinstructions) Microinstruction contains Bits initiate microoperations Bits determine address of next microinstruction Control address register (CAR) Specifies address of next microinstruction Next address generator (microprogram sequencer) Determines address sequence for control memory Microprogram sequencer functions Increment CAR by one Transfer external address into CAR Load initial address into CAR to start control operations Control data register (CDR)- or pipeline register Holds microinstruction read from control memory Allows execution of microoperations specified by control word simultaneously with generation of next microinstruction Control unit can operate without CDR also

Microprogram Routines

Sequencing(Microprogram Sequencing)

Routine Group of microinstructions stored in control memory Each computer instruction has its own microprogram routine to generate microoperations that execute the instruction A Microprogram Control Unit that determines the Microinstruction Address to be executed in the next clock cycle
- In-line Sequencing - Branch Conditional/ Unconditional - Subroutine - Instruction OP-code mapping

Control Memory
. Jump to Indirect or Execute Fetch cycle routine

. Jump to Execute
. Jump to Fetch Jump to Op code routine . Jump to Fetch or Interrupt . Jump to Fetch or Interrupt

Indirect Cycle routine

Interrupt cycle routine Execute cycle begin AND routine ADD routine

Sequencing

MICROINSTRUCTION SEQUENCING
Instruction code Mapping
logic

Status bits

Branch logic

MUX select

Multiplexers Subroutine register (SBR) Incrementer

Control address register

(CAR)

Control memory (ROM) select a status bit Branch address Microoperations

Sequencing Capabilities Required in a Control Storage

- Incrementing of the control address register - Unconditional and conditional branches - A mapping process from the bits of the machine instruction to an address for control memory - A facility for subroutine call and return

Sequencing

CONDITIONAL BRANCH
Load address

Control address register

Increment

MUX

Control memory

...
Status bits (condition) Condition select Next address Micro-operations

Conditional Branch

If Condition is true, then Branch (address from the next address field of the current microinstruction) else Fall Through Conditions to Test: O(overflow), N(negative), Z(zero), C(carry), etc.
Unconditional Branch Fixing the value of one status bit at the input of the multiplexer to 1

Sequencing

MAPPING OF INSTRUCTIONS
Direct Mapping
OP-codes of Instructions ADD 0000 AND 0001 LDA 0010 STA 0011 BUN 0100 Mapping Bits
0 xxxx 010 Address 0000 0001 0010 0011 0100 ADD Routine AND Routine LDA Routine STA Routine BUN Routine Control Storage

. . .

Address 0000 0100 0 0001 010 0 0010 010 0 0011 010 0 0100 010

ADD Routine AND Routine LDA Routine STA Routine BUN Routine

Sequencing

MAPPING OF INSTRUCTIONS TO MICROROUTINES

Mapping from the OP-code of an instruction to the address of the Microinstruction which is the starting microinstruction of its execution microprogram

Machine Instruction Mapping bits Microinstruction address

OP-code 1 0 1 1

Address

0 x x x x 0 0
0 1 0 1 1 0 0

Mapping function implemented by ROM or PLA OP-code Mapping memory (ROM or PLA)

Control address register Control Memory

Microprogram

MICROPROGRAM EXAMPLE
Computer Configuration
MUX
10 AR Address 10 PC 0 Memory 2048 x 16 0

MUX 6 SBR 0 6 CAR 0 15 DR 0

Control memory 128 x 20 Control unit

Arithmetic logic and shift unit 15 AC 0

Microprogram

MACHINE INSTRUCTION FORMAT

Machine instruction format
15 14 11 10 Opcode I 0 Address

Sample machine instructions

Symbol ADD BRANCH STORE EXCHANGE OP-code 0000 0001 0010 0011 Description AC AC + M[EA] if (AC < 0) then (PC EA) M[EA] AC AC M[EA], M[EA] AC EA is the effective address

Microinstruction Format
3 F1 3 F2 3 F3 2 CD 2 BR 7 AD

F1, F2, F3: Microoperation fields CD: Condition for branching BR: Branch field AD: Address field

Microprogram

MICROINSTRUCTION FIELD DESCRIPTIONS - F1,F2,F3

F1 000 001 010 011 100 101 110 111 Microoperation None AC AC + DR AC 0 AC AC + 1 AC DR AR DR(0-10) AR PC M[AR] DR Symbol NOP ADD CLRAC INCAC DRTAC DRTAR PCTAR WRITE F2 000 001 010 011 100 101 110 111 Microoperation None AC AC - DR AC AC DR AC AC DR DR M[AR] DR AC DR DR + 1 DR(0-10) PC Symbol NOP SUB OR AND READ ACTDR INCDR PCTDR

F3 000 001 010 011 100 101 110 111

Microoperation None AC AC DR AC AC AC shl AC AC shr AC PC PC + 1 PC AR Reserved

Symbol NOP XOR COM SHL SHR INCPC ARTPC

Microprogram

MICROINSTRUCTION FIELD DESCRIPTIONS - CD, BR

CD 00 01 10 11

Condition Always = 1 DR(15) AC(15) AC = 0

Symbol U I S Z

Comments Unconditional branch Indirect address bit Sign bit of AC Zero value in AC

BR 00 01 10 11

Symbol JMP CALL RET MAP

Function CAR AD if condition = 1 CAR CAR + 1 if condition = 0 CAR AD, SBR CAR + 1 if condition = 1 CAR CAR + 1 if condition = 0 CAR SBR (Return from subroutine) CAR(2-5) DR(11-14), CAR(0,1,6) 0

Microprogram

SYMBOLIC MICROINSTRUCTIONS
Symbols are used in microinstructions as in assembly language
A symbolic microprogram can be translated into its binary equivalent by a microprogram assembler.

Sample Format five fields: Label:

label; micro-ops; CD; BR; AD may be empty or may specify a symbolic address terminated with a colon

Micro-ops: consists of one, two, or three symbols separated by commas CD: one of {U, I, S, Z}, where U: Unconditional Branch I: Indirect address bit S: Sign of AC Z: Zero value in AC

BR: AD:

one of {JMP, CALL, RET, MAP} one of {Symbolic address, NEXT, empty}

Microprogram

SYMBOLIC MICROPROGRAM - FETCH ROUTINE

During FETCH, Read an instruction from memory and decode the instruction and update PC Sequence of microoperations in the fetch cycle:
AR PC DR M[AR], PC PC + 1 AR DR(0-10), CAR(2-5) DR(11-14), CAR(0,1,6) 0

Symbolic microprogram for the fetch cycle:

FETCH: ORG 64 PCTAR READ, INCPC DRTAR U JMP NEXT U JMP NEXT U MAP

Binary equivalents translated by an assembler

Binary address 1000000 1000001 1000010

F1 110 000 101

F2 000 100 000

F3 000 101 000

CD 00 00 00

BR 00 00 11

AD 1000001 1000010 0000000

Microprogram

SYMBOLIC MICROPROGRAM
Control Storage: 128 20-bit words The first 64 words: Routines for the 16 machine instructions The last 64 words: Used for other purpose (e.g., fetch routine and other subroutines) Mapping: OP-code XXXX into 0XXXX00, the first address for the 16 routines are 0(0 0000 00), 4(0 0001 00), 8, 12, 16, 20, ..., 60

Partial Symbolic Microprogram

Label
ADD:

Microops
ORG 0 NOP READ ADD ORG 4 NOP NOP NOP ARTPC ORG 8 NOP ACTDR WRITE ORG 12 NOP READ ACTDR, DRTAC WRITE ORG 64 PCTAR READ, INCPC DRTAR READ DRTAR

CD
I U U S U I U I U U I U U U U U U U U

BR
CALL JMP JMP JMP JMP CALL JMP CALL JMP JMP CALL JMP JMP JMP JMP JMP MAP JMP RET

AD
INDRCT NEXT FETCH OVER FETCH INDRCT FETCH INDRCT NEXT FETCH INDRCT NEXT NEXT FETCH NEXT NEXT NEXT

BRANCH: OVER:

STORE:

EXCHANGE:

FETCH: INDRCT:

Microprogram

BINARY MICROPROGRAM
Micro Routine ADD Address Decimal Binary 0 0000000 1 0000001 2 0000010 3 0000011 4 0000100 5 0000101 6 0000110 7 0000111 8 0001000 9 0001001 10 0001010 11 0001011 12 0001100 13 0001101 14 0001110 15 0001111 64 65 66 67 68 1000000 1000001 1000010 1000011 1000100 F1 000 000 001 000 000 000 000 000 000 000 111 000 000 001 100 111 110 000 101 000 101 Binary Microinstruction F2 F3 CD 000 000 01 100 000 00 000 000 00 000 000 00 000 000 10 000 000 00 000 000 01 000 110 00 000 000 01 101 000 00 000 000 00 000 000 00 000 000 01 000 000 00 101 000 00 000 000 00 000 100 000 100 000 000 101 000 000 000 00 00 00 00 00 BR 01 00 00 00 00 00 01 00 01 00 00 00 01 00 00 00 00 00 11 00 10 AD 1000011 0000010 1000000 1000000 0000110 1000000 1000011 1000000 1000011 0001010 1000000 1000000 1000011 0001110 0001111 1000000 1000001 1000010 0000000 1000100 0000000

BRANCH

STORE

EXCHANGE

FETCH

INDRCT

This microprogram can be implemented using ROM

Design of Control Unit

- DECODING ALU CONTROL INFORMATION -

DESIGN OF CONTROL UNIT

microoperation fields
F1 F2 F3

3 x 8 decoder 7 6 54 3 21 0

3 x 8 decoder 7 6 54 3 21 0

3 x 8 decoder 76 54 3 21 0

AND ADD DRTAC PCTAR DRTAR From From PC DR(0-10) 0 1 Multiplexers Arithmetic logic and shift unit

AC DR

Load

AC

Select

Load

AR

Clock

Design of Control Unit

- NEXT MICROINSTRUCTION
External (MAP)

MICROPROGRAM SEQUENCER

ADDRESS LOGIC

Branch, CALL Address RETURN form Subroutine In-Line

L

S1S0 00 01 10 11

Address Source CAR + 1, In-Line SBR RETURN CS(AD), Branch or CALL MAP

Address source selection

3 2 1 0 S1 MUX1 S0

SBR

Subroutine CALL

Incrementer

Clock

CAR

Control Storage

MUX-1 selects an address from one of four sources and routes it into a CAR

- In-Line Sequencing CAR + 1 - Branch, Subroutine Call CS(AD) - Return from Subroutine Output of SBR - New Machine instruction MAP

Design of Control Unit

MICROPROGRAM SEQUENCER
- CONDITION AND BRANCH CONTROL -

From I CPU S

1 MUX2 Select Z

Test

L BR field of CS
T Input I0 logic I
1

L(load SBR with PC) for subroutine Call S0 for next address S1 selection

CD Field of CS

Input Logic
I0I1T 000 001 010 011 10x 11x Meaning Source of Address In-Line JMP In-Line CALL RET MAP CAR+1 CS(AD) CAR+1 CS(AD) and SBR <- CAR+1 SBR DR(11-14) S1S0 00 10 00 10 01 11 L 0 0 0 1 0 0

S0 = I0 S1 = I0I1 + I0T L = I0I1T

Design of Control Unit

MICROPROGRAM SEQUENCER
External (MAP)
L

I0 Input I1 logic T

3 2 1 0 S1 MUX1 S0

SBR

Load

1 I S Z

Incrementer
MUX2 Select Test Clock CAR

Control memory Microops CD BR AD

...

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