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    Clock Divide

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    abhipankaj
    The document discusses various techniques for generating divide-by-clock signals using flip-flops. It explains how to divide the clock by 2, 4, 8, and higher powers of 2 using modulo-N counters. Other divide ratios like divide-by-3, 5, 6, 7, 9 are also explained. The output of one flip-flop is passed to the next as clock to generate more divided clock frequencies in a cascaded manner while maintaining a 50% duty cycle.

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    Attribution Non-Commercial (BY-NC)
    Download as PPTX, PDF, TXT or read online from Scribd

    Clock Divide

    Uploaded by

    abhipankaj
    183 views42 pages
    The document discusses various techniques for generating divide-by-clock signals using flip-flops. It explains how to divide the clock by 2, 4, 8, and higher powers of 2 using modulo-N counters. Other divide ratios like divide-by-3, 5, 6, 7, 9 are also explained. The output of one flip-flop is passed to the next as clock to generate more divided clock frequencies in a cascaded manner while maintaining a 50% duty cycle.

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    clock divide

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    The document discusses various techniques for generating divide-by-clock signals using flip-flops. It explains how to divide the clock by 2, 4, 8, and higher powers of 2 using modulo-N counters. Other divide ratios like divide-by-3, 5, 6, 7, 9 are also explained. The output of one flip-flop is passed to the next as clock to generate more divided clock frequencies in a cascaded manner while maintaining a 50% duty cycle.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    183 views42 pages

    Clock Divide

    Uploaded by

    abhipankaj
    The document discusses various techniques for generating divide-by-clock signals using flip-flops. It explains how to divide the clock by 2, 4, 8, and higher powers of 2 using modulo-N counters. Other divide ratios like divide-by-3, 5, 6, 7, 9 are also explained. The output of one flip-flop is passed to the next as clock to generate more divided clock frequencies in a cascaded manner while maintaining a 50% duty cycle.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPTX, PDF, TXT or read online from Scribd
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    You are on page 1of 42

    Divide by clock

    Deepak Floria
    deepakfloria@gmail.com

    Clock
    Clock refers to any device for measuring and displaying the time. Clock is repetitive in nature after some time period.

    System Clock
    Every modern PC has multiple system clocks. Each of these vibrates at a specific frequency, normally measured in MHz . A clock "tick" is the smallest unit of time in which processing happens, and is sometimes called a cycle.
    clock

    System Clock
    Some types of work can be done in one cycle while others require many. The ticking of these clocks is what drives the various circuits in the PC, and the faster they tick, the more performance you get from your machine.

    Clock Period
    clock
    On Time = t Off Time= t On Time

    Off Time

    On Time

    Off Time

    2t

    On time = off time Total time = T = 2t


    Duty Cycle = [(On Time/Total time) * 100 ]% Duty Cycle = t /T * 100 % = t/2t *100 % = 50%

    Clock
    Positive Edge

    ` Parameters
    Positive Level

    Negative Edge

    Negative Level

    Posedge to negedge => posLevel => On time => High Level


    Negedge to posedge => neg level => Off time => Low Level

    Clock Period => Posedge To Posedge or Negedge to Negedge

    Divide by Clock
    Reference clock

    In SOC some type of job done in one clock and others in multiple cycle. There are many types of Buses inside SOC system. These buses works at different clock signal but take reference from the main system clock. Taking Reference as the main System clock we perform the Divide by Clock operations.

    Divide by
    Freq divide By 2N N=1 => Divide By 2
    Reference Clock T = 2t F = 1/T Derived Clock

    N 2

    T = 2t F = 1/2T

    Divide by 2
    Counter: A counter is a device which works on each edge of the clock and count the number of clock pulses. Mod 2 Counter: Mod 2 counter will count two clock pulses of the clock signal. A mod 2 counter is exactly working for two clock cycle. Clk Count Clock
    pulses X 0 X 0 0 1

    Divide by 2 Mod 2 Counter


    d
    Reference Clock Reset Reference Clock T = 2t Q = Div/2 Clk T = 2T

    D-FF

    Div/2 Clock

    Divide by 4
    Freq divide By 2N N=2 => Divide By 4
    Reference Clock

    Derived Clock

    Clk period T = 4T Freq F= 1/T => 1/4T

    Divide by 4
    Mod 4 Counter: Mod 4 Johnson counter will count Four clock pulses of the clock signal. Consider the second FF Q1 output which is high for two Clock & low For Two Clock Cycle
    Clk Count Q1 Q0 Clock pulses

    X
    1 1 1

    X
    0 0 1

    X
    0 1 1

    0
    1 2 3

    1 0

    Divide by 4
    d0
    Q0

    d1

    Q1

    D-FF
    Clock

    Clock

    D-FF
    Q1
    Reset

    Q0

    Reset

    Reference Clock

    Divide by 4
    Freq divide By 2N N=2 => Divide By 4
    Reference Clock T = 2t F = 1/T 0

    Q0

    Q1 Derived Clock

    T = 4T

    F = 1/4T

    Alternative way to Div/4


    d0
    Q0

    d1

    Q1

    D-FF
    Clock

    Clock

    D-FF
    Q1
    Reset

    Q0

    Reset

    Reference Clock

    Pass the O/P of the 1st FF to the next FF as Clk signal

    Alternative way to Div/4


    Reference Clock T = 2t

    Q0 = Div/2 Clk Ref clk to 2nd FF

    Q1 = Div/4 Clk

    T = 4T

    Divide by 8 counter
    Freq divide By 2N N=3 => Divide By 8 A divide by 8 counter requires three flip flops It has 8 possible states The Q output of the third FF is given as an input to the first flip flop
    O/P of the 3rd FF is high for 3 clk cycle & low for 3 clk Cycle. This is the required Div/8 Clk signal
    clk X 1 1 1 1 1 1 1 1 Count Q2 Q1 Q0 X 0 0 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 Clock Cycle

    Waveform for Divide by 8 clock

    CLK
    T=2t

    T = 8T

    Divide by 8 counter Logic Diagram

    DA

    QA

    DB

    QB

    DC

    QC
    Div/8

    DFF
    CLK

    DFF

    DFF

    Alternative way to Div/8


    d0 Q0

    d1
    Q1

    Div/8

    D-FF
    Clock

    Clock

    D-FF
    Q1
    Clock Reset

    D-FF
    Reset

    Q0
    Reset

    Reference Clock

    Pass the O/P of the one FF to the next FF as Clk signal

    Alternative way to Div/8


    Reference Clock T = 2t

    Q0 = Div/2 Clk

    Q2 = Div/8 Clk

    T = 8T

    Divide by 16 counter
    Freq divide By 2N N=4 => Divide By 16 A divide by 16 counter requires 4 flip flops It has 16 possible states. The Q output of the last flip flop is connected to input to the first flip flop

    clk X 1 1

    Count Q3 Q2 Q1 Q0 X 0 0 0 0 X 0 0 0 0 X 0 0 1 1 X 0 1 0 1 0 1 2 3 4

    Clock Cycle

    The last FF O/P value is low for 8 clk cycle & high for 8 clk cycle. This O/P is the required Div/16 clk signal.

    1 1

    1
    1 1

    0
    0 0

    1
    1 1

    0
    0 1

    0
    1 0

    5
    6 7

    1
    1 1

    0
    1 1

    1
    0 0

    1
    0 0

    1
    0 1

    8
    9 10

    1
    1 1

    1
    1 1

    0
    0 1

    1
    1 0

    0
    1 0

    11
    12 13

    1
    1 1

    1
    1 1

    1
    1 1

    0
    1

    1
    0

    14
    15 16

    1 1

    Divide by 16 counter
    CLK

    T= 2t

    8T T = 16 T F = 1/16T

    Divide by 16 counter Logic Diagram

    DA

    QA

    DB

    QB

    DC

    QC

    DD

    QD

    Div/16

    DFF
    CLK

    DFF

    DFF

    DFF
    QD

    Divide by
    Freq divide By 2N N=N => Divide By N
    Reference Clock T = 2t F = 1/T Derived Clock

    N 2

    T = NT

    F = 1/NT

    Divide by
    d0 Q0

    N 2
    dN Div/N D-FF
    Clock

    d1
    Q1

    d2 Q2

    D-FF
    Clock Clock

    D-FF
    Q1
    Q0
    Clock

    D-FF

    Q2
    Reset

    QN

    Reset

    Reset

    Reset

    Reference Clock

    Divide by 3
    A divide by 3 clock requires A mod 3 Counter. It can be constructed using 2 FF. It has 4 possible states and it needs only 3 states
    Observe the OP of 2nd FF
    Clk Count Q1 Q0
    X X

    Clock pulses

    1 1 1

    0 0 1

    0 1 0

    1 2 3

    Divide by 3
    Pass the second FF O/P to one more FF which is triggered as negedge of clk. Make ORing of Q1 & Q. This is the require Div/3 50 % duty cycle Clk circuit.
    Div/ 3 clk

    d0

    d1 Q0
    Q1 Clock Q0

    D-FF
    Clock Reset

    D-FF
    Q1

    D-FF

    Reset

    Reference Clock

    Waveform for Divide by 3


    Freq divide By3
    Reference Clock
    T = 2t F = 1/T

    Q0

    Q1
    Q Div/3 clk

    T = 3T

    Divide by 5 clock
    A divide by 5 counter requires can be developed using Mod 5 Counter in similar method. To get 50% duty cycle output one more flip flop is added and it is negative edge triggered. Pass the output of the second Clk Count cycle
    Pass the output of the second FF to one more FF which is triggered with negedge of clk then make ORing of these two.
    Observe the output of second FF. It is High for 2 cycle & low for 3 cycle. Q2 Q1 Q0 X 1 1 1 X 0 0 0 X 0 0 1 X 0 1 0 0 1 2 3

    1 1

    0 1

    1 0

    1 0

    4 5

    Waveform for Divide by 5


    CLK T =2t

    QB

    2T

    QD

    QB + Q D

    t= 2+1/2 T
    T=5T

    Divide by 5 Clock Logic Diagram


    Y

    .
    DA QA QA

    DB

    QB QB

    DC

    QC

    DD

    QD

    QC

    CLK

    Divide by 6 counter
    Div/6 can be constructed by johnson counter. A Div/6 Johnson counter requires 3 bit FF.

    Clk The O/P of the 1st FF is high for 3 clk cycle & low for 3 clk cycle. This is the Required Div/6 clk signal. X 1 1 1

    Count Q2 Q1 Q0 X 0 1 1 X 0 0 1 X 0 0 0

    cycle 0 1 2 3

    1 1
    1

    1 0
    0

    1 1
    0

    1 1
    1

    4 5
    6

    Wavaeform for Divide by 6 counter


    Clk T=2t 3T Q

    T = 6T

    Divide by 7 counter
    A divide by 7 counter requires Mod 7 counter. It has 8 possible states and it needs only 7 states.
    The O/P of the 3rd FF is High for 3 clk cycle & low for 3 clk cycle. Pass this O/P to one more FF which will work negedge of Clk then make ORing of these two O/P. Clk X Count Q2 Q1 Q0 X X X cycle 0

    1 1
    1 1 1 1 1

    0 0
    0 0 1 1 1

    0 0
    1 1 0 0 1

    0 1
    0 1 0 1 0

    1 2
    3 4 5 6 7

    Divide by 7 counter
    1 CLK 2 3 4 5 6 7 1 2 3 4 5 6

    2t
    6T

    QA

    QD

    7T T=7T

    QA + Q D

    Divide by 7 counter Logic Diagram


    . .
    DA
    QA QA Y

    DB

    QB

    DC

    QC QC

    DD

    QD

    QB

    CLK

    Divide by 9 counter
    A divide by 9 counter requires Mod 9 counter. It has 16 possible states and it needs only 9 states
    The 3rd FF O/P value is low for 5 clk cycle & high for 4 clk cycle. This O/P is the required Div/9 clk signal but not 50% duty cycle.
    Pass this O/P to one more FF triggered with negedge clk and then make Oring fo these two signal to 50% duty cycle.
    clk Count Q3 Q2 Q1 Q0 X 0 0 0 0 0 0 X 0 0 0 0 1 1 X 0 0 1 1 0 0 X 0 1 0 1 0 1 0 1 2 3 4 5 6 Clock Cycle X 1 1 1 1 1 1

    1
    1 1 1

    0
    0 1 1

    1
    1 0 0

    1
    1 0 0

    0
    1 0 1

    7
    8 9 10

    Divide by 9 counter
    1 2 3 4 5 6 7 8 9 1 2 3 4 5 6

    CLK

    2T
    4T

    QB

    QE

    4+1/2T

    Q B + QE T=9T

    Div/9 counter Logic Diagram


    . . .

    .
    DA QA QA CLK DB QB QB

    DC

    QC QC

    .
    .

    DD

    QD QD

    DE

    QE

    ThankYou Deepak floria

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