490/590

Computer Architecture
Lecture 1: Course Introduction


Prof. Wenyao Xu
Computer Science & Engineering, SUNY at Buffalo
Spring 2014, 1/27/2014



Agenda Today
Why we need to learn Computer Architecture?
Motivation;
Definition.

What is Course Content?
Knowledge Review;
Memory Hierarchy;
Parallelism.

Course Logistics and Administration
Logistics;
Grading policy.

2
Agenda Today
Why we need to learn Computer Architecture?
Motivation;
Definition.

What is Course Content?
Knowledge Review;
Memory Hierarchy;
Parallelism.

Course Logistics and Administration
Logistics;
Grading policy.

3
Background:
Example 1: direction measurement.





Example 2: activity tracker.
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What is manufactured is what we need!
Accelerometer
Filtering, Amplifying
ADC
Activity featuring
Activity recognition
Output
Magnetometer
Output
We need to integrate many components from different layers.
What is Computer Architecture
Application
Physics
Gap too large
to bridge in
one step
In its broadest definition,
computer architecture is
the design of the
abstraction layers that
allow us to implement
information processing
applications efficiently
using available
manufacturing
technologies.
Abstraction Layers in Modern Systems
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Algorithm
Gates/Register-Transfer Level (RTL)
Application
Instruction Set Architecture (ISA)
Operating System/Virtual Machines
Microarchitecture
Devices
Programming Language
Circuits
Physics
490/590
Computer
Architecture
The Power of Abstraction
Levels of transformation create abstractions
Abstraction: A higher level only needs to know about the
interface to the lower level, not how the lower level is
implemented
E.g., high-level language programmer does not really need to
know what the ISA is and how a computer executes instructions

Abstraction improves productivity
No need to worry about decisions made in underlying levels
E.g., programming in Java vs. C vs. assembly vs. binary vs. by
specifying control signals of each transistor every cycle

Then, why would you want to know what goes on
underneath or above?


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Crossing the Abstraction Layers
As long as everything goes well, not knowing what happens
in the underlying level (or above) is not a problem.

What if
The program you wrote is running slow?
The program you wrote does not run correctly?
The program you wrote consumes too much energy?

What if
The hardware you designed is too hard to program?
The hardware you designed is too slow because it does not provide the
right primitives to the software?

One goal of this course is to understand how a processor
works underneath the software layer and how decisions
made in hardware affect the software/programmer
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Computing Devices Then
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EDSAC, University of Cambridge, UK, 1949
Computing Devices Now
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10
Robots
Supercomputers
Automobiles
Laptops
Set-top
boxes
Games
Smart
phones
Servers
Media
Players
Sensor Nets
Routers
Cameras
Conventional Wisdom in Comp. Arch
Old CW: Power is free, Transistors are expensive
New CW: Power is expensive, Transistors are free
(Can put more on chip than can afford to turn on)

Old CW : Reduced Instruction Set Computer (RISC) is efficient (old
Apple CPU)
New CW : Complex Instruction Set Computer (CISC) has better
performance (using Out-of-order, speculation, VLIW, ), such as Intel
CPU, new Apple CPU.

Old CW : Multiplies are slow, Memory access is fast
New CW: Memory slow, multiplies fast

Old CW : Build a powerful and complicated processor
New CW: Assemble many simple processors together


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Agenda Today
Why we need to learn Computer Architecture?
Motivation;
Definition.

What is Course Content?
Knowledge Review;
Memory Hierarchy;
Parallelism.

Course Logistics and Administration
Logistics;
Grading policy.

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Course Structure
15-week Lectures

14-week Recitations

5 Homeworks

2 Projects

2 Quiz, 1 Midterm, 1 Final
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CSE 490/590 Course Focus
Understanding the design techniques, machine structures,
technology factors, evaluation methods that will determine
the form of computers in 21st Century
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Technology
Programming
Languages
Operating
Systems
History
Applications
Interface Design
(ISA)
Measurement &
Evaluation
Parallelism
Computer Architecture:
Organization
Hardware/Software Boundary
Compilers
Course Structure
Instruction Level Parallelism
Superscalar
Very Long Instruction Word (VLIW)
Long Pipelines (Pipeline Parallelism)
Advanced Memory and Caches (Memory Hierarchy)
Data Level Parallelism
Vector
GPU
Thread Level Parallelism
Multithreading
Multiprocessor
Multicore
Manycore
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Agenda Today
Why we need to learn Computer Architecture?
Motivation;
Definition.

What is Course Content?
Knowledge Review;
Memory Hierarchy;
Parallelism.

Course Logistics and Administration
Logistics;
Grading policy.

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Course Info: Who Are We?
Instructor: Wenyao Xu
wenyaoxu@buffalo.edu
Office: 330 Davis
Office Hours: Tue/Thu 9-10am (or by appointment)
http://www.cse.buffalo.edu/~wenyaoxu/
PhD from UC Los Angeles 2013
Research and teaching interests:
Efficient Computing Technologies
Computer architecture, hardware/algorithm co-design
Memory-computing
DVFS, Word-length Optimization, etc.
Embedded Sensing System
Embedded Algorithms
Human-computer Interaction
Medical and Healthcare Applications



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Course Info: Who Are We?
Teaching Assistants
Pengzhan Yan
Email: pyan2@buffalo.edu
Office hours: Mon 1:00-3:00pm or by appointment
Location: 340 Davis Hall
Shixiong Jiang
Email: shixiong@buffalo.edu
Office hours: Wen 1:00-3:00pm or by appointment
Location: 340 Davis Hall
Dayu He
Email: dayuhe@buffalo.edu
Office hours: Fri 1:00-3:00pm or by appointment
Location: 302 Davis Hall



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Where to Get Up-to-date Course Info?
Course Website:
http://www.cse.buffalo.edu/~wenyaoxu/courses/cse490/in
dex.html
Lecture notes
Project information
Homeworks
Course schedule, handouts, reading, FAQs

Your email: we will send you timely notice regarding the
course.

Email me and the TAs

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Books
Computer Architecture, Fifth
Edition: A Quantitative
Approach (The Morgan
Kaufmann Series in Computer
Architecture and Design) (5th
Edition), 2011.
John L. Hennessy and David
A. Patterson
The 5th edition is new and
very different than previous
editions. USE THE 5TH
EDITION. (ISBN: 978-
0123838728)
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What Do We Expect From You?
Required background: CSE 241 (digital logic, RTL
implementation, Verilog), CSE 341 (computer organization,
basic processor design, pipelining/cashes, assembly) or
equivalent courses.
Afford BASYS2 Dev. Board for projects
You need to purchase it as soon as possible!
http://www.digilentinc.com/Products/Detail.cfm?Prod=BASYS2
Get the student version ($69)
Learn the material thoroughly
attend lectures, do the homeworks & projects independently
Ask questions, take notes, participate
Work hard and manage your time
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How Will You Be Evaluated?

5 Homeworks: 0% (no grading, solutions provided)
Two Quiz: 20% (10% each)
Midterm: 20%
Final: 25%
Two Projects: 35%
10% for the first project
25% for the second project




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Recitations & HW Assignments

It is very helpful to attend the recitations.
Reasons:
For the first 5 weeks, we will cover Xilinx ISE tools, Verilog
and how to use BASYS2 board.
We will do the review before quiz and exam.
Do Homeworks!
The best way to self-examine what you learnt;
Quiz/Exams might have the similar questions to HW.



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A Note on Cheating and Academic Dishonesty
Absolutely no form of cheating will be tolerated

You are all adults and we will treat you so

See syllabus, UB Policy, and CSE Academic Integrity Policy
Linked from syllabus

Cheating Failing grade (no exceptions)
And, perhaps more

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Acknowledgement
These slides heavily contain material developed and
copyright by
Krste Asanovic (MIT/UCB)
David Patterson (UCB)
Onur Mutlu (CMU)
And also by:
Arvind (MIT)
Joel Emer (Intel/MIT)
James Hoe (CMU)
John Kubiatowicz (UCB)

MIT material derived from course 6.823
UCB material derived from course CS252
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