Analog To Digital Converters (ADC) 1: ©paul Godin Created April 2008

Analog to Digital Converters
(ADC)
1
ADC 1.1
Paul Godin
Created April 2008
Introduction
Analog to digital conversion is an important aspect
of digital electronics.
ADCs allow the use of real-world values with the
advantages of digital electronics.
There are many examples of ADC converters used
in everyday applications.
Name a few examples of ADC applications

ADC 1.2
Advantages of Digital Values
Relatively less sensitive to distortion (noise and losses)

Can be reproduced much more accurately
Much easier to reconstruct a signal
More storage options
Can be processed mathematically and logically
Easier to standardize
Systems are easier to design (fewer voltage / current issues)
Digital systems can be made small (low current)
Display options
ADC 1.3
Challenges with ADC

Converting an analog value to digital values
comes with disadvantages:
It takes time to convert a signal from Analog to Digital,
and then to process that signal. May be too slow for
some applications.
Never 100% reproductionalways a series of discrete
values.
Requires more complex circuit design
More faithful reproduction requires more bit of
resolution.
Requires other circuit elements such as oscillators and
memory systems.
ADC 1.4
ADC FUNDAMENTALS
ADC 1.5
Sampling
Voltage signals are comprised of amplitude over
time.
The analog signal must be converted to its digital
value at specific periods of time.
Sampling is the process of taking a digital value at
regular time intervals.
ADC 1.6
Sampling
AC Value
Sampling
Pulses
Time
Digital Values at timed intervals
ADC 1.7
Sampling
Increasing the number of binary values
representing a voltage value improves its voltage
resolution. This is called quantization. The
greater the number of bits available, the greater
the quantization level.
Increasing the sampling frequency improves the

time resolution. The more samples taken over
time the more accurate the representation of the
signal.
ADC 1.8
Nyquist
The sampling frequency must be greater than the
highest frequency component of the analog signal.
The Nyquist frequency has a value of twice the
highest analog frequency.
fsample 2fA(MAX)
Where:
fsample is the sampling frequency
fA(MAX) is the maximum analog frequency
ADC 1.9
Sampling Issues
AC Value
Digital Value
Properly Sampled
Under-sampled
ADC 1.10
Sampling Rates
Sampling rates are selected based on:
application
requirements
standards
As an example, an exterior thermometer neednt

be sampled at the same rate as an audio
application.
ADC 1.11
Audio Application of ADC

When music is digitized for CDs the sampling
frequency is 44.1 kHz (48 kHz for professional
recording).
According to the Nyquist frequency, 44.1kHz is
acceptable for up to 22 kHz. Since most audio
equipment functions at less than 20 kHz (and is at
the upper limit of human hearing), the 44.1 kHz
sampling rate is acceptable.
The bit depth is 16 for CD audio.
ADC 1.12
Notes on mp3
MP3 audio files refer to their quality as a bit rate. Typical

mp3 bit rates are 128kbps and 192kbps (maximum is
320kbps according to standards).
MP3 is an encoding format used to compress and reduce the

file size. The file follows protocols and contains various
elements such as headers, file information, the compressed
data, bit rate type and other information.
For comparison, bit rate for uncompressed audio (CD)

recording is 44.1kHz sampling x 16 bits x 2 channels
(1411.2 kbps).
ADC 1.13
Digitizing Voice
Human voice for applications such as telephone
conversations need not be sampled at a similar
rate and bit depth as music.
Typically, 8 bits at 8 kHz sampling rate is used
(64kbps).
ADC 1.14
ASYNCHRONOUS ADC
ADC 1.15
Asynchronous ADC
ADCs can be constructed from comparators.
A comparator is an op amp configuration where

the voltages of two inputs are compared.
If the + input is greater than the - input, the output
is a logic high.
VDD
We first investigated comparators when

discussing the 555 timers function.
ADC 1.16
Comparator-Based ADC
VDD
Analog In
Digital Out
2-bit weighted ADC

ADC 1.17
Flash ADC
VDD
Analog In
Priority
Encoder
Digital Out
Enable
3-bit Flash ADC

ADC 1.18
SYNCHRONOUS ADC
ADC 1.19
Hold/Store
Asynchronous ADC have limited uses. ADCs need to store

measured values between the sampling pulses.
The data must be held between the sampling pulses to allow

the digital devices to read the values. This is necessary for
values to be either processed or stored.
As the input values change the digital output values change
numerically, not linearly.
All bits of an ADC do not change at precisely the same time due
to delays.
Converting a stored digital signal back to analog requires a
similar clocking frequency (time needs to be reproduced). AD
conversion represents a series of values at specific instances of
time.
The Sample and Hold creates the output ladder effect.
ADC 1.20
Basic ADC
A basic ADC contains:
differential analog inputs (VREF) for
scaling
Analog signal input (VIN)
Output Enable for tristate-able outputs
(OE)
Start of Conversion input (SOC) to
trigger the analog signal read cycle.
End of Conversion output (EOC) to
indicate that the conversion is
complete, the data is on the data bus
and a new input may be applied.
Digital output (D0~D7).
ADC 1.21
Flash ADC with Sample/Hold

VDD
Analog In
Priority
Encoder
Latch
Circuit
Clock
Digital Out
Digital Out
Enable
3-bit Flash ADC

ADC 1.22
Flash ADC
Flash ADCs are very fast and can convert data at
high frequencies.
The major disadvantage to flash ADCs is the
complexity of the circuits.
One op amp is required for each output value (minus one
for all zero). This means that:
an 8-bit Flash ADC requires 255 op amps
a 12-bit Flash ADC requires 4095 op amps
a 16-bit flash ADC requires 65,535 op amps
ADC 1.23
Dual Slope ADC

Also known as Counter-Ramp or Digital Ramp ADC
A dual slope ADC is commonly used in

measurement instruments (such as DVMs).
ADC 1.24
Dual Slope Circuit

Input
Oscillator
Switch
Control Logic
Counter
VReference
Registers
Digital Output
ADC 1.25
Dual Slope Function

The Dual Slope ADC functions in this manner:
When an analog value is applied the capacitor begins to
charge in a linear manner and the oscillator passes to the
counter.
The counter continues to count until it reaches a
predetermined value. Once this value is reached the
count stops and the counter is reset. The control logic
switches the input to the first comparator to a reference
voltage, providing a discharge path for the capacitor.
As the capacitor discharges the counter counts.
When the capacitor voltage reaches the reference voltage
the count stops and the value is stored in the register.
ADC 1.26
Dual Slope
VReference
Capacitor Cycle
Counter Cycle
Charge
Counts from 0
to max
Count Reset
Discharge
Count
Display
Count
Display
Max Count /
Restart Count
ADC 1.27
Dual Slope
The Dual Slope method takes time for the
conversion to occur. Each additional bit improves
resolution but also adds a significant bit to the
counter, costing considerable time. This type of
ADC is therefore unsuitable for rapidly changing
analog input.
Each clocking pulse increments the counter by
one. It takes (2N-1) clock cycles times the clock
period for an output to be produced.
ADC 1.28
Dual Slope
If using an 8-bit digital ramp with an input
frequency of 500kHz, the conversion would take:
1
(28 1) (
) 255 2s 510s
500kHz
If using a 12-bit digital ramp with an input

frequency of 500kHz, the conversion would take:
1
(212 1) (
) 4095 2s 8.19ms
500kHz
ADC 1.29
Dual Slope
The Dual Slope method is accurate and requires
less circuitry than other methods. Since it uses
the same clock input for both phases of
conversion, a drift in the clocking frequency will
not affect the accuracy of the output.
The Dual Slope is best suited for applications

where the measured value is relatively stable such
as DC voltage measurements.
ADC 1.30
Successive-Approximation ADC
The Successive-Approximation ADC is one of the
most popular types in use today. It has a
relatively simple configuration and an excellent
conversion rate.
ADC 1.31
SOC
Input
Oscillator
Voltage
Comparator
EOC
Control Logic
Digital to
Analog
Converter
Approximation
Register
Output
Register
Digital Output
ADC 1.32
The SAC ADC functions in this manner:
The approximation register is reset to all zero.

When a voltage is applied to the input the approximation
registers most significant bit is changed from a 1 to a 0. The
digital output of the register is converted back to analog through
the DAC and is compared to the applied analog voltage. If the
value is too low the 1 is left at the MSB. The next MSB is
incremented, the output converted to analog and again compared
to the analog input. Each bit is successively incremented and the
output value compared.
If the voltage from the DAC becomes higher than the applied
analog value the bit is reset to 0 and the next MSB is incremented
and compared.
The process continues in this manner until the LSB value is
reached. At the LSB, if the applied value makes the DAC output
voltage higher the bit is reset to 0. The ADC has completed its
process. It stores the value to the output register and provides an
EOC output to indicate there is a value in the register.
ADC 1.33
SAC ADC Conversion
An 8-bit SAC has a resolution of 10 mV. What is the digital

output for an input of 505 mV?
Solution:
505mV / 10mV 50.5steps

50 steps = 0011 0010
51 steps = 0011 0011
A SAC produces an output below the analog voltage, therefore

the output is 0011 0010
(50 steps at 10 mV per step, or 500 mV)
ADC 1.34
SAC ADC Conversion Time
Theoretically each step in the comparison process takes a clock

edge. It therefore takes a SAC ADC approximately the same
amount of clock edges as the number of bits it handles.
If a SAC ADC has an output of 8 bits and an input clocking
frequency of 500 kHz, it takes approximately:
8(1/500kHz) = 82s=16s
In actual practice it may take more than one clock edge per
step, but this is still faster than some other methods.
ADC 1.35
The ADC08
The ADC08 family is a relatively popular SAC ADC.
VDD
+VIN
D0 to D7
-VIN
Digital Output
Vref/2
CS
RD
ClkOUT
WR
ClkIN
INTR
GNDAnalog
A
GNDDigital
D
ADC 1.36
ADC08
+VIN and VIN : Differential analog voltage.
Vref/2 : Used to change the input voltage range. Normally at

2.5V when VDD = 5V, if 1.5V is applied the input range is 3.0
Volts and the resolution is changed accordingly.
ClkIN: Input clock. External clocking edges can be provided

to the ADC.
ClkOUT: Output Clock. This ADC has an internal clocking

circuit that requires external connection to an RC.
T = 1.1RC
Typical values: 10k & 150F
ADC 1.37
ADC08
CS : Chip Select (input), tri-states the digital output for bus

applications
RD: Read enable (input), enables the output from the

Approximation register to the output register.
WR: Write enable (input), used to request the start of a

new conversion.
INTR: Interrupt, output high when the ADC is in the

process of converting an input. Used to signal
microprocessors or microcontrollers. Conversion time is
approximately 100s.
ADC 1.38
ADC08
Questions:
What is the purpose of two grounds?
How would the device be configured for an input of:

0 to 5 Volts
0 to 3 Volts
-2.5 to +2.5 Volts
What is the purpose of the Vref/2 input?
ADC 1.39
SAC ADC
The SAC ADC is a fast, accurate device.
It has few disadvantages over other methods.
ADC 1.40
END ADC1
Paul R. Godin
prgodin@ gmail.com
ADC 1.41

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Analog to Digital Converters

Name a few examples of ADC applications

Advantages of Digital Values

Relatively less sensitive to distortion (noise and losses)

Challenges with ADC

Increasing the sampling frequency improves the

As an example, an exterior thermometer neednt

Audio Application of ADC

MP3 audio files refer to their quality as a bit rate. Typical

MP3 is an encoding format used to compress and reduce the

For comparison, bit rate for uncompressed audio (CD)

A comparator is an op amp configuration where

We first investigated comparators when

2-bit weighted ADC

3-bit Flash ADC

Asynchronous ADC have limited uses. ADCs need to store

The data must be held between the sampling pulses to allow

The Sample and Hold creates the output ladder effect.

Flash ADC with Sample/Hold

3-bit Flash ADC

Dual Slope ADC

A dual slope ADC is commonly used in

Dual Slope Circuit

Dual Slope Function

If using a 12-bit digital ramp with an input

The Dual Slope is best suited for applications

The SAC ADC functions in this manner:

The approximation register is reset to all zero.

SAC ADC Conversion

An 8-bit SAC has a resolution of 10 mV. What is the digital

505mV / 10mV 50.5steps

A SAC produces an output below the analog voltage, therefore

SAC ADC Conversion Time

Theoretically each step in the comparison process takes a clock

+VIN and VIN : Differential analog voltage.

Vref/2 : Used to change the input voltage range. Normally at

ClkIN: Input clock. External clocking edges can be provided

ClkOUT: Output Clock. This ADC has an internal clocking

CS : Chip Select (input), tri-states the digital output for bus

RD: Read enable (input), enables the output from the

WR: Write enable (input), used to request the start of a

INTR: Interrupt, output high when the ADC is in the

How would the device be configured for an input of:

It has few disadvantages over other methods.

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