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    Pipelined Adc

    Uploaded by

    Hubert Ekow Attah
    The document discusses pipelined ADCs. It describes the pipelined ADC architecture as a bucket brigade of algorithmic ADCs with concurrent operation of all stages. It explains the operation of 1.5-bit and 2.5-bit stages, including timing diagrams, decoding schemes, and reference levels. It also covers features and limitations of pipelined ADCs as well as strategies for optimizing stage scaling to reduce area and power consumption.

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    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd

    Pipelined Adc

    Uploaded by

    Hubert Ekow Attah
    145 views14 pages
    The document discusses pipelined ADCs. It describes the pipelined ADC architecture as a bucket brigade of algorithmic ADCs with concurrent operation of all stages. It explains the operation of 1.5-bit and 2.5-bit stages, including timing diagrams, decoding schemes, and reference levels. It also covers features and limitations of pipelined ADCs as well as strategies for optimizing stage scaling to reduce area and power consumption.

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    Pipeline notes

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    The document discusses pipelined ADCs. It describes the pipelined ADC architecture as a bucket brigade of algorithmic ADCs with concurrent operation of all stages. It explains the operation of 1.5-bit and 2.5-bit stages, including timing diagrams, decoding schemes, and reference levels. It also covers features and limitations of pipelined ADCs as well as strategies for optimizing stage scaling to reduce area and power consumption.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    145 views14 pages

    Pipelined Adc

    Uploaded by

    Hubert Ekow Attah
    The document discusses pipelined ADCs. It describes the pipelined ADC architecture as a bucket brigade of algorithmic ADCs with concurrent operation of all stages. It explains the operation of 1.5-bit and 2.5-bit stages, including timing diagrams, decoding schemes, and reference levels. It also covers features and limitations of pipelined ADCs as well as strategies for optimizing stage scaling to reduce area and power consumption.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 14

    Data Converters

    Pipelined ADCs
    Professor Y. Chiu

    EECT 7327
    Fall 2014

    Pipelined ADC

    Data Converters

    Pipelined ADCs
    Professor Y. Chiu

    EECT 7327

    Pipelined ADC Architecture


    Fall 2014

    A bucket brigade of algorithmic ADC w/ concurrent operation of all stages


    2

    Data Converters

    Pipelined ADCs
    Professor Y. Chiu

    EECT 7327

    A 1.5-Bit Stage

    Fall 2014

    2X gain + 3-level DAC + subtraction all integrated


    Digital redundancy relaxes the tolerance on CMP/RA offsets
    3

    Data Converters

    Pipelined ADCs
    Professor Y. Chiu

    EECT 7327

    Timing Diagram of Pipelining


    Fall 2014

    Two-phase nonoverlapping clock is typically used, with the coarse ADCs


    operating within the nonoverlapping times
    All pipelined stages operate simultaneously, increasing throughput at the
    cost of latency (what is the latency of pipeline? 1 T?)
    4

    Data Converters

    Pipelined ADCs
    Professor Y. Chiu

    EECT 7327

    1.5-Bit Decoding Scheme


    Fall 2014

    b-1

    -1

    +1

    C2

    +VR

    -VR

    Data Converters

    Pipelined ADCs
    Professor Y. Chiu

    EECT 7327

    A 2.5-Bit Stage

    Fall 2014

    Data Converters

    Pipelined ADCs
    Professor Y. Chiu

    EECT 7327

    2.5-Bit RA Transfer Curve


    Fall 2014

    6 comparators + 7-level DAC are required


    Max tolerance on comparator offset is VR/8
    7

    Data Converters

    Pipelined ADCs
    Professor Y. Chiu

    EECT 7327

    2.5-Bit Decoding Scheme


    Fall 2014

    b-3

    -3

    -2

    -1

    +1

    +2

    +3

    b1

    -1

    -1

    -1

    +1

    +1

    +1

    b2

    -1

    -1

    +1

    +1

    b3

    -1

    +1

    C2

    +VR

    +VR

    +VR

    -VR

    -VR

    -VR

    C3

    +VR

    +VR

    -VR

    -VR

    C4

    +VR

    -VR

    7-level DAC, 333 = 27 permutations of potential configurations


    multiple choices of decoding schemes!
    Choose the scheme to minimize decoding effort, balance loading for
    reference lines, etc.
    8

    Data Converters

    Pipelined ADCs
    Professor Y. Chiu

    EECT 7327

    Pipelined ADC

    Fall 2014

    Features

    Architecture complexity is proportional to the resolution N = nj


    Throughput is significantly improved relative to algorithmic or SAR
    Digital redundancy works the same way as algorithmic
    Inter-stage gain enables stage scaling to save power and area

    Limitations

    Typically 3 conversion operations are involved


    Sample-and-hold
    Sub-ADC comparison
    Sub-DAC and residue generation

    High-gain op-amps are required to produce residue signals with certain


    accuracy, which limits the conversion speed
    Long latency may be problematic for certain applications

    Data Converters

    Pipelined ADCs
    Professor Y. Chiu

    EECT 7327

    No Stage Scaling

    Fall 2014

    Stage size/
    power/area

    S 1
    Input-referred
    kT/C noise

    All stages identically sized same capacitors, op-amps, comparators


    Later stages are clearly oversized due to inter-stage gains
    10

    Data Converters

    Pipelined ADCs
    Professor Y. Chiu

    EECT 7327

    Aggressive Stage Scaling


    Fall 2014

    Stage size/
    power/area

    S 2
    Input-referred
    kT/C noise

    Stages sized such that the input-referred noises are identical


    Later stages are clearly downsized too aggressively
    11

    nj 2

    Data Converters

    Pipelined ADCs
    Professor Y. Chiu

    EECT 7327

    Optimum Stage Scaling

    Fall 2014

    Stage size/
    power/area
    nj

    S2
    Input-referred
    kT/C noise

    Optimum scaling lies in between the two extremes S 2nj


    12

    Data Converters

    Pipelined ADCs
    Professor Y. Chiu

    EECT 7327

    References

    Fall 2014

    1. S. H. Lewis and P. R. Gray, JSSC, pp. 954-961, issue 6, 1987.


    2. S. Sutarja and P. R. Gray, JSSC, pp. 1316-1323, issue 6, 1988.
    3. B.-S. Song et al., JSSC, pp. 1324-1333, issue 6, 1988.
    4. Y.-M. Lin, B. Kim, and P. R. Gray, JSSC, pp. 628-636, issue 4, 1991.
    5. S. H. Lewis et al., JSSC, pp. 351-358, issue 3, 1992.
    6. S.-H. Lee and B.-S. Song, JSSC, pp. 1679-1688, issue 12, 1992.
    7. A. N. Karanicolas, H.-S. Lee, and K. Barcrania, JSSC, pp. 1207-1215, issue 12, 1993.
    8. K. Sone et al., JSSC, pp. 1180-1186, issue 12, 1993.
    9. M. Yotsuyanagi et al., JSSC, pp. 292-300, issue 3, 1993.
    10. J. Wu, B. Leung, and S. Sutarja, ISCAS, 1994, pp. 461-464.
    11. T.-H. Shu, B.-S. Song, and K. Barcrania, JSSC, pp. 443-452, issue 4, 1995.
    12. T. B. Cho and P. R. Gray, JSSC, pp. 166-172, issue 3, 1995.
    13. E. G. Soenen and R. L. Geiger, TCAS2, pp. 143-153, issue 3, 1995.
    14. P. C. Yu and H.-S. Lee, JSSC, pp. 1854-1861, issue 12, 1996.
    15. D. W. Cline and P. R. Gray, JSSC, pp. 294-303, issue 3, 1996.
    13

    Data Converters

    Pipelined ADCs
    Professor Y. Chiu

    EECT 7327

    References

    Fall 2014

    16. M. K. Mayes and S. W. Chin, JSSC, pp. 1862-1872, issue 12, 1996.
    17. L. A. Singer and T. L. Brooks, VLSI, 1996, pp. 94-95.
    18. S.-U. Kwak, B.-S. Song, and K. Barcrania, JSSC, pp. 1866-1875, issue 12, 1997.
    19. K. Y. Kim, N. Kusayanagi, and A. A. Abidi, JSSC, pp. 302-311, issue 3, 1997.
    20. J. M. Ingino and B. A. Wooley, JSSC, pp. 1920-1931, issue 12, 1998.
    21. I. E. Opris et al., JSSC, pp. 1898-1903, issue 12, 1998.
    22. I. Mehr and L. A. Singer, JSSC, pp. 318-325, issue 3, 2000.
    23. L. A. Singer et al., ISSCC, 2000, pp. 38-39.
    24. W. Yang et al., JSSC, pp. 1931-1936, issue 12, 2001
    25. B. Murmann and B. E. Boser, JSSC, pp. 2040-2050, issue 12, 2003.
    26. X. Wang, P. J. Hurst, and S. H. Lewis, CICC, 2003, pp. 409-412.
    27. J. Li and U.-K. Moon, CICC, 2003, pp. 413-416.
    28. Y. Chiu, P. R. Gray, and B. Nikolic, JSSC, pp. 2139-2151, issue 12, 2004.
    29. E. Siragusa and I. Galton, JSSC, pp. 2126-2138, issue 12, 2004.
    30. H.-C. Liu, Z.-M. Lee, and J.-T. Wu, ISSCC, 2004, pp. 454-455, 539.
    14

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