Design of High Speed Op Amp With Different

High speed op amp with different
compensation technique
7/5/15
Overview
Introduction
Objective
Literature Survey
Frequency Compensation
Compensation Techniques
Design plan
Results
Layout
Conclusion
References
7/5/15
Introduction
Op Amps are the most versatile and integral part of many

analog and mixed signal system.
They are employed from dc bias application to high speed

amplifiers and filters
General purpose op amps can be used as summer, buffer,

integrator, differentiator, comparators and many other
applications
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Transient Frequency
The expression for a short channel MOSFET transition
frequency (fT) and open-loop gain (gm*ro) are given as
Important!!
Therefore from the above eqn we can

see that scaling down of feature size
results in higher fT
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Biasing for high speed
Must use minimum length devices
Larger overdrive results in faster circuits

- Drawback is that the devices enter the triode region earlier
For minimum power use minimum size devices
- For nm CMOS minimum (drawn) W is, generally, 10 times
minimum L
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Open loop gain trends in future

CMOS process
The projection of open-loop voltage gain drops

from CMOS
transistors.
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Objective
To design the high speed two stage op amp

with different types of compensation circuits
like
1. with nulling resistor
2. with voltage follower
3. with current buffer
and the optimized layout design.
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Specification
Parameters
Target
Supply voltage
= 1.8V +/- 10%
Vin,cm
=1.2V +/-10%
DC gain
> 50dB
UGB
> 1GHz
PM
> 60deg
Settling time
< 3ns
CL
1pF
Technology
= 130nm
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Literature survey
Stability of an
opamp
Closed loop
response
Barkhausens Criteria.
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11
Time-Domain Response of a
System Versus Position of Poles
The location of the poles of a closed

Loop system is shown
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12
One-Pole System
(one-pole feed forward amplifier)
one pole system is

Unconditionally
Stable.
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Two-Pole System
When is reduced,
the system becomes
more stable.
Assumption:
does not depend
on frequency.
The system is stable since the

loop gain is less than 1 at a frequency
For which the angle(H())=-180.
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The pole locations of the classical second-order homogeneous

system
The locations of the poles are
If =0, s1,2=p1,p2
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If 1, corresponding to an
overdamped system, the two
poles are real and lie in the lefthalf
plane
For an underdamped system, 0 <

1, the poles form a complex
conjugate pair,
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Transient Response Versus

PM
Peaking is usually correlated with ringing in

the time domain!
PM=60o, usually the optimum value.

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Frequency Compensation
Reason for frequency compensation:

|H()| does not drop to unity when <H()
reaches -180o.
Possible Solution:
(Push PX Out)
(push GX in)
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20
Miller Theorem
The method that transforms a floating capacitor to

two grounded capacitors, thereby allowing association
of one pole with each node
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Two stage OTA

Without Rz
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Small signal analysis
The small signal transfer function for

the two stage miller compensation
Compensation capacitor (Cc)

between the output of the gain
stages causes pole-splitting and
achieves dominant pole
compensation.
The first pole is located at
The second pole is located at
An RHP zero exists at
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23
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Pole splitting with Cc
Pole splitting with gm2
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What is the origin of

the positive zero??
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26
Origin of positive zero

This is the result of the
feedforward current
which adds extra phase
margin -90deg
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Types of compensation
techniques
The different types of compensation circuit to remove zero is
With nulling resistor
With current buffer
With voltage buffer
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With the nulling resistor

This resistor causes some
cancellation of the effect of the
feedforward by the
feedback.
If Rc=1/gm2 ; Z=infinity
If Rc>1/gm2 ; Z=LHP
Z=1/Rc*Cc
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Max and Min Rc

Let us assume that
Z>=10GBW
7/5/15
30
Design plan
Let us assume that
Z>=10GBW
For 60deg phase margin we have
Cc>0.22CL
I5=SR*Cc
For M5
For M6
For M3,M4
For M3,M4
For M1,M2
Gain
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Another choice of Rc is to make z1 cancel

P2:
z1=gm6/CC(1-gm6Rz) - gm6/(CL+C1)
CC+CL+C1
Rc =
gm6CC
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Optimum design for high

GBW
WKT
Assume
Therefore
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33
Nulling resistor
Devices
(W/L)1,2
Values
(W/L)um
12/0.4
(W/L)3,4
42/0.8
(W/L)5
18/1
(W/L)6
22/0.16
(W/L)7
23/1
7/5/15
34
With current buffer
The compensation current is indirectly feedback from low impedance

node
The RHP pole zero can be eliminated as the feedforward current is
blocked by the common gate amplifier
Node V1 is now not loaded by the compensation capacitor (as previously)
and thus results in a much faster second stage and increased unity gain
frequency
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Small Signal Analysis
TAKING KCL AT EACH

NODE
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36
Simplified Transfer
Function
The transfer function can be
simplified and approximated as:-
The coefficients can be evaluated

as
Evaluating the poles and zeros
Assuming the pole |p1| >> |p2|, |p3|
The denominator can now be

approximated
Complex Poles
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bserving the Pole/Zero

Locations
The third order transfer function as 3 poles and 1 zero

Dominant Pole location
Remains at the same location
Non-dominant poles are complex conjugate

Condition For complex Poles
LHP Zero Location
Improves Phase Margin

7/5/15
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Analytical Results Summary

Complex
conjugate
Pole / Zero Location
X
Z=UGB
X
X
Dominat pole
Quick Facts
Complex P2,P3 moved to much
higher frequency
Z=UGB
Complex Poles Condition
LHP zero improves the phase

margin near UGB
Much faster op-amp with lower
power and CC
7/5/15
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Design plan
gm2
<-Noise
Cc
<- UGB
Id1
<-SR=Id1/Cc
(W/L)1,2
P2=2UGB<-For 60deg PM
gm2
<-gm2=4gm1
Id2
<-SR=Id2/CL
(W/L)6
Gmc=gm1 <-Assume Z=UGB

Id1=Idc
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Current buffer
Devices
(W/L)1,2
Values
(W/L)um
72/0.8
(W/L)3,4
48/0.8
(W/L)5
12/1
(W/L)6
84/0.15
(W/L)7
36/1
(W/L)8 (CG)
12/0.6
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41
Voltage buffer
Devices
(W/L)1,2
Values
(W/L)um
16/0.8
(W/L)3,4
38/0.8
(W/L)5
16/1
(W/L)6
34/0.15
(W/L)7
26/1
(W/L)8 (VB)
14/0.6
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Results
With current buffer
DC GAIN
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Settling time
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Slew Rate
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Current buffer
Parameter
UGB
Simulated
values
1GHz
DC gain
59.8dB
PM
61.12deg
Cc
0.4pF
Settling time
3.4ns(2%)
Slew Rate
707V/us
Pdiss
2.66mW
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With nulling resistor
Parameter
UGB
Nulling
resistor
235MHz
DC gain
61dB
PM
60.15deg
Cc
1.2pF
Pdiss
1.94mW
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With voltage follower
Parameter
UGB
Nulling
resistor
478MHz
DC gain
54dB
PM
60.9deg
Cc
0.7pF
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Comparison
Parameter
UGB
Nulling
resistor
235MHz
Voltage
follower
Current buffer
478.84MHz
1GHz
DC gain
61dB
54.4dB
59.8dB
PM
60.15deg
60.9deg
61.12deg
Cc
1.2pF
700fF
400fF
Pdiss
1.94mW
2.22mW
2.66mW
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Layout of current buffer
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Conclusion
The three compensated OTA is compared
with gain, UGB, Power dissipation,PM.
We can observe that Cc of current buffer is
reduced to 0.4fF when compared to Cc of
nulling resistor of 1.2pF.
Current buffer compensated OTA there is
improvement in the gain, UGB, PM and area
requirement is also less compared to nulling
resistor compensated OTA.
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52
References
[1] G. Palmisano, and G. Palumbo, A compensation strategy for two-stage CMOS
opamps based on current buffer, IEEE Transactions on Circuits and Systems IFundamental Theory and Applications, vol. 44, no. 3, pp. 257-262, Mar, 1997.
[2] P. E. Allen, and D. R. Holberg, CMOS analog circuit design, 2nd ed., New York: Oxford
University Press, 2002.
[3] B. K. Ahuja, An Improved Frequency Compensation Technique for CMOS OperationalAmplifiers, IEEE Journal of Solid-State Circuits, vol. 18, no. 6, pp. 629-633, 1983.
[4] H. Lee, and P. K. T. Mok, Active-feedback frequency-compensation technique for lowpower multistage amplifiers, IEEE Journal of Solid-State Circuits, vol. 38, no. 3, pp.
511-520, 2003.
[5] P. J. Hurst, S. H. Lewis, J. P. Keane et al., Miller compensation using current buffers in
fully differential CMOS two-stage operational amplifiers, IEEE Transactions on
Circuits and Systems I-Regular Papers, vol. 51, no. 2, pp. 275-285, 2004.
[6] H. Mahattanakul, and J. Chutichatuporn, Design procedure for two-stage CMOS
opamp with flexible noise-power balancing scheme, IEEE Transactions on Circuits
and Systems I-Regular Papers, vol. 52, no. 8, pp. 1508-1514, 2005.
7/5/15
53
THANK YOU
7/5/15
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High speed op amp with different

Op Amps are the most versatile and integral part of many

They are employed from dc bias application to high speed

General purpose op amps can be used as summer, buffer,

Therefore from the above eqn we can

Biasing for high speed

Must use minimum length devices

Larger overdrive results in faster circuits

Open loop gain trends in future

The projection of open-loop voltage gain drops

To design the high speed two stage op amp

and the optimized layout design.

= 1.8V +/- 10%

The location of the poles of a closed

one pole system is

The system is stable since the

The pole locations of the classical second-order homogeneous

The locations of the poles are

For an underdamped system, 0 <

Transient Response Versus

Peaking is usually correlated with ringing in

PM=60o, usually the optimum value.

Reason for frequency compensation:

The method that transforms a floating capacitor to

Two stage OTA

Small signal analysis

The small signal transfer function for

Compensation capacitor (Cc)

The second pole is located at

An RHP zero exists at

Pole splitting with Cc

Pole splitting with gm2

What is the origin of

Origin of positive zero

With nulling resistor

With current buffer

With voltage buffer

With the nulling resistor

Max and Min Rc

Another choice of Rc is to make z1 cancel

Optimum design for high

With current buffer

The compensation current is indirectly feedback from low impedance

Small Signal Analysis

TAKING KCL AT EACH

The coefficients can be evaluated

The denominator can now be

bserving the Pole/Zero

The third order transfer function as 3 poles and 1 zero

Non-dominant poles are complex conjugate

LHP Zero Location

Improves Phase Margin

Analytical Results Summary

Pole / Zero Location

Complex Poles Condition

LHP zero improves the phase

Gmc=gm1 <-Assume Z=UGB

With current buffer

With nulling resistor