Objective. Block Diagram. Design Aspects of Noc.: Routing Algorithms. Flow Control. Error Control Scheme

CONTENTS
Objective.
Introduction.
Block Diagram.
Design Aspects of NoC.
Routing algorithms.
Flow control.
Error control scheme.
BiNoC Router Architecture.

Channel direction control.
Work done and works to be done.
Simulation results.
Design Requirements.
Conclusion.
References
1
Objectives
To develop a prototype of bidirectional NoC
communication having
reconfigurable channels.
dynamically
self
To increase the noise toleration capability of
the system using a hybrid scheme of error

correction and retransmission.
INTRODUCTION
SoC Integrating all the components of an
electronic system in a single chip.

Inter processor communication - An important design
issue.
Traditional on-chip communication methods-global
bus, Point to Point Links.
NoC- Communication Backbone In SoC.
Basic Tiled NoC

Architecture
ADVANTAGES
Commonly used NoC
architecture
Simple and scalable
High performance
DISADVANTAGES
No effective resource
utilization.
Less bandwidth utilization.
Channel Overflow occurs
BLOCK DIAGRAM
3*3 grid structure of bidirectional NoC
Design aspects of NoC

Topology.
Routing.
Flow Control.
Noise toleration.
Topology
Commonly Used
Topologies
2D mesh topology
Torus topology
Ring topology
2D mesh topology
Advantages
2D mesh topology
Simplicity.
High degree of scalability.
7
Routing Algorithms
Determines The Path Selected By a Packet To
Reach Its Destination.

Oblivious routing and adaptive routing.
Oblivious Routing
Path Uniquely Defined By Source And Destination.
Adaptive Routing
Path chosen based on network conditions.

Path might be changed within network to avoid
congestion.
Oblivious Routing
Algorithms
No Information About Conditions
Of
The
Network, Like Traffic Amounts Or Congestions.

Simplest Oblivious Routing Algorithm- Minimal
Turn Routing (Example Dimension Order Routing)

Dimension Order Routing(DOR)- Determines The
Direction Of Packet During Every Stage Of

Routing
9
XY routing algorithm
Type Of Dimension Order
Routing.
Routes Packets First in X

(Horizontal Direction)
Then In Y(vertical
Direction).
XY Routing Suits Well On

a Network Using Mesh
Or Torus Topology.
XY routing
10
Flow control
Network
flow
Determines How
inside a Network.
control(routing
mode)Packets are Transmitted
Routing modes
Store-and-Forward Routing.
Virtual Cut-Through Routing.
Wormhole Routing.
11
Wormhole Routing
Packets are Divided To Small And Equal Sized
Flits(flow Control Unit).

Wormhole Mode Requires Less Memory.
Latency Is Less.
12
Flit structure
Header flit
LSB
MSB
8 bit Source
address
8 bit destination
address
Tail flit
0 1
LSB
MSB
Data
Data flit
1 1
LSB
MSB
Data
13
Error control Scheme

Using hamming code Single error correction
double error detection(SEC-DED).

Hybrid
Scheme- Combination Of Error

Correction Scheme And
Retransmission
Scheme.
Increases
the noise toleration capability
Not
Ideal.
Switch Drops The Packet In Case Of Uncorrectable
Erroneous Header Flit.
14
SEC DED hamming code

Hamming code can be converted to a SEC-
DED code by adding one more check bit which

is a parity bit.
Can detect up to two bit errors .
Correction is possible only for 1 bit error.
15
Error Control Policies
Switch-to-Switch Error Control Policy
Flits are encoded and decoded at each hop.

Area overhead 4 encoders, 4 decoders and Extended
Buffer Registers
Delay Overhead Per Flit - Nmax (TEncoder + TDecoder),
Nmax is the maximum number of hops made by a flit
End-to-End Error control policy .

One Encoder And One Decoder Are Needed To Be
Connected To The NI (Network Interface).
Area Overhead -One Encoder, One Decoder And
Extended Buffer Registers.
Additional Delay Overhead Per Flit TD.-Flit = TEncoder +
TDecoder
16
BiNoC ROUTER
ARCHITECTURE
17
Channel Direction
Channel direction controlled using two finite
control(CDC)
state machines(FSMs)
High priority FSM
Low priority FSM
Hp FSM 3states.
LP FSM 3 states.
Inter router channel direction control
18
HP FSM
LP FSM
19
Work in progress
Work done:
Developed a basic 5 port router used in tiled NoC

architecture.
Developed the channel direction control scheme using
CDC protocol.
Works to be done:
Develop a BiNoC router by integrating the CDC protocol

concept with the basic router structure.
Develop the bidirectional NoC model by interconnecting
the routers in mesh topology.
Design the Noise toleration scheme to increase the
reliability of the System
20
BASIC NoC ROUTER ARCHITECTUR
21
Inter Router Channel Direction

Control
Output_request
input_request
Channel_request
Channel_request
HP FSM
Din_1
Dout_1_1
input_request
Output_request
LP FSM
Dout_2_1
Channel-1
Dout_1_2
Dout_2_2
Channel-2
input_request
Din_2
Output_request
LP FSM
HP FSM
Output_request
input_request
CLOCK
22
Simulation results
Simulation Result : FIFO buffer
Data input to buffer
Read enable signal
Data Output from buffer
Write enable signal
Data getting stored in inner registers of buffer
Buffer empty signal Buffer Full signal

23
Simulation result: XY logic
Input header flit
X coordinate of destination address

Y coordinate of destination address North_out
South_out
east_out
West_out
local_out
24
Simulation Result : Rotating priority

arbiter
25
Simulation Result: 5 port basic NoC

router
West_in
local_in
North_in
East_in
West_out
South_in
local_out North_out
East_out
South_out
26
Contd..
Input port
Header flit injected
XY address of
destination
XY address of local
router
Output port
WEST
00001111000011
11010001000101
(1,1)
(1,1)
LOCAL
LOCAL
11110000111100
00010001010001
(4,1)
(1,1)
SOUTH
NORTH
11111111000000
00010010000101
(1,2)
(1,1)
EAST
EAST
11111111000000
00010000000001
(0,0)
(1,1)
WEST
SOUTH
00001111000011
11010001000001
(0,1)
(1,1)
NORTH
27
Simultaneous multiple request handling in

NoC Router
West_in
local_in
North_in
West_out
East_in
South_in
local_out North_out
East_out
South_out
28
Contd..
West_in
local_in
North_in
West_out
east_in
South_in
South_out
local_out North_out
East_out
29
Contd..
West_in
local_in
North_in
West_out
East_in
South_in
local_out North_out
East_out
South_out
30
Contd..
Input Port
WEST
LOCAL
NORTH
EAST
SOUTH
Header Flit Injected
11111111000000
00010010000101
00000000111111
11010010000101
01010101010101
01010010000101
11110000111100
00010001010001
00110011001100
11000010000101
XY Address Of
Destination
XY Address Of
Local Router
Output Port
Order Of
Grant
(1,2)
(1,1)
EAST
(1,2)
(1,1)
EAST
(1,2)
(1,1)
EAST
(4,1)
(1,1)
SOUTH
(1,2)
(1,1)
EAST
31
Channel direction
Configuration
Channel_1-right
Channel_2-left
Channel_2 -right
Channel_2- left
Channel_1-left
32
Contd
Channel_1-left
Channel_1-right
Channel_2-left
33
TOOLS REQUIRED
Xilinx ISE design suite 12.1
Modelsim SE plus 6.2c
34
Conclusion
Designed a basic five port NoC router using
VHDL and simulated the results.

Designed the CDC scheme for inter router
channel direction control at run time.
35
Reference
[1] Y. C. Lan, S. H. Lo, Y. C. Lin, Y. H. Hu, and S. J. Chen, BiNoC: A bidirectionalNoC
architecture with dynamic self-reconfigurable channel, IEEE Trans. Comput.-Aided
Des,vol. 30, No. 3, Pp. 421434, March 2011.
[2] Design and Analysis of On-Chip Router for Network On Chip International
Journal of Computer Trends and Technology- July to Aug Issue 2011
[3] A Survey of Architectural Design and Implementation Tradeoffs in Network on
Chip Systems Dan Marconett University of California, Davis, CA 95616, USA .
[4] L. Benini and G. De Micheli, Networks on chips: a new SoC paradigm, IEEE
Transactions on Computers, vol. 35, no. 1, pp. 7078, 2002.
[5] Networks on Chips: Structure and Design Methodologies Hindawi Publishing
Corporation
Journal of Electrical and Computer Engineering, Volume 2012, Article ID 509465
36
Contd..
[6]Simulation & Synthesis of Five Port Router Swati Malviya (M.Tech. -Digital
Communication) Anurag Jaiswal (Capgemini Consulting India Pvt. Ltd., Former
HOD-IT, FMS, MITS University).
[7] Network on Chip Routing Algorithms TUCS Technical Report No 779, August
2006
[8] Davide Bertozzi, Luca Benini,Error Control Schemes for On-Chip
Communication,Links: The EnergyReliability Tradeoff IEEE Trans. Comput.Aided Des. Vol. 24, No. 6, June 2005.
[9] Error Correction Techniques on NoC Protocol Layers Ahmed Garamoun ,
Haupt-Seminar
Reliable Networks-on-Chip in the Many-Core Era, University of Stuttgart.
37
THANK YOU
38

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CONTENTS

BiNoC Router Architecture.

To increase the noise toleration capability of

the system using a hybrid scheme of error

electronic system in a single chip.

Basic Tiled NoC

3*3 grid structure of bidirectional NoC

Design aspects of NoC

Reach Its Destination.

Path Uniquely Defined By Source And Destination.

Path chosen based on network conditions.

Network, Like Traffic Amounts Or Congestions.

Turn Routing (Example Dimension Order Routing)

Direction Of Packet During Every Stage Of

Routes Packets First in X

XY Routing Suits Well On

Flits(flow Control Unit).

Error control Scheme

double error detection(SEC-DED).

Scheme- Combination Of Error

the noise toleration capability

SEC DED hamming code

DED code by adding one more check bit which

Error Control Policies

Switch-to-Switch Error Control Policy

Flits are encoded and decoded at each hop.

Nmax is the maximum number of hops made by a flit

End-to-End Error control policy .

High priority FSM

Low priority FSM

Developed a basic 5 port router used in tiled NoC

Develop a BiNoC router by integrating the CDC protocol

BASIC NoC ROUTER ARCHITECTUR

Inter Router Channel Direction

Data input to buffer

Read enable signal

Data Output from buffer

Write enable signal

Data getting stored in inner registers of buffer

Buffer empty signal Buffer Full signal

Simulation result: XY logic

Input header flit

X coordinate of destination address

Simulation Result : Rotating priority

Simulation Result: 5 port basic NoC

Header flit injected

Simultaneous multiple request handling in

Header Flit Injected

VHDL and simulated the results.

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