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    A Seminar Report On Vlsi Floorplanning

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    PARAG
    This document describes a seminar presentation on using a clonal selection algorithm for VLSI floorplanning design. [1] It introduces the problem of floorplanning and presents a clonal selection algorithm to optimize module placement and minimize dead space. [2] Experimental results on benchmark circuits like ami33 and ami49 show the algorithm can iteratively reduce costs and find optimal or near-optimal solutions. [3] The clonal selection approach is an efficient method for VLSI floorplanning that merits further investigation to decrease whitespace values.

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    A Seminar Report On Vlsi Floorplanning

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    PARAG
    147 views17 pages
    This document describes a seminar presentation on using a clonal selection algorithm for VLSI floorplanning design. [1] It introduces the problem of floorplanning and presents a clonal selection algorithm to optimize module placement and minimize dead space. [2] Experimental results on benchmark circuits like ami33 and ami49 show the algorithm can iteratively reduce costs and find optimal or near-optimal solutions. [3] The clonal selection approach is an efficient method for VLSI floorplanning that merits further investigation to decrease whitespace values.

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    A Seminar Report on Vlsi Floorplanning

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    This document describes a seminar presentation on using a clonal selection algorithm for VLSI floorplanning design. [1] It introduces the problem of floorplanning and presents a clonal selection algorithm to optimize module placement and minimize dead space. [2] Experimental results on benchmark circuits like ami33 and ami49 show the algorithm can iteratively reduce costs and find optimal or near-optimal solutions. [3] The clonal selection approach is an efficient method for VLSI floorplanning that merits further investigation to decrease whitespace values.

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    © All Rights Reserved
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    Download as pptx, pdf, or txt
    147 views17 pages

    A Seminar Report On Vlsi Floorplanning

    Uploaded by

    PARAG
    This document describes a seminar presentation on using a clonal selection algorithm for VLSI floorplanning design. [1] It introduces the problem of floorplanning and presents a clonal selection algorithm to optimize module placement and minimize dead space. [2] Experimental results on benchmark circuits like ami33 and ami49 show the algorithm can iteratively reduce costs and find optimal or near-optimal solutions. [3] The clonal selection approach is an efficient method for VLSI floorplanning that merits further investigation to decrease whitespace values.

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    You are on page 1of 17

    A SEMINAR PRESENTATION ON

    VLSI Floorplanning Design Using Clonal Selection


    Algorithm
    CONTENTS

     Introduction
     Preminaries
    • Floorplan Cost
    • Cost Function
    • Clonal Selection Algorithm
     Experimental Result
    • Benchmark Dataset
    • Test Results
     Conclusion
     References
    Introduction

    Floorplanning is an essential design step in physical design of VLSI circuits to plan


    the positions of a set of circuit modules on a chip in order to optimize the circuit
    performance. A Clonal Selection Algorithm for VLSI floorplanning problem is
    presented. The Clonal Selection Algorithm has been implemented and tested on
    various popular benchmarks. Experimental results show that the Clonal Selection
    Algorithm can produce optimal or nearly optimal solutions for all the benchmark
    problems.
    Preminaries

     Floorplan Cost.
     Cost Function.
     Clonal Selection Algorithm.
    Floorplan Cost

    The goal of floorplanning is to optimize a predefined cost function. The


    floorplan area directly correlates to the silicon chip cost. The space in the
    floorplan bounding rectangle uncovered by any module is called white
    space or dead space.
    Cost Function

    The quality of the floorplan can be evaluated on the basis of several


    objectives such as area minimization, power minimization and combination of
    these. We used the following cost function to evaluate the floorplan -
    c(x)= σni=1 wi hi
    where, n is the number of modules & wi and hi are the width and height of
    the divided region respt.
    Because module rotation is allowed, we might have two possible floorplan
    implementations (w,h) and (h,w), for a module of the dimension (w,h).
    Clonal Selection Algorithm

    First we have taken each of the benchmark data and create a random initial
    population and then we iteratively apply mutation and crossover on it. At
    each iteration the population should be improved and it is shown in
    experiment result that with every iteration the dead/ white space of the
    floorplan decreases.
    Initialization of clonal selection algorithm is given in Algorithm 1 and
    mutation algorithm is given in Algorithm 2.
    Algorithm 1: Initialization of clonal selection algorithm

    i <= number of module end while


    j <= 1 j <= 1
    while i ≤ n do while i <= root + 1 AND i ≤ n do
    while j ≤ n do place (i) top of j
    Find j with maximum width[j] waste <= width(j) - width(i)
    swap(j,i) k <= i
    end while i <= i + 1
    i <= i + 1 while waste ≥ width(i) do
    end while place (i) right of k
    while i <= root + 1 AND i ≤ n do waste <= waste - width(i)
    sort according to height k <= i
    end while i <= i + 1
    place(1) end while
    i <= 2 , j <= 1 end while
    while i ≤ root do
    place(i) right of j
    j <= i
    i <= i + 1
    Algorithm 2 :Mutation of clonal selection Algorithm

    i <= number of module


    while i ≤ n do
    For waste top of i find a block j whose height/affinity
    is height to cover the white space
    Mutate by placing j top of i
    Calculate change of white space for mutation
    end while
    while i ≤ n do
    For waste right of i find a block j whose height/affinity
    is height to cover the white space
    Mutate by placing j right of i
    Calculate change of white space for mutation
    end while
    Experimental Result

    A) Benchmark Dataset:
    The benchmark is used as test circuits to evaluate the performance of the
    proposed methodology in this report. The circuit characteristics are presented
    in Table 1

    Circuit No. of modules Area (sq.mm)

    ami33 33 1.16
    ami49 49 35.4
    apte 9 46.56
    hp 11 8.30
    xerox 10 19.35
    Fig.1: A representation of development process of cost reduction by
    clonal selection algorithm testing on ami33 dataset through step Initial
    Population and consecutive Iterations.
    Fig.2: A representation of development process of cost reduction by
    clonal selection algorithm testing on ami49 dataset through step Initial
    Population and consecutive Iterations.
    B) Test Results

    Table 2 shows the development of floorplan by clonal Table 2 shows the cost or dead space of VLSI
    selection algorithm for ami33 and ami49 dataset. floorplanning for different benchmark dataset

    Circuit step1 step2 step3 step4 step5 step6 Benchmark Dataset Dead Space/Cost(in
    percentage %)
    ami33 34.27 28.34 16.50 16.50 16.50 16.50 ami33 16.50

    ami49 25.44 25.44 16.83 14.668 14.668 14.668 ami49 14.668

    apte 6.154

    hp 18.524

    xerox 22.551
    Graph of development process of cost Graph of development process of cost
    reduction by clonal selection algorithm testing reduction by clonal selection algorithm testing
    on ami33 dataset on ami49 dataset
    Conclusion

    This paper has shown the experimental results on different benchmark data,
    using clonal selection for VLSI floorplanning. Minimizing the total area is the
    principal objective of most existing floorplanners. Minimization of the total area is
    helpful to minimize chip size, and thus cost. This work represents the first effort
    towards efficient Clonal Selection for VLSI floorplanning. There are some
    interesting issues that need to be further investigated. For eg. the value of
    whitespace can be further decreased by applying a more advanced algorithm.
    References

     Deen Md Abdullah, Wali Md Abdullah, Noor Mohammad Babu,Md.


    Momenul Islam Bhuiyan, Kazi Munshimun Nabi, M. Sohel Rahman,” VLSI
    Floorplanning Design using Clonal Selection Algorithm,” Informatics,
    Electronics and Vision(ICIEV),2013 International Conference.
     T. Chen and Y. Chang, Electronic Design Automation Synthesis,
    Verification,and Test. Morgan Kaufmann, 2009.
     A. Ranjan, K. Bazargan, S. Ogrenci, and M. Sarrafzadeh, “Fast floorplanning
    for effective prediction and construction,” IEEE Trans. on Very Large Scale
    Integration (VLSI) Systems, vol. 9, no. 2, pp. 341–351, 2001.
     W. Wolf, Modern VLSI Design: System-on-Chip Design, Third Edition. Prentice
    Hall, 2002.
    Thank You

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