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    Cts Cmnds

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    sravan
    This document discusses clock skew and latency in a digital design. It mentions that clock latency is made up of the source latency plus network latency. It also notes that clock buffers and inverters are used in clock tree synthesis to help reduce skew and that the design uses three clocks - two running at 250MHz and one at 125MHz.

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    Cts Cmnds

    Uploaded by

    sravan
    92 views6 pages
    This document discusses clock skew and latency in a digital design. It mentions that clock latency is made up of the source latency plus network latency. It also notes that clock buffers and inverters are used in clock tree synthesis to help reduce skew and that the design uses three clocks - two running at 250MHz and one at 125MHz.

    Original Description:

    CTS Commands in PD

    Original Title

    cts cmnds

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    This document discusses clock skew and latency in a digital design. It mentions that clock latency is made up of the source latency plus network latency. It also notes that clock buffers and inverters are used in clock tree synthesis to help reduce skew and that the design uses three clocks - two running at 250MHz and one at 125MHz.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    92 views6 pages

    Cts Cmnds

    Uploaded by

    sravan
    This document discusses clock skew and latency in a digital design. It mentions that clock latency is made up of the source latency plus network latency. It also notes that clock buffers and inverters are used in clock tree synthesis to help reduce skew and that the design uses three clocks - two running at 250MHz and one at 125MHz.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
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    Clock skew and latency

    Clock latency =source+network


    •Clock buffers and clock inverters used in clock
    Tree synthesis
    Using clustering based tree
    Clock buffers and clock inv used in CTS
    :Report_clocks
    Clocks used in design:3
    2(250mhz),125mhz

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