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    Distributed Embed Ed System

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    Vidya Bagal
    1. Distributed embedded systems consist of physically distributed processing elements that communicate over interconnects and networks. This allows for data reduction at the source, reduced load on single processors, and improved modularity and fault tolerance. 2. Common network architectures for distributed embedded systems include I2C, CAN, SHARC link ports, Ethernet, Myrinet, and the Internet. These networks vary in speed, topology, arbitration, and other features. 3. Designing distributed embedded systems requires analyzing communication requirements, system performance, hardware platforms, and allocating and scheduling tasks across processing elements. Load balancing is important for efficient system design.

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    Distributed Embed Ed System

    Uploaded by

    Vidya Bagal
    24 views27 pages
    1. Distributed embedded systems consist of physically distributed processing elements that communicate over interconnects and networks. This allows for data reduction at the source, reduced load on single processors, and improved modularity and fault tolerance. 2. Common network architectures for distributed embedded systems include I2C, CAN, SHARC link ports, Ethernet, Myrinet, and the Internet. These networks vary in speed, topology, arbitration, and other features. 3. Designing distributed embedded systems requires analyzing communication requirements, system performance, hardware platforms, and allocating and scheduling tasks across processing elements. Load balancing is important for efficient system design.

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    1. Distributed embedded systems consist of physically distributed processing elements that communicate over interconnects and networks. This allows for data reduction at the source, reduced load on single processors, and improved modularity and fault tolerance. 2. Common network architectures for distributed embedded systems include I2C, CAN, SHARC link ports, Ethernet, Myrinet, and the Internet. These networks vary in speed, topology, arbitration, and other features. 3. Designing distributed embedded systems requires analyzing communication requirements, system performance, hardware platforms, and allocating and scheduling tasks across processing elements. Load balancing is important for efficient system design.

    Copyright:

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    24 views27 pages

    Distributed Embed Ed System

    Uploaded by

    Vidya Bagal
    1. Distributed embedded systems consist of physically distributed processing elements that communicate over interconnects and networks. This allows for data reduction at the source, reduced load on single processors, and improved modularity and fault tolerance. 2. Common network architectures for distributed embedded systems include I2C, CAN, SHARC link ports, Ethernet, Myrinet, and the Internet. These networks vary in speed, topology, arbitration, and other features. 3. Designing distributed embedded systems requires analyzing communication requirements, system performance, hardware platforms, and allocating and scheduling tasks across processing elements. Load balancing is important for efficient system design.

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    Distributed Embedded Systems

    Need for DES:

    Different task are physically distributed (location wise)


    Data reduction (Initial signal processing at event place)
    Reduces load on single processor
    Modularity is maintain
    Easier to debug
    Fault tolerance can be maintain
    Distributed Embedded Architectures

    Interconnection between Processing Elements (PE)


    Communication between PE
    Physically separated PE have interaction
    One part of system can be used to diagnose problems in another
    part
    Reusability increases
    Network Abstraction

    Application Layer End user Interaction


    Presentation Layer Data Formats
    Session Layer Dialog controls
    Transport Layer Connections
    Network Layer End to End Service
    Data Link Layer Reliability
    Physical Layer Mech/Electrical spects

    OSI Model
    Hardware and Software Architecture
    P-P Communication
    Simplex
    Duplex Half/Full
    Buses
    Use for communication
    uses packets
    have some payload
    Arbitration Fixed priority
    Fair arbitration (Round Robin-No starvation)
    Network
    Dataflow
    Single stage/Multistage
    Networks for Embedded Systems

    •I2C Bus

    •CAN Bus

    •SHARC Link Ports

    •Ethernet

    •Myrinet

    •Internet
    I2C (Inter IC)Bus

    SDL: Serial Data Line


    SCL: Serial Clock line

    S Address WR-0 Data S Address WR-0 Data P


    RD - 1 RD - 1 (Slave)
    1 7 1 7 1 7 1 7 bits 1
    Physical Layer
    Low cost and easy to implement
    Moderate speed (upto 100 kbps for Std)(400 kbps for
    extended)
    Uses 2 lines SDL Serial Data Line
    SCL Serial Clock Line
    Every node is connected to both lines (SDL, SCL)
    Multi master Bus: More than one master
    Master: Initiates data
    Slave: Only responds to request from master
    Master is responsible to generate SCL clocks(High)
    Slave can stretch low period of clock
    Data Link Layer
    Every device is determine by unique address
    Addr-7 bits long
    1 bit –data direction 0:M---S and 1:S---M
    Data push programming style is used (polling method)

    1 7 1 1
    S Addr W/ Data P
    R

    0-W, 1-R
    An I2C Interface in a Microcontroller
    CAN (Controller Area Network)
    Physical Layer
    Designed for Automotive Electronics
    Uses serial bit transmission
    Speed 1Mbps over twisted pair max of 40 meters
    Multi master Bus: supports multiple masters
    Logical 1-Recessive and 0-Dominant
    Synchronous Bus
    Data Link Layer
    uses CSMA/AMP (Arbitration on message priority)

    S-0
    P-0000000
    Remote Transmission Request (RTR) 0-Read, 1-Write

    1 12 6 0-64bits 16 2 7
    S Arbitration Control DATA CRC ACK P

    Identifier Data
    length
    Architecture of CAN Controller
    SHARC link Ports

    Ceramic Quad Flat Pack (CQFP) System:


    Interconnection through serial ports
    Peak rates 120MFlops to 480 MFlops
    SHARC Link Ports
    Uses Multiprocessor Communication
    High Speed ports (120-480 Mflops)
    6 Link Ports are available
    Data Transfer are packed into 32/48 bit word
    Link Ports are in Half Duplex
    Token Passing between the processors
    Link Ports can target the DMA transfers
    Ethernet

    Uses CSMA/CD
    Network is Not Synchronized
    Low Cost
    Bus with Single Path
    Uses Twisted Pair/ Co-Ax Cable

    Ethernet Organization
    Ethernet Packet format

    Preamble Start Dest. Source Length Data Padding CRC


    frame Addr Addr

    Ethernet CSMA/CD Algorithm


    Myrinet

    Very High Speed Network (640 Mbps)


    Operates in Full Duplex Mode
    BW 1.28 Gbps
    Use parallel processing
    High performance network system
    Uses packet transmission
    Internet

    Node A Node B
    Application Application

    Presentation Presentation

    Session Session
    Router
    Transport Transport

    Network Network Network

    Data Link Data Link Data Link

    Physical Physical Physical


    Internet

    IP Packet Structure

    Header Service
    Version Total Length
    length type

    Identification Flags Fragment Offset

    Time to Live Protocol Header Check Sum

    Source Address

    Destination Address

    Option and Padding

    Payload Data
    Uses IP
    Uses Routers
    Uses Network Layer
    32 bits for IPV4 and 128 bits for IPV6

    FTP HTTP SMTP Telnet SNMP

    TCP UDP

    IP

    Internet Service Pack


    Network Based Design

    • Communication Analysis
    • System Performance Analysis
    • Hardware platform Design, Allocation and Scheduling
    Communication Analysis

    Message Delay
    Tm = Tx + Tn + Tr
    where Tx = Transmitter side overhead
    Tn = Network transmission time
    Tr = Receiver side overhead

    Total delay
    T = Td + Tm
    Where Td = Network availability delay
    Tm = message delay
    Td depends on the arbitration used (fixed priority or fair (RR))
    PE 1 PE 1

    PE 1

    PE 1 PE 1

    • Single-hop communication Networks


    • Multi-hop communication networks
    System Performance Analysis
    Simple task graph

    Tp1 Tp2
    nTx
    P1 P2

    Distributed system with multi-rate concurrency

    PE 2
    PE 1 P2 PE 3
    P1 P3
    P4
    Hardware platform Design, Allocation and Scheduling
    Hardware platform issues
    • Number of PEs required
    • Types of all PEs
    • Number of networks used
    • Type of networks

    Efficient system design issues

    • I/O - intensive system design


    • Computation - intensive design system

    Load Balancing is a good idea for the Design of DES


    I/O - intensive system design
    • Inventory the require I/O devices
    • Determining the I/O to connect to network or not (local/remote
    processing)
    • Analyze communication time
    • Allocate minimum required PE
    • Design communication intensive processes

    Computation - intensive system design


    • Start with task with shortest deadlines (Scheduling overheads)
    • Analyze critical communication time
    • Allocate lower priority tasks to shared PEs where possible

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