MSI
MSI
MSI
Acknowledgement
• The contents of these slides have origin from School of
Computing, National University of Singapore.
• We greatly appreciate support from Mr. Aaron Tan Tuck
Choy for kindly sharing these materials.
© IT - TDT Computer Organisation 3
MSI COMPONENTS
• Introduction
• Decoders
• Encoders
• Demultiplexers
• Multiplexers
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INTRODUCTION
• Four common and useful MSI circuits:
• Decoder
• Demultiplexer
• Encoder
• Multiplexer
decoder encoder
code entity entity code
select select
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DECODERS (1/5)
• Codes are frequently used to represent entities, eg: your
name is a code to denote yourself (an entity!).
• These codes can be identified (or decoded) using a
decoder. Given a code, identify the entity.
• Convert binary information from n input lines to (maximum
of) 2n output lines.
• Known as n-to-m-line decoder, or simply n:m or nm
decoder (m 2n).
n
• May be used to generate 2 minterms of n input variables.
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DECODERS (2/5)
• Example: If codes 00, 01, 10, 11 are used to identify four
light bulbs, we may use a 2-bit decoder.
2x4
F0 Bulb 0
2-bit X Dec F Bulb 1
1
code Y
F2 Bulb 2
F3 Bulb 3
DECODERS (3/5) X
0
Y F0
0 1
F1 F2 F3
0 0 0
0 1 0 1 0 0
• From truth table, circuit for 1 0 0 0 1 0
24 decoder is: 1 1 0 0 0 1
F2 = XY'
F3 = XY
X Y
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DECODERS (4/5)
• Design a 38 decoder.
F0 = x'y'z'
x y z F0 F1 F2 F3 F4 F5 F6 F7
0 0 0 1 0 0 0 0 0 0 0
F1 = x'y'z
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
F2 = x'yz'
0 1 1 0 0 0 1 0 0 0 0
F3 = x'yz
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
F4 = xy'z'
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1 F5 = xy'z
F6 = xyz'
F7 = xyz
x y z
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DECODERS (5/5)
• In general, for an n-bit code, a decoder could
n
select up to 2 lines:
n-bit n to 2n up to 2n
code : decoder : output lines
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2x4
Dec 0 F4 = wx'y'
S1 1 F5 = wx'y
S0 2 F6 = wxy'
E 3 F7 = wxy
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2x4
w Dec 0 F0 = w'x'y'
x S1 1 F1 = w'x'y
y S0 2 F2 = w'xy'
E 3 F3 = w'xy
2x4
Dec F4 = wx'y'
S1 F5 = wx'y
S0 F6 = wxy'
E F7 = wxy
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3x8
Dec 0 F8
S2
1 F9
S1 : :
S0 7 F15
E
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(c)
(a) Active-high decoder with OR gate. (b) Active-low decoder with NAND gate.
0 0
3x8 1 3x8 1
Dec 2 f(Q,X,P) Dec 2
f(Q,X,P)
Q A 3 Q A 3
B 4 B 4
X X
5 5
P C 6 P C 6
7 7
(c) Active-high decoder with NOR gate. (d) Active-low decoder with AND gate.
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READING ASSIGNMENT
• Reducing Decoders
• Read up DLD pg 136 – 140.
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ENCODERS (1/4)
• Encoding is the converse of decoding.
• Given a set of input lines, of which exactly one is high, the
encoder provides a code that corresponds to that input
line.
n
• Contains 2 (or fewer) input lines and n output lines.
• Implemented with OR gates.
• Example:
F0 D0
Select via F1 4-to-2
switches 2-bits
F2 Encoder D1 code
F3
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ENCODERS (2/4)
F0 F1 F2 F3 D1 D0
• Truth table: 1 0 0 0 0 0
0 1 0 0 0 1
0 0 1 0 1 0
With K-map, we obtain: 0 0 0 1 1 1
D0 = F1 + F3 0 0 0 0 X X
D1 = F2 + F3 0 0 1 1 X X
0 1 0 1 X X
0 1 1 0 X X
Circuit: 0 1 1 1 X X
1 0 0 1 X X
1 0 1 0 X X
1 0 1 1 X X
1 1 0 0 X X
1 1 0 1 X X
1 1 1 0 X X
1 1 1 1 X X
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ENCODERS (3/4)
• Example: Octal-to-binary encoder.
• At any one time, only one input line has a value of 1.
• Otherwise, we need priority encoder.
Inputs Outputs
D0 D1 D2 D3 D4 D5 D6 D7 x y z
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
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ENCODERS (4/4)
• Example: Octal-to-binary encoder.
D0
D1 x = D 4 + D5 + D6 + D7
D2
D3 y = D 2 + D3 + D6 + D7
D4
D5
D6
D7 z = D 1 + D3 + D5 + D7
An 8-to-3 encoder
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DEMULTIPLEXERS (1/2)
• Given an input line and a set of selection lines, a
demultiplexer directs data from the input to one selected
output line.
• Example: 1-to-4 demultiplexer.
Outputs
Y0 = D∙S1'∙S0' S1 So Y0 Y1 Y2 Y3
0 0 D 0 0 0
Y1 = D∙S1'∙S0
Data D demux
0 1 0 D 0 0
Y2 = D∙S1∙S0' 1 0 0 0 D 0
Y3 = D∙S1∙S0
1 1 0 0 0 D
S1 S0
select
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DEMULTIPLEXERS (2/2)
• It turns out that the demultiplexer circuit is actually
identical to a decoder with enable.
24 0 Y0 = ?
Decoder
S1 A 1 Y1 = ?
S0 B 2 Y2 = ?
E 3 Y3 = ?
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MULTIPLEXERS (1/5)
• A multiplexer is a device which has
• A number of input lines
• A number of selection lines
• One output line
n
• It steers one of 2 inputs to a single output line, using n
selection lines. Also known as a data selector.
n
2 :1
inputs Multiplexer output
:
...
select
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MULTIPLEXERS (2/5)
• Truth table for a 4-to-1 multiplexer:
I0 I1 I2 I3 S1 S0 Y S1 S0 Y
d0 d1 d2 d3 0 0 d0 0 0 I0
d0 d1 d2 d3 0 1 d1 0 1 I1
d0 d1 d2 d3 1 0 d2 1 0 I2
d0 d1 d2 d3 1 1 d3 1 1 I3
Inputs Inputs
I0 0 I0
I1 4:1 I1
1 4:1
MUX Y
I2 2 Y Output I2 mux
I3 3 I3
S1 S0
S1 S0
select select
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S1 S0 Y
MULTIPLEXERS (3/5) 0 0 I0
0 1 I1
• Output of multiplexer is
1 0 I2
“sum of the (product of data lines and selection lines)” 1 1 I3
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MULTIPLEXERS (4/5)
• A 4:1 multiplexer circuit:
I0 I0
I1 I1
Y Y
I2 I2
I3 I3
0 1 2 3
2-to-4
Decoder
S1 S0 S1 S0
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MULTIPLEXERS (5/5)
• An application:
MULTIPLEXER IC PACKAGE
• Some IC packages have a few multiplexers in each
package (chip). The selection and enable inputs are
common to all multiplexers within the package.
A0
Y0
A1
Y1
A2
Y2
A3
Y3
B0
B1 E’ S Output Y
1 X all 0’s
B2 0 0 select A
B3 0 1 select B
S
(select)
E' Quadruple 2:1 multiplexer
(enable)
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I0 S2 S1 S0 Y
I1 4:1 0 0 0 I0
I2 MUX
I3 0 0 1 I1
0 1 0 I2
2:1 0 1 1 I3
S1 S0 MUX Y
I4
1 0 0 I4
I5 1 0 1 I5
4:1
I6 1 1 0 I6
MUX S2
I7 1 1 1 I7
S1 S0
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(b)
(c)
74151A 8-to-1 multiplexer. (c) Logic diagram. (d) Generic logic symbol.
(e) IEEE standard logic symbol.
Source: The TTL Data Book Volume 2. Texas Instruments Inc.,1985.
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MULTIPLEXERS: IMPLEMENTING
FUNCTIONS (1/3)
• Boolean functions can be implemented using
multiplexers.
n
• A 2 -to-1 multiplexer can implement a Boolean function of
n input variables, as follows:
1. Express in sum-of-minterms form. Example:
F(A,B,C) = A'B'C + A'BC + AB'C + ABC'
= S m(1,3,5,6)
2. Connect n variables to the n selection lines.
3. Put a ‘1’ on a data line if it is a minterm of the function, or ‘0’
otherwise.
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MULTIPLEXERS: IMPLEMENTING
FUNCTIONS (2/3)
• F(A,B,C) = S m(1,3,5,6)
0
1
0
1
This method works because:
0 2
F
Output = m0I0 + m1I1 + m2I2 + m3I3
1 3 mux
0 4 + m4I4 + m5I5 + m6I6 + m7I7
1 5
1
0
6
7 Supplying ‘1’ to I1,I3,I5,I6 , and ‘0’ to
A B C
the rest:
Output = m1 + m3 + m5 + m6
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MULTIPLEXERS: IMPLEMENTING
FUNCTIONS (3/3)
• Example: Use a 74151A to implement
f(x1,x2,x3) = S m(0,2,3,5)
1 0
1 1
0 2 1 0
1 3 mux F C 1 F
0 4 mux
0 5 0 2
1 6 C' 3
0 7
A B C A B
MUX
A B C F
input
0 0 0 1 ? 0
0 0 1 1 ? 1 F
mux
0 1 0 0 ? 2
0 1 1 1 ? 3
1 0 0 0
1 0 1 0 A B
1 1 0 1
1 1 1 0
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B C
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S0 0 1024 – 2047
1 DATA (8) (8)
S1 2 ADRS (10)
3 CS
1K x 8
RW
2048 – 3071
Read/write DATA (8) (8)
ADRS (10)
CS
1K x 8
RW
3072 – 4095
DATA (8)
(8)
ADRS (10)
CS
1K x 8 Output
RW
data
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1
Add M
u
x
4 ALU 0
Add result
RegWrite Shift
left 2
Instruction [5– 0]
ALUOp
© IT - TDT Computer Organisation 57
Q&A