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    The document provides an introduction to the 8086 microprocessor, describing its key features and architecture. The 8086 has a 16-bit arithmetic logic unit and 20-bit address bus. It contains two main parts - the bus interface unit which fetches instructions and handles memory addressing, and the execution unit which decodes and executes instructions. The document outlines the various registers used by the 8086 and describes its addressing modes and common assembly pseudo instructions.

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    3 MP

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    The document provides an introduction to the 8086 microprocessor, describing its key features and architecture. The 8086 has a 16-bit arithmetic logic unit and 20-bit address bus. It contains two main parts - the bus interface unit which fetches instructions and handles memory addressing, and the execution unit which decodes and executes instructions. The document outlines the various registers used by the 8086 and describes its addressing modes and common assembly pseudo instructions.

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    The document provides an introduction to the 8086 microprocessor, describing its key features and architecture. The 8086 has a 16-bit arithmetic logic unit and 20-bit address bus. It contains two main parts - the bus interface unit which fetches instructions and handles memory addressing, and the execution unit which decodes and executes instructions. The document outlines the various registers used by the 8086 and describes its addressing modes and common assembly pseudo instructions.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    28 views19 pages

    3 MP

    Uploaded by

    sn
    The document provides an introduction to the 8086 microprocessor, describing its key features and architecture. The 8086 has a 16-bit arithmetic logic unit and 20-bit address bus. It contains two main parts - the bus interface unit which fetches instructions and handles memory addressing, and the execution unit which decodes and executes instructions. The document outlines the various registers used by the 8086 and describes its addressing modes and common assembly pseudo instructions.

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    An Introduction to

    8086 Microprocessor.
    8086 Microprocessor
    8086 Features

    • 16-bit Arithmetic Logic Unit


    • 16-bit data bus (8088 has 8-bit data bus)

    • 20-bit address bus - 220 = 1,048,576 = 1 meg


    8086 Architecture

    • The 8086 has two parts, the Bus Interface Unit (BIU) and the
    Execution Unit (EU).

    • The BIU fetches instructions, reads and writes data, and computes the
    20-bit address.

    • The EU decodes and executes the instructions using the 16-bit ALU.

    • The BIU contains the following registers:

    IP - the Instruction Pointer


    CS - the Code Segment Register
    DS - the Data Segment Register
    SS - the Stack Segment Register
    ES - the Extra Segment Register

    The BIU fetches instructions using the CS and IP, written CS:IP, to contract
    the 20-bit address. Data is fetched using a segment register (usually the DS)
    and an effective address (EA) computed by the EU depending on the
    addressing mode.
    The EU contains the following 16-bit registers:

    AX - the Accumulator
    BX - the Base Register
    CX - the Count Register
    DX - the Data Register
    SP - the Stack Pointer \ defaults to stack segment
    BP - the Base Pointer /
    SI - the Source Index Register
    DI - the Destination Register

    These are referred to as general-purpose registers, although, as seen by


    their names, they often have a special-purpose use for some instructions.

    The AX, BX, CX, and DX registers can be considers as two 8-bit registers, a
    High byte and a Low byte. This allows byte operations and compatibility with
    the previous generation of 8-bit processors, the 8080 and 8085. 8085 source
    code could be translated in 8086 code and assembled. The 8-bit registers are:

    AX --> AH,AL
    BX --> BH,BL
    CX --> CH,CL
    DX --> DH,DL
    ES Extra Segment
    BIU registers CS Code Segment
    SS Stack Segment
    DS Data Segment
    IP Instruction Pointer

    EU registers AX AH AL Accumulator
    BX BH BL Base Register
    CX CH CL Count Register
    DX DH DL Data Register
    SP Stack Pointer
    BP Base Pointer
    SI Source Index Register
    DI Destination Index Register
    FLAGS
    8086/88
    8086/88internal
    internalregisters
    registers16
    16bits
    bits(2
    (2bytes
    byteseach)
    each)

    AX, BX, CX and DX are two


    bytes wide and each byte can
    be accessed separately

    These registers are used as


    memory pointers.

    Flags will be discussed later

    Segment registers are used


    as base address for a segment
    in the 1 M byte of memory
    Intel

    Memory Address Generation


    • The BIU has a dedicated adder for
    determining physical memory addresses
    Offset Value (16 bits)

    Segment Register (16 bits) 0000

    Adder

    Physical Address (20 Bits)


    20 bit address lines  1MB memory
    divided into 16 logical segments of size 64 KB

    1) Segment Register indicates the base address of a particular segment.


    2) Offset address indicates the distance of the required memory location
    in the segment from the base address.

    Generation of 20 Bit Physical Address.

    If Segment Address  1005 H


    Offset Address  5555H
    Segment Address  1005 H  0001 0000 0000 0101
    Shifting Segment Address
    to the Left Bit Wise by 4 times 0001 0000 0000 0101 0000
    +
    Offset Address  5555H 0101 0101 0101 0101

    ________________________

    0001 0101 0101 1010 0101

    1 5 5 A 5 H
    • Status flags: Flags
    Flags
    – They are set according to some results of arithmetic operation. You do
    not need to alter the value yourself.
    • Control flags:
    – Used to control some operations of the MPU.

    Carry flag
    Overflow
    Direction Parity flag

    Interrupt enable Auxiliary flag


    6 are status flags Trap Zero
    3 are control flag
    Sign
    Flag O D I T S Z A P C

    Bit no. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
    • CF (carry) Contains carry from leftmost bit following arithmetic, also
    contains last bit from a shift or rotate operation.
    • OF (overflow) Indicates overflow of the leftmost bit during arithmetic.
    • DF (direction) Indicates left or right for moving or comparing string data. DF =0
    autoinc… DF=1 auto decrem.
    • IF (interrupt) Indicates whether external interrupts are being processed or ignored.
    • TF (trap) Permits operation of the processor in single step mode.

    • SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)

    • ZF (zero) Indicates when the result of arithmetic or a comparison is zero. (1=yes)

    • AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized arithmetic.

    • PF (parity) Indicates the number of 1 bits that result from an operation.


    Addressing Modes:
    1)It describes the types of operand and the way they are accessed for executing an
    instruction.
    2) MOV (OPCODE or Operation Code) AX,BX (Operand)
    3) Types 1) Immediate MOV AX,0005H
    2) Direct MOV AX,[5000H] offset address is directly given
    Physical address 10*H DS+5000H
    3) Register MOV BX,AX all reg. except IP may be used.
    4) Register Indirect MOV AX,[BX]
    Physical address 10*H DS+[BX]
    5) Indexed MOV AX,[SI]
    Physical address 10*H DS+[SI]
    6) Register Relative MOV AX,50H[BX]
    Physical address 10*H DS+50H+[BX]
    7) Based Indexed MOV AX,[BX][SI]
    Physical address 10*H DS+ [BX]+[SI]
    8) Relative Based Indexed MOV AX,50H[BX][SI]
    Physical address 10*H DS+[BX]+[SI]+50H
    9) Intrasegment Direct Mode
    10) Intrasegment InDirect Mode
    11) Intersegment Direct Mode
    12) Intersegment InDirect Mode
    ASM PSEUDOINSTRUCTIONS

    1.Define Byte/Word/Double word DB/DW/DD


    2. Segment and Ends
    3. Assume.
    4.End
    5.Procedure & EndP
    6.ORG
    7.GLOBAL & Local
    8.EQU
    9.EVEN
    10.EXTRN and Public
    11.Group
    12.Label
    13.PTR
    mov dl,00h
    mov ax,0ffffh
    mov bx,0aaaah
    add ax,bx
    jnc l1
    inc dl
    l1: hlt
    count equ 03h
    mov dx,count-1
    l1: mov cx,dx
    mov si,5000h Input 5000 – 3010
    l2: mov ax,[si] 5002 -- 1010
    cmp ax,[si+2] 5004 -- 2010
    jnc l3
    xchg [si+2],ax Output ???
    xchg [si],ax
    l3: add si,02
    loop l2
    dec dx
    jnz l1
    hlt

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