8085 Complete Architecture
8085 Complete Architecture
8085 Complete Architecture
Presented By:
Branch : Electrical Engineering Aditya Mehra(130120109001)
Div: B Rijay Doshi(130120109007)
Batch : B1 Jay Kared (130120109016)
PRESENTATION ON :
8085 ARCHITECTURE
• Stack pointer maintains the address of the last byte that is entered into stack.
• Each time when the data is loaded into stack, Stack pointer gets decremented.
• It accepts data from instruction decoder and generates micro steps to perform it
,in addition it accepts clock inputs for synchronizing operations.
• This unit consists of an oscillator and controller sequencer which sends control
signals needed for internal and external control of data and other units.
• X1 and X2:-
• This pin is used for providing the clock frequency to the
microprocessor. Generally Crystal oscillator or LC
oscillator is used to generate the frequency. The frequency
generated here is internally divided into two. As we know
that the basic operating timing frequency of the
microprocessor is 3 MHz so 6 MHz frequency is applied.
• Address Bus:
• A8 - A15: (output; 3-state)
• It carries the most significant 8 bits of the memory address or the 8 bits
of the I/O address.
• Data bus:
• AD0 - AD7 (input/output; 3-state)
• These multiplexed set of lines used to carry the lower order 8 bit
address as well as data bus.
• During the opcode fetch operation, in the first clock cycle, the lines
deliver the lower order address A0 - A7.
• In the subsequent IO / memory, read / write clock cycle the lines are
used as data bus.
• The CPU may read or write out data through these lines.
Control and Status signals:
• ALE (output) - Address Latch Enable.
• It is an output signal used to give information of AD0-A
D7 contents.
• It is a positive going pulse generated when a new
operation is started by microprocessor.
• When pulse goes high it indicates that AD0-AD7 are
address.
• When it is low it indicates that the contents are data.
• RD (output 3-state, active low)
• Read memory or IO device.
• This indicates that the selected memory location or
I/O device is to be read and that the data bus is ready
for accepting data from the memory or I/O device