ARM Cortex-M: External Interrupt & Keil C Debug
ARM Cortex-M: External Interrupt & Keil C Debug
ARM Cortex-M: External Interrupt & Keil C Debug
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ARM Cortex-M
External Interrupt & Keil C debug
Stacking Unstacking
NVIC automatically starts to the stacking Automatically pops the values of
process, and pushes registers to preserve the these registers out of the stack. The
running environment. Status register (xPSR), NVIC recovers the processor’s
Program counter (PC), Link Register (LR), state or called running environment.
R12, R3, R2, R1, R0 From R0 xPSR
ISR
NVIC changes the status of Interrupt from pending state to active state.
NVIC forces the processor to branch to the interrupt handler, and starts to execute the
interrupt handler. The interrupt service routine completes its execution by running the
following instruction: BX LR
Nested in Interrupts
Preemption
Tail chaining
External interrupt
The external interrupt controller consists of up to 19
edge detectors for generating interrupt requests
GPIO mode:
- External Interrupt Mode with Rising edge trigger detection
- External Interrupt Mode with Falling edge trigger detection
- External Interrupt Mode with Rising/Falling edge trigger detection
GPIO Pull-up/Pull-down:
- No Pull-up and No Pull-down
- Pull – up
- Pull - Down
NVIC CONFIGURATION
Keil Debugger Tutorial
Software vs Hardware Debug
Debug Control
Click the debug button to start the debug and click it again
to exit the debug.
• Run: Continues the execution from the current position until you click
Stop or the program is paused by a breakpoint.
• Step In: Execute one step and enter the function if the current step
calls a function.
• Step Over: Execute one step and run the function all at once if the
current step calls a function.
Disassembly window
Breakpoint
Source window
Peripheral Registers
From the menu: Peripherals ⟶ System Viewer, we can view and update
the control and data registers of all available peripherals
Watch Window