ARM PROCESSOR

ARM Architecture
 Based on RISC architecture with
enhancements to meet requirements of
embedded applications
o A large uniform register file
o Load/store architecture
o Uniform and fixed length instructions
o 32 bit processor
o Good speed/power consumption ratio
o High code density
 Load-store architecture
 Instruction set will only process (add, subtract
and so on) values which are in registers and
place the results into a register
 The operations which apply to memory state are
o the ones which copy memory values into
registers(load instructions)
o or copy register values into memory (store
instructions)
 LOAD-STORE ARCHITECTURE
CONT…
ARM instructions fall into one of the
following categories
1. Data processing instructions(use and
change only register values)
2. Data transfer instructions(load and store
instructions)
3. Control flow instructions[branch instructions,
branch and link instructions(similar to
interrupt) or supervisor calls
 ENHANCEMENTS TO BASIC RISC
FEATURES
 Control over ALU and shifter for every data
processing operations to maximize there
usage
 Auto-increment and auto-decrement
addressing modes to optimize program loops
 Multiple Load/Store data elements to
maximize throughput
 Conditional execution of instruction to
maximize throughput
 ARM Architecture Versions
 Version 1
o 26 bit addressing, no multiply or coprocessor
 Version 2
o Includes 32 bit result multiply co-processor
 Version 3
o 32 bit addressing
 Version 4
o Add signed, unsigned half word and signed byte load and store
instructions
 Version 4T
o 16 bit Thumb compressed form of instruction is introduced
 ARM Architecture Versions cont..
 Version 5T
o Superset of 4T adding new instruction
 Version 5TE
o Add signal processing extension
 Examples
o ARM6: v3
o ARM7: v3, ARM7TDMI:V4t
o StrongARM: v4
o ARM 9E-S:v5TE
 ARM Architecture Versions cont..
 ARM9TDMI
o T –Thumb 16 bit compressed instruction set
o D – on chip Debug request
o M – enhanced Multiplier(yields 64 bit result)
o I – Embedded ICE hardware to give on-chip
breakpoint and watchpoint support
 Overview: Core Data Path
 Data items are placed in register file
o No data processing instructions directly manipulate
data in memory
 Instructions typically use two source registers
and single result or destination register
 A Barrel shifter on the data path can pre-process
data before it enters ALU
 Increment/Decrement logic can update register
content for sequential access independent of
ALU
Basic ARM Organisation
 Registers
 General purpose registers hold either data or
address
 All registers are of 32 bits
 In user mode 16 data registers and 2 status
registers are visible
 Data registers: r0 to r15
o Three registers r13, r14 and r15 perform special
functions
o r13: stack pointer
o r14: link register (where return address is stored
whenever a subroutine is called)
o r15: program counter
 Registers contd..
 Depending upon context r13 and r14 can
also be used as GPR
 Any instruction which use r0 can as well
be used with any other GPR(r1-r13)
 In addition, there are two status registers
o CPSR: Current Program Status Register
o SPSR: Saved Program Status Register
 Register(r15)
• When the processor is executing in ARM
state
o All instructions are 32 bit wide
o All instructions are word aligned
o PC value is stored in bits[31:2] with bits [1:0]
undefined
 Program Status Registers
31 28 27 24 23 16 15 8 7 6 5 4 0

N Z C V U n d e f i n e d I F T mode
f s x c
• Condition code flags • Interrupt Disable bits.
– N = Negative result from – I = 1: Disables the IRQ.
ALU – F = 1: Disables the FIQ.
– Z = Zero result from ALU • T Bit
– C = ALU operation Carried – Architecture xT only
out – T = 0: Processor in ARM
– V = ALU operation state
oVerflowed – T = 1: Processor in Thumb
state

• Mode bits
– Specify the processor mode
 Processor modes
 Processor modes determine
o Which registers are active and
o Access rights to CPSR register itself
 Each processor mode is either
o Privileged: full read-write access to the CPSR
o Non-privileged: only read access to the
control field of the CPSR but read-write
access to the condition flags
 Processor modes contd..
 ARM has seven modes
o Privileged: abort, fast interrupt request,
interrupt request, supervisor, system and
undefined
o Non-privileged: user
 User mode is used for program and
applications
 Privileged modes
 Abort: when there is a failed attempt to
access memory
 Fast Interrupt Request (FIQ) & interrupt
request: correspond to interrupt levels
available on ARM
 Supervisor mode: state after reset and
generally the mode in which OS kernel
executes
 Privileged modes contd..
 System mode: special version of user
mode that allows full read-write access of
CPSR
 Undefined: When processor encounters
an undefined instruction
 Banked Registers
 Register file contains in all 37 registers
o 20 registers are hidden from program at
different times. These registers are called
banked registers
o Banked registers are available only when the
processor is in a particular mode
• Processor modes (other than system mode) have
a set of associated banked registers that are
subset of 16 registers
• Maps one-to-one onto a user mode register
 Register Banking
Current Visible Registers
Current Visible Registers User Registers replaced by
r0
User Mode
User r1
r0
r1
banked registers
r2
r2
r3 Banked out Registers
r4
r3 Banked out Registers
r4
r5
r5
r6
r6
FIQAbort FIQ
IRQ IRQ
SVC SVC
Undef Undef
Abort
r7
r7
r8 r8 r8
r8
r9 r9 r9
r9
r10 r10 r10
r10
r11 r11 r11
r11
r12 r12 r12
r12
r13 (sp) r13 (sp) r13r13
r13 (sp) (sp)
(sp) r13
r13 (sp)
(sp) r13
r13 (sp)
(sp) r13 r13
(sp)(sp)
r13 (sp)
CPSR r14 (lr) r14 (lr) r14r14
r14 (lr) (lr)
(lr) r14
r14 (lr)
(lr) r14
r14 (lr)
(lr) r14 r14
(lr)(lr)
r14 (lr)
copied r15 (pc)
r15 (pc)
into cpsr
SPSR spsr
cpsr spsr spsr
spsr spsr
spsr
spsr
spsr spsr
spsr
 SPSR
• Each privileged mode (except system
mode) has associated with it a SPSR (
Stored Program Status Register)
• This SPSR is used to save the state of
CPSR (Current Program Status Register)
when the privileged mode is entered in
order that the user state can be fully
restored when the user process is
resumed
 ARM Registers
System & User FIQ Supervisor Abort IRQ Undefined
R0 R0 R0 R0 R0 R0
R1 R1 R1 R1 R1 R1
R2 R2 R2 R2 R2 R2
R3 R3 R3 R3 R3 R3
R4 R4 R4 R4 R4 R4
R5 R5 R5 R5 R5 R5
R6 R6 R6 R6 R6 R6
R7 R7 R7 R7 R7 R7
R8 R8_fiq R8 R8 R8 R8
R9 R9_fiq R9 R9 R9 R9
R10 R10_fiq R10 R10 R10 R10
R11 R11_fiq R11 R11 R11 R11
R12 R12_fiq R12 R12 R12 R12
R13 R13_fiq R13_svc R13_abt R13_irq R13_und
R14 R14_fiq R14_svc R14_abt R14_irq R14_und
R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC)
CPSR CPSR CPSR CPSR CPSR CPSR
SPSR_fiq SPSR_svc SPSR_abt SPSR_irq SPSR_und
 Mode changing
• Mode changes by writing directly to CPSR
or by hardware when the processor
responds to exception (any condition that
needs to halt the normal sequential
execution of instructions) or interrupt
• To return to user mode a special return
instruction is used that instructs the core to
restore the original CPSR and banked
registers
 ARM Memory organisation
 Can be configured as little endian or big
endian
 Little endian
 Big endian
 Memory organization contd..
 "Little Endian" means that the low-order byte of the
number is stored in memory at the lowest address, and
the high-order byte at the highest address. (The little end
comes first.) For example, a 4 byte Long Int Byte3 Byte2
Byte1 Byte0 will be arranged in memory as follows:
o Base Address+0 Byte0
o Base Address+1 Byte1
o Base Address+2 Byte2
o Base Address+3 Byte3

 Intel processors (those used in PC's) use "Little Endian"

byte order.
 Memory Organization contd..
 "Big Endian" means that the high-order byte of
the number is stored in memory at the lowest
address, and the low-order byte at the highest
address. (The big end comes first.) Our Long Int,
would then be stored as:
o Base Address+0 Byte3
o Base Address+1 Byte2
o Base Address+2 Byte1
o Base Address+3 Byte0
 Motorola processors (those used in Mac's) use
"Big Endian" byte order.
 Which is better
 In "Little Endian" form, assembly language instructions for
picking up a 1, 2, 4, or longer byte number proceed in
exactly the same way for all formats: first pick up the
lowest order byte at offset 0. Also, because of the 1:1
relationship between address offset and byte number
(offset 0 is byte 0), multiple precision math routines are
correspondingly easy to write.
 In "Big Endian" form, by having the high-order byte come
first, you can always test whether the number is positive
or negative by looking at the byte at offset zero. You don't
have to know how long the number is, nor do you have to
skip over any bytes to find the byte containing the sign
information. The numbers are also stored in the order in
which they are printed out, so binary to decimal routines
are particularly efficient.
ARM INSTRUCTION SET
 Instructions
 Instructions process data held in registers
and access memory with load and store
registers
 Classes of instructions:
o Data processing
o Branch instructions
o Load-store instructions
o Software interrupt instructions
o Program status register instructions
 Features of arm instruction set
• 3 address data processing instruction
• Conditional execution of every instruction
• Load and store multiple registers
• Shift, ALU operation in a single instruction
• Open instruction set extension through the
coprocessor instruction
 ARM Data types
 Word is 32 bits long
 Word can be divided into four bytes
 ARM addresses can be 32 bit long
 Address refers to byte
o Address 4 starts at byte 4
 Can be configured at power up as little
endian or big endian mode
 Data Processing
 Manipulate data within registers
o MOVE instructions
o Arithmetic instructions
• Multiply instructions
o Logical instructions
o Comparison instructions
 Suffix S on data processing instructions
updates flags in CPSR
 Data processing instructions
• Operands are 32 bit wide; comes from
registers or specified as literal in the
instruction itself
• Second operand send to ALU via barrel
shifter
• 32-bit result placed in register; long
multiply instruction produces 64 bit result
 Move instruction
 MOV Rd, N
o Rd: Destination register
o N: can be an immediate value or source
register
o Example: mov r7, r5

o MVN Rd, N
o Move into Rd not of the 32-bit value from
source
 Using Barrel Shifter
 Enables shifting 32 bit operand in one of
the source registers left or right by a
specific no. of positions within the cycle
time of instructions
 Basic barrel shifter operations
o Shift left, shift right, rotate right
 Facilitates fast multiply, division and
increases code density
 Example : mov r7, r5, LSL #2
 Arithmetic instructions
 Implements 32 bit addition and subtraction
 3 operand form
 Examples
SUB r0, r1, r2
Subtract value stored in r2 from that of
r1 and store in r0
SUB r1, r1, #1
Subtract 1 from r1 and store result in r1
and update Z and C flags
 With Barrel shifter
 Use of barrel shifter with arithmetic and
logical instructions increases the set of
possible available operations
 Example
o ADD r0, r1, r1 LSL #1
o Register r1 is shifted to the left by 1, then it is
added with r1 and the result (3 times of r1) is
stored in r0.
 Multiply instructions
• Multiply contents of a pair of registers
Long multiply generates 64 bit result
 Examples
MUL r0, r1, r2
UMULL r0, r1, r2, r3
 Number of cycles taken for execution of
multiply instruction depends upon
processor implementation
 Multiply and Accumulate
• Result of multiplication can be
accumulated with content of another
register
– MLA Rd, Rm, Rs, Rn
• Rd = (Rm * Rs) + Rn

– UMLAL Rdlo, Rdhl, Rm, Rs

• [Rdhl, Rdlo] = [Rdhl, Rdlo] + [Rm*Rs]
 Logical instructions
 Bit wise logical operations on the two
source registers
o AND, OR , Ex-OR, bit clear
o Example : BIC r0, r1, r2
o r2 contains a binary pattern where every binary 1
in r2 clears a corresponding bit location in register
r1
o Useful in manipulating status flags and interrupt
masks
 Compare instructions
• Enables comparison of 32 bit values
– Updates CPSR flags but do not affect other
registers
– Examples
• CMP r0, r9
– Flags set as a result of r0 - r9
• TEQ r0, r9
– Flags set as a result of r0 ex-or r9
• TST r0, r9
– Flags set as a result of r0 & r9
 Summary
• We have examined basics of ARM
architecture
• Understood processor modes
• We have looked at core data path
• Discussed basic data processing
operations
LOAD/STORE INSTRUCTIONS
 Transfers data between memory and processor
registers
o Single register transfer
• Data types supported are signed and unsigned
words(32 bits), half-words and bytes
o Multiple-register transfer
• Transfers multiple registers between memory and the
processor in a single instruction
o Swap
• Swap content of a memory location with the contents of the
register
 Single Transfer instructions
 Load and Store data on a boundary alignment
o LDR, LDRH, LDRB;
• Load (word, half-word, byte)
o STR, STRH, STRB;
• Store (word, half-word, byte)
 Supports different addressing modes:
o Register indirect: LDR r0, [r1]
o Immediate: LDR r0, [r1, #4]
• 12 bit offset added to the base register
o Register operation: LDR r0, [r1, -r2]
• Address calculated using base register and another register
 More addressing modes
• Scaled
o Address is calculated using the base address
register and a barrel shift operation
• Pre and Post indexing
o Pre-index with write back: LDR r0, [r1, #4]!
• Updates the address base register with new
address
o Post index: LDR r0, [r1], #4
• Updates the address register after address is used
 Example
 Pre-indexing with write back
 LDR r0, [r1, #4]!
o Before instruction execution
• r0 = 0x00000000 r1 = 0x00009000
• Mem32[0x00009000] = 0x01010101
• Mem32[0x00009004] = 0x02020202
o After instruction execution
• r0 = 0x02020202
• r1 = 0x00009004
 Multiple Register Transfer
 Load-store multiple instructions transfer multiple
register contents between memory and the
processor in a single instruction
 More efficient – for moving blocks of memory,
saving and restoring context and stack
 These instructions can increase interrupt latency
o Usually instruction executions are not interrupted by
ARM
 Multiple Byte Load-Store
• Any subset of current bank of registers
can be transferred to memory or fetched
from memory
– LDM
– SDM
• The base register Rn determines source
or destination address
 Stack Processing
• A stack is implemented as a linear data
structure which grows up (ascending) or
down (descending)
• Stack pointer holds the address of the
current top of the stack
 Modes of Stack Operation
• ARM Multiple register transfer instructions
support
– Full ascending: grows up, SP points to the
highest address containing a valid item
– Empty ascending: grows up, SP points to the
first empty location above stack
– Full descending: grows down, SP points to the
lowest address containing a valid data
– Empty descending: grows down, SP points to
the first location below stack
 Some stack instructions
• Full Ascending
– LDMFA: translates to LDMDA (POP)
– STMFA: translates to STMIB (PUSH)
– SP points to last item in stack
• Empty Descending
– LDMED: translates to LDMIB (POP)
– STMED: translates to STMIA (PUSH)
– SP points to first unused location
 SWAP INSTRUCTION
• Special case of load store instruction
• Swap instructions
– SWP: swap a word between memory and
register
– SWPB: swap a byte between memory and
register
• Useful for implementing synchronization
primitives like semaphore
 Control Flow instructions
• Branch instructions
• Conditional branches
• Conditional execution
• Branch and link instructions
• Subroutine return instructions
 Branch instruction
• Branch instruction: B label
– Example: B forward
– Address label is stored in the instruction as a
signed pc-relative offset
• Conditional Branch: B <cond> label
– Example: BNE loop
– Branch has a condition associated with it and
executed if condition codes have the correct
value
 Example: Block memory copy
Loop LDMIA r9!, {r0-r7}
STMIA r10!, {r0-r7}
CMP r9, r11
BNE loop

r9 points to source of data, r10 points to start

of destination data, r11 points to end of the
source
 Conditional Execution
• An unusual feature of ARM instruction set
is that conditional execution applies not
only to branches but to all ARM
instructions
• Example: ADDEQ r0, r1, r2
– Instruction will only be executed when the
zero flag is set to 1
 Advantages
• Reduces the number of branches
– Reduces the number of pipeline flushes
– Improves performance of the code
• Increases code density
• Whenever the conditional sequence is 3
instructions or fewer (smaller and faster) to
exploit conditional execution than to use a
branch
 Branch and Link
• Perform a branch, save the address following
the branch in the link register, r14
– Example: BL subroutine
• For nested subroutine, push r14 and some work
registers required to be saved onto a stack in
memory
– Example
BL sub1
……….
STMFD r13!, (r0-r2, r14)
BL sub2
……….
 Subroutine return instructions
• No specific instructions
• Example(1):
sub …..
MOV PC, r14
• Example(2):
Sub2 …….
LDMFD r13!, (r0-r12, PC)
Software Interrupt Instruction(SWI)
• A software interrupt instruction causes a
software interrupt exception, which provides a
mechanism for moving the processor to move
from application routine to OS routines
• Instruction: SWI {<cond>} SWI_number
• When the processor executes an SWI
instruction, it sets the program counter to the
offset 0x08 in the vector table
• Instruction also forces the processor mode to
SVC, which allows an operating system routine
to execute
 SWI
• SWI is typically executed in user mode
• Instruction forces processor mode to supervisor
(SVC) – this allows an OS routine to be
executed in privileged mode
• Each SWI has an associated SWI number which
is used to represent a particular function call or
feature
• Parameter passing – through registers; Return
value is also passed using registers
 Example
• PRE: cpsr = nzcvqift_USER
• pc = 0x00008000
• lr = 0x003fffff (lr = r14)
• r0 = 0x12
• 0x00008000 SWR 0X123456
• POST: cpsr = nzcvqift_SVC
• Spsr = nzcvqift_USER
• pc = 0x00008004
• lr = 0x00008004 (lr = r14_SVC)
• r0 = 0x12
 Program Status Register
Instructions
• Two instructions to control PSR directly
• MRS – transfers register contents of either
cpsr or spsr into a register
• MSR – transfers contents to register to
cpsr or spsr
 Example
 Enabling IRQ interrupt
o PRE cpsr = nzcvqIFt_SVC
MRS r1, CPSR
BIC r1, r1, #0x80
MSR cpsr, r1
o POST cpsr = nzcvqiFt_SVC
o Instructions in SVC mode
 Coprocessor Instructions
• Used to extend the instruction set
– Used by cores with a coprocessor
– Coprocessor specific operations
• Syntax: Coprocessor data processing
– CDP{<cond>} cp, opcode1, Cd, Cn, Cm, {,opcode2}
• Cp represents coprocessor number between p0 to p15
• Opcode fields describes coprocessor operation
• Cd, Cn, Cm coprocessor registers
• Also coprocessor register transfer and memory
transfer instructions
 Thumb
• Thumb encodes a subset of the 32 bit
instruction set into a 16 bit subspace
• Thumb has higher performance than ARM
on a processor with a 16 bit data bus
• Thumb has a higher code density
– For memory constrained embedded system
 Code density
• ARM divide Thumb divide
MOV r3, #0 MOV r3, #0
Loop Loop
SUBS r0, r0, #1 ADD r3, #1
ADDGE r3, r3, #1 SUB r0, r1
BGE loop BGE loop
ADD r2, r0, r1 SUB r3, #1
ADD r2, r0, r1
5 x 4 = 20 bytes 6 x 2 = 12 bytes
 Thumb Instructions
• Only low registers r0 to r7 fully accessible
– Higher registers accessible with MOV, ADD,
CMP instructions
• Only branch instruction can be
conditionally executed
• Barrel shift operations are separate
instructions
 ARM-Thumb Interworking
• To call a Thumb routine from an ARM routine
the core has to change state
– Changing T bit in CPSR
• BX and BLX instruction can be used for the
switch
– Example: BX r0 ; BLX r0
– Enters Thumb state if bit 0 of the address in Rn is set
to binary 1; otherwise it enters ARM state
– Thumb
 Thumb (T) Architecture contd..
• Thumb instruction decoder is placed in
pipeline
• Change in Thumb mode happens by
changing the state of multiplexers A1
• A1 selects 16 bit data
Thumb (T) Architecture
 Thumb instruction set
• Instruction word length shrunk to 16-bits
• Instructions follow their own syntax but
each instruction has it’s native ARM
instruction counterpart
• Due to shrinking some functionality is lost
• 19 different Thumb instruction formats
Thumb Arm Instruction Mapping
• Example of instruction conversion
• Thumb-instruction ADD Rd,#constant is
converted to unconditionally executed
ARM-instruction ADD Rd,Rn,#constant
• Only the lower register set is in use so the
upper register bit is fixed to zero and
source and destination are equal. The
constant is also 8-bit instead of 12-bit
available in ARM-mode
Thumb Arm Instruction Mapping
 ARMv5E Extensions
• Extensions to facilitate signal processing
operations
• Supports
– Signed multiply accumulate instructions
– Saturation Arithmetic
– Greater flexibility and efficiency when
manipulating 16 bit values for applications
such as 16 bit digital audio processing
 Saturation Arithmetic
• Normal ARM arithmetic instructions wrap
around when there is an overflow of an
integer value
• Using ARMv5E instructions you can
saturate the result
– Once the highest number is exceeded the
result remains at the maximum value
– Minimum value does not change on overflow
• Example instructions: QADD, QSUB
 Summary
• We have studied instruction set of ARM
processors
• We have examined Thumb mode of
operation
• We shall look into interrupt processing and
other features of ARM architecture next
 ARM Exceptions: Review
Exception Mode
Fast Interrupt Request FIQ
Interrupt Request IRQ
SWI and Reset SVC
Pre-fetch Abort & Data Abort
Abort
Undefined instruction undefined
 When Exception Occurs…
• Exception causes mode change and
– Saves the cpsr to the spsr of the exception
mode
– Saves the pc to the lr of the exception mode
– Sets the cpsr to the exception mode
– Sets the pc to the address of the exception
handler
 Vector Table
• Vector table – a table of addresses that the ARM
core branches
– Fixed offset for each type of exception
• These addresses contain instruction of one of
the following forms:
– B <address> : branching relative to PC
– LDR pc, [pc, #offset] : loads handler address from
memory to PC
– MOV PC, #immediate : loads immediate value into
PC
 Exception Priorities
Exceptions Priority I bit Fbit
Reset 1 1 1
Data abort 2 1 -
FIQ 3 1 1
IRQ 4 1 -
Pre-fetch abort 5 1 -
SWI 6 1 -
Undefined
instructions 6 1 -
 Exception Handlers
• Reset handler
– Initializes the system, setting up stack pointers,
memory, external interrupt sources before enabling
IRQ or FIQ
– Code should be designed to avoid further triggering of
exceptions
• Data abort
– Occurs when memory controller indicates that an
invalid memory address has been accessed
– An FIQ exception can be raised within data abort
handler
 Exception Handlers (contd..)
• FIQ
– Occurs when an external peripheral generates the
FIQ input signal
– Core disables both FIQ and IRQ interrupts
• IRQ
– Occurs when an external device generates the IRQ
input signal
– IRQ handler will be entered if neither an FIQ
exception or Data abort exception occurs
– On entry IRQ exception is disabled and should remain
disabled for the handler if not enabled by the handler
 Exception Handlers (contd..)
• Prefetch Abort
– Occurs when an attempt to fetch an instruction results
in memory fault
– FIQ can be serviced
• Undefined instruction
– Occurs when an instruction is not in the ARM or
Thumb instruction
• SWI and undefined instruction have the same
level of priority because they cannot occur
together
 Returning from Exception Handler
• Exception handler must not corrupt lr
• After servicing is complete, return to
normal execution occurs
– By moving the correct value of link register
r14 into pc
– By restoring cpsr from spsr
 Interrupt Assignment
• An interrupt controller connects multiple
external interrupts to either FIQ or IRQ
• IRQ normally assigned to general purpose
interrupts
– Example: periodic timer interrupt to force a
context switch
• FIQ is reserved for an interrupt source
which requires fast response time
 Interrupt latency
• Hardware and software latency
• Software methods to reduce latency
– Nested handler which allows further interrupts to
occur even when currently servicing an existing
interrupt
• by re-enabling the interrupts as soon as the interrupt source
has been serviced but before interrupt handling is complete
• Once a nested interrupt has been serviced control is
relinquished to the original ISR
– Program interrupt controller to ignore interrupts of
same or lower priority
• Higher priority interrupts will have lower average latency
• Processor spends time in lower priority interrupts until higher
priority interrupts occur
 Stack Organisation
• For each processor mode stack has to be
set up
– To be done every time processor is reset
• Change to each mode by storing CPSR bit pattern
and initialize sp
• Design decisions
– Location and mode (descending stack is
common)
– Size
• Nested interrupt handler requires larger stack
 ARM I/O SYSTEM
• Handles all I/O devices using memory
mapped I/O
• Interrupt support:
– Fast interrupt
– Normal interrupt
• DMA transfer
– Large bandwidth data transfer
 ARM CPU CORE

Processor core + Cache + MMU

 ARM 7 Processor core
• Low-end ARM core for applications like mobile
phones
• TDMI
– T: Thumb
– D: On chip debug support for enabling processor to
halt in response to debug request
– M: Enhanced multiplier, yield a full 64 bit result
– I: Embedded ICE Hardware
• Von Neumann architecture
• 3 stage pipeline, CPI ~ 1.9
ARM ORGANISATION