Unit-6

CAD Tools
 Contents
• MOS layers, Stick/layout diagrams
• Layout Design rules
• Issues of Scaling, Scaling factors for device
parameters.
• Layout editors, Design rule checkers, circuit
extractors – Hierarchical circuit extractors
• Automatic layout tools, silicon compilers,
modelling and extraction of circuit parameters
from physical layout.
 Layout Design Rules
The design rules primary address two issues:
1. The geometrical reproduction of features that can be reproduced by the mask
making and lithographical process ,and
2. The interaction between different layers.
There are primarily two approaches in describing the design rules.
1. Linear scaling is possible only over a limited range of dimensions.
2. Scalable design rules are conservative .This results in over dimensioned and less
dense design.
1. Scalable Design Rules (e.g. SCMOS, λ-based design rules): In this approach, all
rules are defined in terms of a single parameter λ. The rules are so chosen that a
design can be easily ported over a cross section of industrial process ,making the
layout portable .Scaling can be easily done by simply changing the value of
2. Absolute Design Rules (e.g. μ-based design rules ) : In this approach, the
design rules are expressed in absolute dimensions (e.g. 0.75μm) and therefore
can exploit the features of a given process to a maximum degree. Here, scaling
and porting is more demanding, and has to be performed either manually or
using CAD tools .Also, these rules tend to be more complex especially for deep
submicron. The fundamental unity in the definition of a set of design rules is the
minimum line width .It stands for the minimum mask dimension that can be
safely transferred to the semiconductor material .Even for the same minimum
dimension, design rules tend to differ from company to company, and from
process to process. Now, CAD tools allow designs to migrate between compatible
processes
The basic separation and minimum size rules are:

• metal 1 Minimum width is 3 λ, minimum separation is 3 λ.

• metal 2 Minimum width is 3 λ, minimum separation is 4 λ.
• polysilicon Minimum width is 2 λ, minimum poly–poly separation is 2 λ.
• p-, n-diffusion Minimum width is 3 λ, minimum separation between same-
type diffusions is 3 λ, minimum p-diff–n-diff separation is 10 λ.
• tubs Tubs must be at least 10 λ wide. The minimum distance from the tub
edge to source/drain active area is 5 λ.
construction rules The basic construction rules are:

• transistors The smallest transistor is of width 3 λ and length 2 λ; poly

extends 2 λ beyond the active region and diffusion extends 3 λ. The active
region must be at least 1 λ from a poly-metal via, 2 λ from another
transistor, and 3 λ from a tub tie.
• vias Cuts are 2 λ X 2 λ; the material on both layers to be connected extends
1 λ in all directions from the cut, making the total via size 4 λ X 4 λ. (MOSIS
also suggests another via construction with 1.5 λ of material around the
cut. This construction is safer but the fractional design rule may cause
problems with some design tools.)
 Layout Design Rules contd..
• The design rules are usually described in two ways:
(i) Micron rules, in which the layout constraints such as minimum
feature sizes and minimum allowable feature separations are stated
in terms of absolute dimensions in micrometers, or,
(ii) Lambda rules, which specify the layout constraints in terms of a
single parameter (X) and thus allow linear, proportional scaling of all
geometrical constraints.

• Lambda-based layout design rules were originally devised to

simplify the industry- standard micron-based design rules and to
allow scaling capability for various processes.
• It must be emphasized, however, that most of the submicron CMOS
process design rules do not lend themselves to straightforward
linear scaling. The use of lambda-based design rules must therefore
be handled with caution in submicron geometries.
• (for continuation ref CMOS DIC-Yousuf Kang-chapter 2)
Scaling
 Layout editors
• A layout editor is an interactive graphic program that lets you create and
delete layout elements.
• Most layout editors work on hierarchical lay-outs, organizing the layout
into cells which may include both primitive layout elements and other
cells.
• Some layout editing programs, such as Magic, work on symbolic layouts,
which include somewhat more detail than do stick diagrams but are still
more abstract than pure layouts.
A via, for example, may be represented as a single rectangle while you
edit the symbolic layout; when a final physical layout is requested, the
sym-bolic via is fleshed out into all the rectangles required for your
process.
• Symbolic layout has several advantages: the layout is easier to specify
because it is composed of fewer elements; the layout editor ensures that
the layouts for the symbolic elements are properly constructed; and the
same symbolic layout can be used to generate several variations, such as
n-tub, p-tub, and twin-tub versions of a symbolic design.
 Design Rule Checkers
• A design rule checker (often called a DRC
program), as the name implies, looks for design
rule violations in the layout.
• It checks for minimum spacing and minimum size
and ensures that combinations of layers from
legal components.
• The results of the DRC are usually shown as
highlights on top of the layout.
• Some layout editors, including Magic, provide on-
line design rule checking.
•
DRC contd..
DRC is the area of Electronic Design Automation(EDA) that determines whether a particular chip layout satisfies a
series of recommended parameters called Design Rules. Design Rule checking is major step during physical
verification of the design, which also involves LVS(layout verses schematic) check, XOR checks, ERC(Electrical rule
check) and Antenna checks.
1) Logic DRC contain following 3 points:
• Net Fanout
• Net capacitance
• Net Transition
• Fixing Techniques:
1. Max Transition
Add a buffer in the middle of long length wire
Reduce the wire length
Adding a chain of buffers
2. Max capacitance
Decrease wire length at output side
3. Max Fanout
Clonning=adding a small cell load will be divided
Sharing the load
2) Physical DRC contains various rules, and it depends on technology, it is defined in technology file(tf file) , tf file
example:
Usually contain technology information such as: Min width of all layers
• Fat metal width spacing rule
• Fat metal extension spacing rule
• Maximum number minimum edge rule
• Adjacent Via rule
• Fat Metal contact rule
• Fat Metal extension contact rule
 DRC contd..

• Design rules are a series of parameters provided by semiconductor manufacturers that enable the
designer to verify the correctness of a mask set. Design rules are specific to a particular
semiconductor manufacturing process. A design rule set specifies certain geometric and
connectivity restrictions to ensure sufficient margins to account for variability in semiconductor
manufacturing processes, so as to ensure that most of the parts work correctly.
• The most basic design rules are shown in the diagram on the right. The first are single layer rules.
A width rule specifies the minimum width of any shape in the design. A spacing rule specifies the
minimum distance between two adjacent objects. These rules will exist for each layer of
semiconductor manufacturing process, with the lowest layers having the smallest rules (typically
100 nm as of 2007) and the highest metal layers having larger rules (perhaps 400 nm as of 2007).
• A two layer rule specifies a relationship that must exist between two layers. For example,
an enclosure rule might specify that an object of one type, such as a contact or via, must be
covered, with some additional margin, by a metal layer. A typical value as of 2007 might be about
10 nm.
• There are many other rule types not illustrated here. A minimum area rule is just what the name
implies. Antenna rules are complex rules that check ratios of areas of every layer of a net for
configurations that can result in problems when intermediate layers are etched. Many other such
rules exist and are explained in detail in the documentation provided by the semiconductor
manufacturer.
• Academic design rules are often specified in terms of a scalable parameter, λ, so that all geometric
tolerances in a design may be defined as integer multiples of λ. This simplifies the migration of
existing chip layouts to newer processes. Industrial rules are more highly optimized, and only
approximate uniform scaling. Design rule sets have become increasingly more complex with each
subsequent generation of semiconductor process
 Circuit Extractors
• Circuit extraction is an extension of design rule checking and uses similar
algorithms.
• A design rule checker must identify transistors and vias to ensure proper checks—
otherwise, it might highlight a transistor as a poly-diffusion spacing error.
• A circuit extractor performs a complete job of component and wire extraction.
• It produces a net list which lists the transistors in the layout and the electrical nets
which connect their terminals.
• Vias do not appear in the net list—a via simply merges two nets into a single larger
net.
• The circuit extractor usually measures parasitic resistance and capacitance on the
wires and annotates the net list with those parasitic values.
• The simplest extraction algorithm works on a layout without cells—this is often
called flat circuit extraction because the component hierarchy is flattened to a
single level before extraction
• However, a flattened layout is very large: a layout built of one 100 rectangle cell
repeated 100 times will have 100 rectangles plus 100 (small) cell records; the same
layout flattened to a single cell will have 10,000 rectangles
• The largest chips today need over one billion rectangles to describe their mask
sets. That added size claims penalties in disk storage, main memory, and CPU time
 Hierarchical circuit extraction

• Hierarchical circuit extraction extracts circuits

directly on the hierarchical layout description.
• Dealing with cell hierarchies requires more
sophisticated algorithms which are beyond our
scope.
• Hierarchical extraction may also require design
restrictions, such as eliminating overlaps between
cells.
• However, one problem which must be solved
• illustrates the kinds of problems introduced by
component hierarchies.
 Hierarchical circuit extraction contd..

• Consider the example above. Each cell has its own net list. The net lists of leaf cells make sense on
their own, but A’s net list is written in terms of its components.
• We often want to generate a flattened net list flattening the net list after extraction makes sense
because the net list is much smaller than the layout.
• To create the flattened net list, we must make correspondences between nets in the cells and nets
in the top-level component.
• Once again, we use transitive closure: if net o in cell B is connected to n2 in A, which in turn is
connected to net a in C, then B.o, A.n2, and C.a are all connected.
• Flattening algorithms can be very annoying if they choose the wrong names for combined
elements.
• In this case, n2, the top-level component’s name for the net, is probably the name most
recognizable to the designer.
 Hierarchical circuit extraction contd..
• A circuit extracted from layout has two important uses.
• First, the extracted circuit can be simulated and the results
compared to the specified circuit design. Serious layout errors, such
as a missing transistor or wire, should show up as a difference in
the specified and extracted circuits.
• Second, extracted parasitics can be used to calculate actual delays.
• Circuit performance may have been estimated using standard
parasitic values or parasitics may have been ignored entirely, but
long wires can slow down logic gates.
• Comparing the actual performance of the extracted layout to the
predicted performance tells you whether the logic and circuits need
to be modified and, if so, where critical delay problems exist.
 Automatic layout tools
• Hierarchical stick diagrams are a good way to
design large custom cells. But you will probably
design large cells from scratch infrequently.
• You are much more likely to use layouts
generated by one of two automated methods:
cell generators (also known macrocell
generators), which create optimized layouts for
specialized functions such as ALUs; or standard
cell placement and routing, which use algorithms
to build layouts from gate-level cells.
Automatic layout tools---Cell generator
• A cell generator is a parameterized layout—it is a program written
by a person to generate the layout for a particular cell or a families
of cells.
• The generator program is usually written textually, though some
graphical layout editors provide commands to create parameterized
layouts.
• If the generator creates only one layout, it may as well have been
created with a graphical layout editor.
• But designers often want to create variations on a basic cell:
changing the sizes of transistors, choosing the number of busses
which run through a cell, perhaps adding simple logic functions.
• Specialized functions like ALUs, register files, and RAMs often
require careful layout and circuit design to operate at high speed.
• Generator languages let skilled designers create parameterized
layouts for such cells which can be used by chip designers whose
expertise is in system design, not circuit and layout design.
 Automatic layout tools—standard cell place & route
• Place-and-route programs take a very different approach to layout
synthesis:
• they break the problem into placing components on the plane, then
routing wires to make the necessary connections.
• Placement and routing algorithms may not be able to match the quality of
hand designed layouts for some specialized functions, but they often do
better than people on large random logic blocks because they have
greater patience to search through large, unstructured problems to find
good solutions.
• The most common placement-and-routing systems use standard cells,
which are logic gates, latches, flip-flops, or occasionally slightly larger
functions like full adders.
• Figure below shows the architecture of a standard cell layout: the
component cells, which are of standard height but of varying width, are
arranged in rows; wires are run in routing channels between the cell rows,
along the sides, and occasionally through feedthroughs (spaces left open
for wires in the component cells).
• The layout is designed in two stages: components are placed using
approximations to estimate the amount of wire required to make the
connections; then the wires are routed.
 Silicon compilers
• A silicon compiler is a software system that takes a
user's specifications and automatically generates
an integrated circuit (IC). The process is sometimes
referred to as hardware compilation.
• Silicon compilation takes place in three major steps:
• Convert a hardware-description language such
as Verilog or VHDL or FPGAC into logic (typically in the
form of a “netlist").
• Place equivalent logic gates on the IC. Silicon compilers
typically use standard-cell libraries so that they do not
have to worry about the actual integrated-circuit layout
and can focus on the placement.
• Routing the standard cells together to form the desired
logic.
 Silicon compilers contd..
• The tool is used to generate low-level cells, and/or standard cells that are limited to ~10 to 40
transistors per cell, very quickly and efficiently while drawing all the layers required in a VLSI
process
• Silicon compilers require extensive and expert maintenance to be effective in a changing
environment. They provide the fastest cell generation possible. A standard cell library can be
generated in ~1 day while customizing the cells for a specific placer and/or routing tool.
• Applications for silicon compilers include the following:
• Standard cell libraries, where standardization of the pin assignment, cell height, abutment, etc., is
an important factor in layout design
• Cells for datapath, where the tool and design requirements have to be guaranteed and tailored to
specific designs
• • Any time speed is the most important factor in a layout generation
Some of the good features of silicon compilers are
• • Layout generation is fast, but the tools are expensive for a small company. For example, silicon
compilers for standard cell libraries are so expensive that only companies selling libraries as their
main product can justify their purchase.
• Only highly trained people in software, i.e., software engineers and/or designers with broad
background in software, can use the tools. They may know how to run the tool, but not necessarily
how the layout is supposed to look and be used.
• There are many internal tools inside big companies for this specific task that require a CAD group
to set up, develop, and maintain the design environment. Standard formats are used to interface
the output of silicon compilers with the other tools in the flow. The problem with using standard
formats is that specific information that is required for the compiler may be lost and the advantage
of using the tools defeated.
• They are so fast compared to full-custom polygon pushers that they have gained a lot of market-
share in the past 5 years. Silicon compilers can be used not only for layout generation, but for
process porting as well.
• Some compilers are targeted to specific applications: RAMs, ROMs, PLAs, I/O cells, standard cells,
datapath designs, etc. These compilers do not require as much training because they have been
designed for novice users.