Lecture 12

Stack and
Subroutines
1
Lecture 12(a)

The Stack
2
 The Stack
A stack is an area of memory that has been
reserved for access as a LIFO storage area.

3
 The Stack
A stack can grow up or down

Stack growing
upwards (higher BASE
addresses)  
 
 
 
 
END
END
 
 
 
 
Stack growing
 
downwards (lower
BASE
addresses)

4
 The Stack
In microprocessors, a register called a stack pointer
(SP) is used to store the address of the last occupied
memory on the stack.
Adding a data item to the stack is known as
pushing
The item is added to the next free location
The SP is updated to point to the new last item.
Removing a data item from the stack is known as
popping or pulling.
The item at the top of the stack is retrieved.
The SP is updated to point to the last valid item.

5
 Some activities
Push
PopAB
F into
to
change
Stack
A
F
C A
The Stack and FContents
Memory
address (hex) (hex)
085D DB
Microprocessor
Valid 085C 06
stack data 085B 06
SP 8059
8056
8058
8057 085A 7F
0859 88
A  
7F
32 0858 D5
16
Last data 0857 08
7F
F   A8
F9 item on stack
 

0856 5C
F9
0855 76
B  
16 0854 10
0853 6F
Invalid
C   D5
57 0852 DD
stack data
0851 14
0850 88
6
 The Stack
Stack used to store data requiring access on LIFO
basis

Stack used to store return addresses when branches

to subroutines or interrupt service routines are
made.

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 The 8085 Stack
The 8085 pushes and pops data as 16 bit values
2 consecutive memory accessed on each push or
pop
SP is 16 bits wide and points to the last occupied
memory location on the stack
The stack grows downwards
A push decrements SP by 2
A pop increments SP by 2
Registers that can be pushed to or popped from the
stack are BC, DE, HL and PSW using big endian style.

8
8085 Push and Pop Instructions
PUSH

(SP-2) ← lower register (SP-1) ← higher

register
SP ← SP – 2

POP

lower register ← (SP)

higher register ← (SP+1)
SP ← SP + 2
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8085 Push and Pop Instructions
Assembly instruction Equation
(SP-1) ← H
PUSH HL (SP-2) ← L
SP ← (SP-2)
Flags ← (SP)
POP PSW A ← (SP+1)
SP ← (SP+2)
H ↔ (SP-1)
XTHL
L ↔ (SP-2)

10
Class Exercise
Exercise 9 – question 1

11
Subroutines

12
 Subroutines
A subroutine is a sub-program which can be
branched to from another program.

On its completion, execution branches back to the

calling routine.

Branching to a subroutine is effected by a CALL

instruction in the calling routine.

Branching back to the calling routine is effected by

a RETURN at the end of the subroutine.

Subroutines can be nested – can be called from

within other subroutines.
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Address Instruction Address Instruction Address Instruction

0850
0851
…
…
Subroutines
0860
0861
JP 0900
…
0870
0871
…
…
0852 … 0862 … 0872 …
0863 … 0873 ….
0853 CALL 0861
0864 … 0874 …
0854 …
0865 RET 0875 RET
0855 …
0866 … 0876 …
0856 …
0867 … 0877 CALL 1588
0857 …
0868 …. 0878 …
0858 CALL 0866
0869 … 0879 RET
0859 …
086A … 087A …
085A …
086B CALL 0870 087B …
085B CALL 087A
086C … 087C …
085C …
086D … 087D …
085D …
085E Nested
086E RET 087E …
subroutine
085F …
086F …. 087F RET
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 Subroutines
Address Instruction
0850 …
0851 …
0852 …
0853 CALL 0861
0854 …
0855 …
0856 …
0857 …
All routines are in 0858 CALL 0866
same memory – 0859 …
but placed at 085A …
different 085B CALL 087A
addresses 085C …
085D …
085E
085F …
0860 JP 0900
0861 …
0862 …
0863 … 15
8085 Call and Return Instructions
CALL INSTRUCTION

(SP-2) ← PC low byte

(SP-1) ← PC high byte
SP ← SP – 2
PC ← call address
RETURN INSTRUCTION

PC low byte ← (SP)

PC high byte ← (SP+1)
SP ← SP + 2

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8085 Sample Call Instructions
Assembly instruction Equation
(SP-1) ← PCh
(SP-2) ← PCl
CALL 0800h SP ← (SP-2)
PC ← 0800h
If Cy=1: (SP-1) ← PCh
(SP-2) ← PCl
CC0A09h SP ← (SP-2)
PC ← 0800h
If Z=0: (SP-1) ← PCh
(SP-2) ← PCl
CNZ 0C80h SP ← (SP-2)
PC ← 0800h
If P=1: (SP-1) ← PCh
(SP-2) ← PCl
CPO 0D05h SP ← (SP-2)
PC ← 0800h 17
8085 Sample Return Instructions
Assembly instruction Equation
PCl ← (SP)
RET PCh ← (SP+1)
SP ← (SP+2)
If Cy=0: PCl ← (SP)
RNC PCh ← (SP+1)
SP ← (SP+2)
If Z=1: PCl ← (SP)
RZ PCh ← (SP+1)
SP ← (SP+2)
If S=1: PCl ← (SP)
RM PCh ← (SP+1)
SP ← (SP+2)
If P=0: PCl ← (SP)
RPE PCh ← (SP+1)
SP ← (SP+2) 18
 Class Design Exercise
Programming Exercise Questions

1. Programming Exercise 1b – question 1

2. Programming Exercise 1a – question 4
3. Programming Exercise 1b – question 3
4. Programming Exercise 1a – question 5
5. Assignment – Programming Exercise 1a – question 5
second part
 Class Exercise
Programming Exercise 1b – Question 1

Develop a program to pack two right-justified BCD

codes into a single byte and write it as a subroutine.
The bytes to be packed are contained in the registers
D and E where E contains the lower BCD code and D
contains the higher BCD code. The results are to be
stored in register B.

20
Lecture 12(b)

Subroutines
21
 Class Exercise
Programming Exercise 1a – Question 4 as
subroutines

1. Develop a program to provide a programmed

delay of 1 second and write it as a subroutine.

2. Develop a program to provide a programmed

delay of 10 seconds and write it as a subroutine.

22
 Class Exercise
Programming Exercise 1b – Question 3

Suppose there is developed subroutine which when

executed offers a delay of 1 second. The subroutine is
located at memory address 9101H. You are required to
develop a program that continuously flashes three
lamps (one red, one blue and one white) at intervals
of 1s from red to blue, 3s from blue to white and 4s
from white to red. Make use of the subroutine.

23
 Class Exercise
Programming Exercise 1b – Question 5
A microprocessor based system is required to control traffic lights at an
intersection. The operation is as follows:
The green lights are of equal durations for both streams, the period being 20
seconds.
The red lights are of equal durations for both streams, the period being 20 seconds.
The amber lights are of equal durations for both streams, the period being 5
seconds.
The traffic lights for stream A are connected to pins 0, 1 and 2 of port 06h
and the traffic lights on stream B are connected to pins 4, 5 and 6 of port
06h.

Based on the delay routines designed earlier, develop a program that will
generate the traffic light sequence at the intersection.

Repeat as assignment if traffic on one stream

gets twice the time as the other. 24