Scribd
Upload
59 views18 pages

NXN Crossbar Design For Barrel Shifter: X-Input Y-Output

Uploaded by

hamza abbas

The document describes the design of an NxN crossbar barrel shifter. It has the following key points: 1. The design uses an NxN crossbar layout with the input on one side and output on the other. 2. A tri-state buffer is used to select the shift amount by selecting the appropriate row. 3. The number of gates is O(N^2) and the delay is O(1), providing an efficient shifter design.

Copyright:

© All Rights Reserved
Download as PPT, PDF, TXT or read online from Scribd
Download as ppt, pdf, or txt

NXN Crossbar Design For Barrel Shifter: X-Input Y-Output

Uploaded by

hamza abbas
59 views18 pages
The document describes the design of an NxN crossbar barrel shifter. It has the following key points: 1. The design uses an NxN crossbar layout with the input on one side and output on the other. 2. A tri-state buffer is used to select the shift amount by selecting the appropriate row. 3. The number of gates is O(N^2) and the delay is O(1), providing an efficient shifter design.

Original Title

Lecture36

Copyright

© © All Rights Reserved

Available Formats

PPT, PDF, TXT or read online from Scribd

Did you find this document useful?

Is this content inappropriate?

The document describes the design of an NxN crossbar barrel shifter. It has the following key points: 1. The design uses an NxN crossbar layout with the input on one side and output on the other. 2. A tri-state buffer is used to select the shift amount by selecting the appropriate row. 3. The number of gates is O(N^2) and the delay is O(1), providing an efficient shifter design.

Copyright:

© All Rights Reserved
Download as PPT, PDF, TXT or read online from Scribd
Download as ppt, pdf, or txt
59 views18 pages

NXN Crossbar Design For Barrel Shifter: X-Input Y-Output

Uploaded by

hamza abbas
The document describes the design of an NxN crossbar barrel shifter. It has the following key points: 1. The design uses an NxN crossbar layout with the input on one side and output on the other. 2. A tri-state buffer is used to select the shift amount by selecting the appropriate row. 3. The number of gates is O(N^2) and the delay is O(1), providing an efficient shifter design.

Copyright:

© All Rights Reserved
Download as PPT, PDF, TXT or read online from Scribd
Download as ppt, pdf, or txt
You are on page 1/ 18

NxN Crossbar design for Barrel Shifter

Tri-
y0 y1 state y2
buffer

x0
Decoder

Shift
count
x1

…
x2

Decoder
X-input selects
Y-output the shift
amount …
Number of gates: O(N2)
Delay: O(1) 1
Shift and Rotate Hardware

2
Review

3
CS501
Advanced Computer
Architecture

Lecture 36

Dr.Noor Muhammad Sheikh


4
Input
Word
Bypass/Shift 1 bit right

Bypass/Shift 2 bit right

Bypass/Shift 4 bit right


Shift Count

Bypass/Shift 8 bit right

Bypass/Shift 16 bit right


cell
A shift/bypass

Delay: O(logN)
Word
Output
Logarithmic Barrel Shifter

5
Number of gates: O(NlogN)
x

OPCODE
n
n
Shift count

Arithmetic Logic Shifter

CONTROL
MUX MUX
n

Condition
Block diagram of an ALU

codes
6
Z
Floating-point representation

Floating-point numbers have two parts


• The Significand
• The Exponent

e.g. consider the number


-5.7x10-3 The
Sign is
negative Exponent

The
Base is 10; fixed for a
Significand or
given representation
Mantissa
7
Floating-Point Representation
A common layout for floating-point number is

sign exponent fraction

s e f

1
me mf

M bits
The Bias or
excess •s=1floating point numbers negative
representation •s=0floating point number is positive
•me = number of bits in exponent field
•mf = number of bits in fraction field
• Value(s,e,f) = (-1)s x f x 2e
8
Continued

• Floating point numbers are generally


represented by sign and magnitude form.
• Exponent could be represented in the form
of 2’s complement, but it gives some
complications, e.g. complications in case
of sorting algorithms.
• The solution to the complications is biased
representation.
9
Floating-point representation

Bias representation
• In bias, or excess representation, a number is
added to the exponent so that the result is
always positive
• Biased representation is useful for normalized
numbers
• Instead of bias, two’s complement form can also
be used to represent the exponent

10
IEEE 32 bit single precision format

sign exponent fraction

s e^ f1f2…f23

0 1 8 9 31

Fraction bits of
Positive values
significand including
between 0 to 255
the hidden bit
with bias=127

The IEEE standard floating point numbers can be either


nomalized or denormalized. The denormalized number
11
does not have a hidden bit
Types and values represented by
IEEE Single-precision format

E^ e VALUE TYPE
255 none none NaN
254 127 (-1)sx(1.f1.f2…)x2127 Normalized
… … …
2 -125 (-1)sx(1.f1.f2…)x2-125 Normalized
1 -126 (-1)sx(1.f1.f2…)x2-126 Normalized
0 -127 (-1)sx(1.f1.f2…)x2-126 Denormalized
12
Range of possible numbers

• Positive underflow
0 to (0.5 x 10-128)
• Negative underflow
(-0.5 x 10-128 ) to 0

13
Floating point Addition and Subtraction

The steps taken in floating point


addition or subtraction are
1. Unpacking of sign, exponent and fraction
fields
2. Alignment of significant
3. Addition or subtraction operation
4. Adjusting for carry
5. Rounding off the result
6. Overflow checking and packing
14
Floating Point Addition
0.510 , -0.437510
Binary :
0.510 = 1/210= 0.12= 1.000 x 2-1
-0.437510= -7/1610 = -7/24= -0.01112 = - 1.110 x 2-2

Align: -1.110 x 2-2 → -0.111 x 2-1

Addition: 1.000 x 2-1 + (-0.111 x 2-1) = 0.001 x 2-1

Normalization of Sum:
0.001 2 X 2-1 = 0.0102 x 2-2
= 1.000 2 x 2-4 15
Floating point Add/Sub Hardware
e1 e2 f1 f2
For alignment
Exponent And
Subtractor Swap normalization

Alignment
Shifter

s1 Sign
s2 computation Significand
FA/FS Adder/sub
e1 e2

select Lead zero


counter
Subtract and Normalize
bias and round

16
sr er fr
Floating Point
Multiplication and Division
The floating point multiply procedure is as follows

Unpack sign, exponent Apply xor operation to


Normalize, round
and significands signs, add exponents,
And shift
Multiply significands

Pack the result Adjust for


and report exceptions overflow

17
Floating Point
Multiplication and Division
The floating point divide procedure is as follows
Apply xor operation to
Unpack sign, exponent signs, subtract Normalize, round
and significands exponents, And shift
divide significands

Pack the result Adjust for


and report exceptions overflow

18

You might also like