Chapter 2: The Microprocessor and its Architecture

Introduction
• This section presents the microprocessor as a
programmable device by first looking at its internal
programming model and then how its memory space
is addressed.
• The architecture of Intel microprocessors is presented,
as are the ways that the family members address the
memory system.
• Addressing modes for this powerful family of
microprocessors are described only one of the three
modes: real, protected, and flat modes of operation.
 Lecture Objectives
Upon completion of this class, you will be able to:

• Describe function and purpose of each program-

visible register in the 8086 microprocessor.
• Detail the flag register and the purpose of each
flag bit.
• Describe how memory is accessed using real mode
memory-addressing techniques.
 2–1  INTERNAL MICROPROCESSOR
ARCHITECTURE

• Before a program is written or instruction

investigated, internal configuration of the
microprocessor must be known.
• -Which is shown in the last class
 The Programming Model
• 8086 through Core2 considered program visible.
– registers are used during programming and are
specified by the instructions
• Other registers considered to be program
invisible.
– not addressable directly during applications
programming
• 80286 and above contain program-invisible
registers to control and operate protected
memory.
– and other features of the microprocessor
• 80386 through Core2 microprocessors contain full
32-bit internal architectures.
• 8086 through the 80286 are fully upward-
compatible to the 80386 through Core2.
• Figure 2–1 illustrates the programming model
8086 through Core2 microprocessor.
– including the 64-bit extensions
Figure 2–1  The programming model of the 8086 through the Core2
microprocessor including the 64-bit extensions.
 Multipurpose Registers
• RAX - a 64-bit register (RAX), a 32-bit register
(accumulator) (EAX), a 16-bit register (AX), or as
either of two 8-bit registers (AH and AL).

• The accumulator is used for instructions such as

multiplication, division, and some of the
adjustment instructions.
• RBX, addressable as RBX, EBX, BX, BH, BL.
– BX register (base index) sometimes holds offset
address of a location in the memory system in all
versions of the microprocessor
• RCX, as RCX, ECX, CX, CH, or CL.
– a (count) general-purpose register that also holds the
count for various instructions
• RDX, as RDX, EDX, DX, DH, or DL.
– a (data) general-purpose register
– holds a part of the result from a multiplication
or part of dividend before a division
• RBP, as RBP, EBP, or BP.
– points to a memory (base pointer) location
for memory data transfers
• RDI addressable as RDI, EDI, or DI.
– often addresses (destination index) string destination
data for the string instructions
• RSI used as RSI, ESI, or SI.
– the (source index) register addresses source string
data for the string instructions
– like RDI, RSI also functions as a general-
purpose register
• R8 - R15 found in the Pentium 4 and Core2 if 64-
bit extensions are enabled.
– data are addressed as 64-, 32-, 16-, or 8-bit
sizes and are of general purpose
• Most applications will not use these registers until
64-bit processors are common.
– the 8-bit portion is the rightmost 8-bit only
– bits 8 to 15 are not directly addressable as
a byte
 Special-Purpose Registers
• Include RIP, RSP, and RFLAGS
– segment registers include CS, DS, ES, SS, FS, and GS
• RIP addresses the next instruction in a section of
memory.
– defined as (instruction pointer) a code segment
• RSP addresses an area of memory called
the stack.
– the (stack pointer) stores data through this pointer
• RFLAGS indicate the condition of the
microprocessor and control its operation.
• Figure 2–2 shows the flag registers of all versions
of the microprocessor.
• Flags are upward-compatible from the 8086/8088
through Core2 .
• The rightmost five and the overflow flag are
changed by most arithmetic and logic operations.
– although data transfers do not affect them
 Figure 2–2  The EFLAG and FLAG register counts for the entire 8086 and Pentium
microprocessor family.

• Flags never change for any data transfer or

program control operation.
• Some of the flags are also used to control
features found in the microprocessor.
 List of Each Flag bit, with a brief description of
function.

• C (carry) holds the carry after addition or borrow

after subtraction.
– also indicates error conditions
• P (parity) is the count of ones in a number
expressed as even or odd. Logic 0 for odd parity;
logic 1 for even parity.
– if a number contains three binary one bits, it has odd
parity; If a number contains no one bits, it
has even parity
• A (auxiliary carry) holds the carry (half-carry)
after addition or the borrow after subtraction
between bit positions 3 and 4 of the result.
• Z (zero) shows that the result of an arithmetic or
logic operation is zero.
• S (sign) flag holds the arithmetic sign of the result
after an arithmetic or logic instruction executes.
• T (trap) The trap flag enables trapping through an
on-chip debugging feature.
• I (interrupt) controls operation of the INTR
(interrupt request) input pin.
• D (direction) selects increment or decrement
mode for the DI and/or SI registers.
• O (overflow) occurs when signed numbers are
added or subtracted.
– an overflow indicates the result has exceeded
the capacity of the machine
 Segment Registers
• Generate memory addresses when combined with
other registers in the microprocessor.
• Four or six segment registers in various versions of
the microprocessor.
• A segment register functions differently in real
mode than in protected mode.
• Following is a list of each segment register, along
with its function in the system.
• CS (code) segment holds code (programs and
procedures) used by the microprocessor.
• DS (data) contains most data used by a program.
– Data are accessed by an offset address or contents of
other registers that hold the offset address
• ES (extra) an additional data segment used by
some instructions to hold destination data.
• SS (stack) defines the area of memory used for
the stack.
– stack entry point is determined by the stack segment
and stack pointer registers
– the BP register also addresses data within
the stack segment
• FS and GS segments are supplemental segment
registers available in 80386–Core2
microprocessors.
– allow two additional memory segments for
access by programs
• Windows uses these segments for internal
operations, but no definition of their usage
is available.
2–2  REAL MODE MEMORY ADDRESSING

• 80286 and above operate in either the real or

protected mode.
• Real mode operation allows addressing of only the
first 1M byte of memory space—even in Pentium 4
or Core2 microprocessor.
– the first 1M byte of memory is called the real memory,
conventional memory, or DOS memory system
 Segments and Offsets
• All real mode memory addresses must consist of a
segment address plus an offset address.
– segment address defines the beginning address of any
64K-byte memory segment
– offset address selects any location within the
64K byte memory segment
• Figure 2–3 shows how the segment plus offset
addressing scheme selects a memory location.
Figure 2–3  The real mode memory-addressing scheme, using a
segment address plus an offset.
– this shows a memory
segment beginning at
10000H, ending at
location IFFFFH
• 64K bytes in length

– also shows how an offset

address, called a
displacement, of F000H
selects location
1F000H in the memory
• Once the beginning address is known, the ending
address is found by adding FFFFH.
– because a real mode segment of memory is64K in
length
• The offset address is always added to the segment
starting address to locate the data.
• Segment and offset address is sometimes written
as 1000:2000.
– a segment address of 1000H; an offset of 2000H
 Default Segment and Offset Registers

• The microprocessor has rules that apply to

segments whenever memory is addressed.
– these define the segment and offset register
combination
• The code segment register defines the start of the
code segment.
• The instruction pointer locates the next
instruction within the code segment.
• Another of the default combinations is the stack.
– stack data are referenced through the stack segment
at the memory location addressed by either the stack
pointer (SP/ESP) or the pointer (BP/EBP)
• Figure 2–4 shows a system that contains four
memory segments.
– a memory segment can touch or overlap if 64K bytes
of memory are not required for a segment
Figure 2–4  A memory system showing the placement of four memory
segments.
– think of segments as
Windows that can be
moved over any area
of memory to access data
or code
– a program can have more
than four or six segments,
• but only access four or six segments
at a time
Chapter 3: Addressing Modes
 Introduction
• Efficient software development for the
microprocessor requires a complete familiarity
with the addressing modes employed by each
instruction.
• This chapter/section explains the operation of the
stack memory so that the PUSH and POP
instructions and other stack operations will
be understood.
 Lecture Objectives
Upon completion of this lecturer, you will be able to:

• Explain the operation of each data-addressing

mode.
• Use the data-addressing modes to form assembly
language statements.
• Explain the operation of each program memory-
addressing mode.
• Use the program memory-addressing modes to
form assembly and machine language statements.
 Lecture Objectives (cont.)
Upon completion of this lecture, you will be able to:

• Select the appropriate addressing mode to

accomplish a given task.
• Describe sequence of events that place data onto
the stack or remove data from the stack.
• Explain how a data structure is placed in memory
and used with software.
• Each statement in an assembly language program
consists of four parts or fields.
• The leftmost field is called the label.
– used to store a symbolic name for the memory
location it represents
• All labels must begin with a letter or one of the
following special characters: @, $, -, or ?.
– a label may any length from 1 to 35 characters
• The label appears in a program to identify the
name of a memory location for storing data and
for other purposes.
• The next field to the right is the opcode field.
– designed to hold the instruction, or opcode
– the MOV part of the move data instruction is an
example of an opcode
• Right of the opcode field is the operand field.
– contains information used by the opcode
– the MOV AL,BL instruction has the opcode MOV and
operands AL and BL
• The comment field, the final field, contains a
comment about the instruction(s).
– comments always begin with a semicolon (;)
 Direct Data Addressing
• Applied to many instructions in a typical program.
• Two basic forms of direct data addressing:
– direct addressing, which applies to a MOV between a
memory location and AL, AX, or EAX
– displacement addressing, which applies to almost any
instruction in the instruction set
• Address is formed by adding the displacement to
the default data segment address or an alternate
segment address.
 3–1  DATA ADDRESSING MODES
• MOV instruction is a common and flexible instruction.
– provides a basis for explanation of data-addressing modes
• Figure 3–1 illustrates the MOV instruction and defines
the direction of data flow.
• Source is to the right and destination the left, next to
the opcode MOV.
– an opcode, or operation code, tells the microprocessor
which operation to perform
Figure 3–1  The MOV instruction showing the source, destination,
and direction of data flow.
• Figure 3–2 shows all possible variations of the
data-addressing modes using MOV.
• These data-addressing modes are found with all
versions of the Intel microprocessor.
– except for the scaled-index-addressing mode, found
only in 80386 through Core2
Figure 3–2  8086–Core2 data-addressing modes.
 Register Addressing
• The most common form of data addressing.
– once register names learned, easiest to apply.
• The microprocessor contains these 8-bit register
names used with register addressing: AH, AL, BH,
BL, CH, CL, DH, and DL.
• 16-bit register names: AX, BX, CX, DX, SP, BP, SI,
and DI.
Figure 3–3  The effect of executing the MOV BX, CX instruction at the point just before the
BX register changes. Note that only the rightmost 16 bits of register EBX change.
• Figure 3–3 shows the operation of the MOV BX,
CX instruction.
• The source register’s contents do not change.
– the destination register’s contents do change
• The contents of the destination register or
destination memory location change for all
instructions except the CMP and TEST
instructions.
• The MOV BX, CX instruction does not affect the
leftmost 16 bits of register EBX.
 Immediate Addressing
• Term immediate implies that data immediately
follow the hexadecimal opcode in the memory.
– immediate data are constant data
– data transferred from a register or memory location
are variable data
• Immediate addressing operates upon a byte or
word of data.
• Figure 3–4 shows the operation of a MOV
EAX,13456H instruction.
 Figure 3–4  The operation of the MOV EAX,3456H instruction. This
instruction copies the immediate data (13456H) into EAX.

• As with the MOV instruction illustrated in Figure

3–3, the source data overwrites the destination
data.
• The symbolic assembler portrays immediate data
in many ways.
• The letter H appends hexadecimal data.
• If hexadecimal data begin with a letter, the
assembler requires the data start with a 0.
– to represent a hexadecimal F2, 0F2H is used
in assembly language
• Decimal data are represented as is and require no
special codes or adjustments.
– an example is the 100 decimal in the
MOV AL,100 instruction
• An ASCII-coded character or characters may be
depicted in the immediate form if the ASCII data
are enclosed in apostrophes.
– be careful to use the apostrophe (‘) for ASCII
data and not the single quotation mark (‘)
• Binary data are represented if the binary number
is followed by the letter B.
– in some assemblers, the letter Y
 Direct Addressing
• Direct addressing with a MOV instruction transfers
data between a memory location, located within
the data segment, and the AL (8-bit), AX (16-bit),
or EAX (32-bit) register.
– usually a 3-byte long instruction
• MOV AL,DATA loads AL from the data segment
memory location DATA (1234H).
– DATA is a symbolic memory location, while
1234H is the actual hexadecimal location
 Figure 3–5  The operation of the MOV AL,[1234H] instruction when DS=1000H .

• This instruction transfers a copy contents of

memory location 11234H into AL.
– the effective address is formed by adding
1234H (the offset address) and 10000H
(the data segment address of 1000H times
10H) in a system operating in the real mode
 Register Indirect Addressing
• Allows data to be addressed at any memory
location through an offset address held in any of
the following registers: BP, BX, DI, and SI.
Figure 3–6  The operation of the MOV AX, [BX] instruction when BX = 1000H and DS = 0100H.
Note that this instruction is shown after the contents of memory are transferred to AX.
• The data segment is used by default with register
indirect addressing or any other mode that uses
BX, DI, or SI to address memory.
• If the BP register addresses memory, the stack
segment is used by default.
– these settings are considered the default for
these four index and base registers
• For the 80386 and above, EBP addresses memory
in the stack segment by default.
• EAX, EBX, ECX, EDX, EDI, and ESI address memory
in the data segment by default.
• In some cases, indirect addressing requires
specifying the size of the data by the special
assembler directive BYTE PTR, WORD PTR,
DWORD PTR, or QWORD PTR.
– these directives indicate the size of the memory data
addressed by the memory pointer (PTR)
• The directives are with instructions that address a
memory location through a
pointer or index register with immediate data.
• With SIMD instructions, the octal OWORD PTR,
represents a 128-bit-wide number.
Base-Plus-Index ( 索引、註標 ) Addressing
• Similar to indirect addressing because it indirectly
addresses memory data.
• The base register often holds the beginning
location of a memory array.
– the index register holds the relative position
of an element in the array
– whenever BP addresses memory data, both the stack
segment register and BP generate the effective address
Locating Data with Base-Plus-Index Addressing

• Figure 3–8 shows how data are addressed by the

MOV DX, [BX + DI] instruction when the
microprocessor operates in the real mode.
• The Intel assembler requires this addressing mode
appear as [BX][DI] instead of [BX + DI].
• The MOV DX, [BX + DI] instruction is MOV DX,[BX]
[DI] for a program written for the Intel ASM
assembler.
Figure 3–8  An example showing how the base-plus-index addressing mode functions for the
MOV DX, [BX + DI] instruction. Notice that memory address 02010H is accessed because
DS=0100H, BX=100H and DI=0010H.
 Locating Array Data Using Base-Plus-Index
Addressing

• A major use is to address elements in a memory

array.
• To accomplish this, load the BX register (base) with
the beginning address of the array and the DI
register (index) with the element number to be
accessed.
• Figure 3–9 shows the use of BX and DI to access an
element in an array of data.
Figure 3–9  An example of the base-plus-index addressing mode. Here an element (DI) of an
ARRAY (BX) is addressed.
 Register Relative Addressing
• Similar to base-plus-index addressing and
displacement addressing.
– data in a segment of memory are addressed by adding
the displacement to the contents of a base or an index
register (BP, BX, DI, or SI)
• Figure 3–10 shows the operation of the MOV AX,
[BX+1000H] instruction.
• A real mode segment is 64K bytes long.
Figure 3–10  The operation of the MOV AX, [BX+1000H] instruction,
when BX=1000H and DS=0200H .
Addressing Array Data with Register Relative

• It is possible to address array data with register

relative addressing.
– such as with base-plus-index addressing
• In Figure 3–11, register relative addressing is
illustrated with the same example as for base-plus-
index addressing.
– this shows how the displacement ARRAY adds
to index register DI to generate a reference to
an array element
Figure 3–11  Register relative addressing used to address an element of ARRAY.
The displacement addresses the start of ARRAY, and DI accesses an element.
 Base Relative-Plus-Index Addressing

• Similar to base-plus-index addressing.

– adds a displacement
– uses a base register and an index register to
form the memory address
• This type of addressing mode often addresses a
two-dimensional array of memory data.
Addressing Data with Base Relative-Plus-Index

• Least-used addressing mode.

• Figure 3–12 shows how data are referenced if the
instruction executed by the microprocessor is
MOV AX, [BX + SI + 100H].
– displacement of 100H adds to BX and SI to form the
offset address within the data segment
• This addressing mode is too complex for frequent
use in programming.
Figure 3–12  An example of base relative-plus-index addressing using a MOV AX,
[BX+SI=1000H] instruction. Note: DS=1000H
Addressing Arrays with Base Relative-Plus-Index

• Suppose a file of many records exists in memory,

each record with many elements.
– displacement addresses the file, base register
addresses a record, the index register addresses an
element of a record
• Figure 3–13 illustrates this very complex form of
addressing.
Figure 3–13  Base relative-plus-index addressing used to access a FILE
that contains multiple records (REC).
 Scaled-Index Addressing
• Unique to 80386 - Core2 microprocessors.
– uses two 32-bit registers (a base register and
an index register) to access the memory
• The second register (index) is multiplied by a
scaling factor.
– the scaling factor can be 1x, 2x, 4x, 8x
• Assembly language instruction: MOV AL, [EBX
+2xECX].
Exercise:
 3–3  STACK MEMORY-ADDRESSING MODES

• The stack plays an important role in all

microprocessors.
– holds data temporarily and stores return addresses
used by procedures
• Stack memory is LIFO (last-in, first-out) memory
– describes the way data are stored and removed from
the stack
• Data are placed on the stack with a PUSH
instruction; removed with a POP instruction.
• Stack memory is maintained by two registers:
– the stack pointer (SP or ESP)
– the stack segment register (SS)
• Whenever a word of data is pushed onto the stack,
the high-order 8 bits are placed in the location
addressed by SP – 1.
– low-order 8 bits are placed in the location addressed by
SP – 2
• The SP is decremented by 2 so the next word is
stored in the next available stack location.
– the SP/ESP register always points to an area of memory
located within the stack segment.

• When data are popped from the stack,

 the low-order 8 bits are removed from the location
addressed by SP.
 The higher order 8 bits are removed from location
addressed by SP+1
 Finally, the SP register is incremented by 2
Figure 3–17  The PUSH and POP instructions: (a) PUSH BX places the contents of BX onto the
stack; (b) POP CX removes data from the stack and places them into CX. Both instructions are
shown after execution.
• Note that PUSH and POP store or retrieve words
of data—never bytes—in 8086 - 80286.
• 80386 and above allow words or doublewords to
be transferred to and from the stack.
• Data may be pushed onto the stack from any 16-
bit register or segment register.
– in 80386 and above, from any 32-bit extended register
• Data may be popped off the stack into any register
or any segment register except CS.
• PUSHA and POPA instructions push or pop all
except segment registers, on the stack.
• Not available on early 8086/8088 processors.
• 80386 and above allow extended registers to be
pushed or popped.
– 64-bit mode for Pentium and Core2 does not contain a
PUSHA or POPA instruction
 4–2  PUSH/POP
• Important instructions that store and retrieve data
from the LIFO (last-in, first-out) stack memory.
• Six forms of the PUSH and POP instructions:
– register, memory, immediate
– segment register, flags, all registers
• The PUSH and POP immediate & PUSHA and POPA
(all registers) available 80286 - Core2.
PUSH and POP instructions
• Register addressing allows contents of any 16-bit
register to transfer to & from the stack.
• Memory-addressing PUSH and POP instructions
store contents of a 16- or 32 bit memory location
on the stack or stack data into a memory location.
• Immediate addressing allows immediate data to
be pushed onto the stack, but not popped off the
stack.
• Segment register addressing allows contents of
any segment register to be pushed onto the stack
or removed from the stack.
– ES may be pushed, but data from the stack may never
be popped into ES
• The flags may be pushed or popped from
that stack.
– contents of all registers may be pushed or
popped
 PUSH
• Always transfers 2 bytes of data to the stack;
– 80386 and above transfer 2 or 4 bytes
• PUSHA instruction copies contents of the internal
register set, except the segment registers, to the
stack.
• PUSHA (push all) instruction copies the registers
to the stack in the following order: AX, CX, DX, BX,
SP, BP, SI, and DI.
• PUSHF (push flags) instruction copies the
contents of the flag register to the stack.
• PUSHAD and POPAD instructions push and pop
the contents of the 32-bit register set in 80386 -
Pentium 4.
– PUSHA and POPA instructions do not function in the
64-bit mode of operation for the Pentium 4
 Figure 4–13  The effect of the PUSH AX instruction on ESP and stack memory
locations 37FFH and 37FEH. This instruction is shown at the point after execution.
• PUSHA instruction pushes all the internal 16-bit
registers onto the stack, illustrated in 4–14.
– requires 16 bytes of stack memory space to
store all eight 16-bit registers
• After all registers are pushed, the contents of the
SP register are decremented by 16.
• PUSHA is very useful when the entire register set
of 80286 and above must be saved.
• PUSHAD instruction places 32-bit register set on
the stack in 80386 - Core2.
– PUSHAD requires 32 bytes of stack storage
Figure 4–14  The operation of the PUSHA instruction, showing the
location and order of stack data.
 POP
• Performs the inverse operation of PUSH.
• POP removes data from the stack and places it in a
target 16-bit register, segment register, or a 16-bit
memory location.
– not available as an immediate POP
• POPF (pop flags) removes a 16-bit number from
the stack and places it in the flag register;
– POPFD removes a 32-bit number from the stack and
places it into the extended flag register
• POPA (pop all) removes 16 bytes of data from the
stack and places them into the following registers,
in the order shown: DI, SI, BP, SP, BX, DX, CX, and
AX.
– reverse order from placement on the stack by PUSHA
instruction, causing the same data to return to the
same registers
• Figure 4–15 shows how the POP BX instruction
removes data from the stack and places them into
register BX.
Figure 4–15  The POP BX instruction, showing how data are removed
from the stack. This instruction is shown after execution.
 Initializing the Stack
• When the stack area is initialized, load both the
stack segment (SS) register and the stack pointer
(SP) register.
• Figure 4–16 shows how this value causes data to
be pushed onto the top of the stack segment with
a PUSH CX instruction.
• All segments are cyclic in nature
– the top location of a segment is contiguous
with the bottom location of the segment
 Figure 4–16  The PUSH CX instruction, showing the cyclical nature of the stack segment. This
instruction is shown just before execution, to illustrate that the stack bottom is contiguous to the
top.
 SUMMARY
• The MOV instruction copies the contents of the
source operand into the destination operand.
• The source never changes for any instruction.
• Register addressing specifies any 8-bit register
(AH, AL, BH, BL, CH, CL, DH, or DL) or any 16-bit
register (AX, BX, CX, DX, SP, BP, SI, or DI).
 SUMMARY (cont.)
• The segment registers (CS, DS, ES, or SS) are
also addressable for moving data between a
segment register and a 16-bit register/memory
location or for PUSH and POP.
• In the 80386 through the Core2
microprocessors, the extended registers also
are used for register addressing; they consist of
EAX, EBX, ECX, EDX, ESP, EBP, EDI, and ESI.
 SUMMARY (cont.)
• In the 64-bit mode, the registers are RAX, RBX,
RCX, RDX, RSP, RBP, RDI, RSI, and R8 through
R15.
• The MOV immediate instruction transfers the
byte or word that immediately follows the
opcode into a register or a memory location.
• Immediate addressing manipulates constant
data in a program.
 SUMMARY (cont.)
• In the 80386 and above, doubleword
immediate data may also be loaded into
a 32-bit register or memory location.
• The .MODEL statement is used with assembly
language to identify the start of a file and the
type of memory model used with the file.
• If the size is TINY, the program exists in
the code segment, and assembled as a
command (.COM) program.
 SUMMARY (cont.)
• If the SMALL model is used, the program uses a
code and data segment and assembles as an
execute (.EXE) program.
• Direct addressing occurs in two forms in the
microprocessor: direct addressing and
displacement addressing.
 SUMMARY (cont.)
• Both forms of addressing are identical except
that direct addressing is used to transfer data
between EAX, AX, or AL and memory;
displacement addressing is used with any
register-memory transfer.
• Direct addressing requires 3 bytes of memory,
whereas displacement addressing requires 4
bytes.
 SUMMARY (cont.)
• Register indirect addressing allows data to be
addressed at the memory location pointed to
by either a base (BP and BX) or index register
(DI and SI).
• In the 80386 and above, extended registers
EAX, EBX, ECX, EDX, EBP, EDI, and ESI are used
to address memory data.
 SUMMARY (cont.)
• Base-plus-index addressing often addresses
data in an array.
• The memory address for this mode is formed by
adding a base register, index register, and the
contents of a segment register times 10H.
• In the 80386 and above, the base and index
registers may be any 32-bit register except EIP
and ESP.
 SUMMARY (cont.)
• Register relative addressing uses a base or
index register, plus a displacement to access
memory data.
• Base relative-plus-index addressing is useful for
addressing a two-dimensional memory array.
• The address is formed by adding a base register,
an index register, displacement, and the
contents of a segment register times 10H.
 SUMMARY (cont.)
• Scaled-index addressing is unique to the 80386
through the Core2.
• The second of two registers (index) is scaled by
a factor of to access words, doublewords, or
quadwords in memory arrays.
• The MOV AX, [ EBX + 2*ECX] and the MOV [4 *
ECX ], EDX are examples of scaled-index
instructions.
 SUMMARY (cont.)
• The PUSH and POP instructions transfer a word
between the stack and a register or memory
location.
• A PUSH immediate instruction is available to
place immediate data on the stack.
 SUMMARY
• The PUSHA and POPA instructions transfer AX,
CX, DX, BX, BP, SP, SI, and DI between the stack
and these registers.
• In 80386 and above, the extended register and
extended flags can also be transferred between
registers and the stack.
• A PUSHFD stores the EFLAGS, whereas a PUSHF
stores the FLAGS. POPA and PUSHA are not
available in 64-bit mode.