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Chameleon Chip: By: B.Manaswitha Reddy (07261A0467)

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Sri Krishna Priya Kuppa
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51 views19 pages

Chameleon Chip: By: B.Manaswitha Reddy (07261A0467)

Uploaded by

Sri Krishna Priya Kuppa
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Chameleon Chip

By:
B.Manaswitha Reddy
(07261A0467)
CONTENTS
1.Introduction
2.Multifunction Implementation
3.Architecture
4.Reconfigurable Processing Fabric
5.Programmable I/O
6.Technologies Used In Chip
7.Design Process
8.Comparison With Other Technologies
9.Advantages
10.Disadvantages
11.Applications
12.Conclusion
1.Introduction
A reconfigurable processor is a microprocessor with
erasable hardware that can rewire itself dynamically.

Contains several parallel processing computational units


known as functional blocks.

that means when a particular software is loaded the


present hardware design is erased and a new
hardware design is generated by making a particular
number of connections active while making others
idle.
This will define the optimum hardware configuration for that
particular software.

It takes just 20 microseconds to reconfigure the entire


processing array.

Reconfigurable processors are currently available from


Chameleon Systems, Billions of Operations (BOPS), and PACT
(Parallel Array Computing Technology).
3.Architecture
Components:

32-bit Risc ARC processor @125MHz


64 bit memory controller
32 bit PCI controller
reconfigurable processing fabric (RPF)
high speed system bus
programmable I/O (160 pins)
DMA Subsystem
Configuration Subsystem
4.Reconfigurable Processing Fabric(RPF)

 Consists of :
 84,32-bit Data path Units
 24, 16×24-bit Multipliers.
Operating at 125Mhz, they provide up to 3,000 16-bit Million
Multiply-Accumulates Per Second and 24,000 16-bit Million
Operations Per Second.

The fabric is divided into Slices, each slice into tiles.


Tiles contain :
 Datapath Units
 Local Store Memories
 16x24 multipliers
 Control Logic Unit
5.Programmable I/O

RCP includes banks of Programmable I/O (PIO) pins which


provide tremendous bandwidth.

Each PIO bank of 40 PIO pins delivers 0.5 GBytes/sec I/O


bandwidth.
6. Technologies used in the chip:

• e- configurable technology: reconfigures fabric in one


clock cycle and increases voice/data/video channels per chip

• C~SIDE Development Tools: provides ability for the


customers to do the programming themselves thus keeping the
secrecy of their algorithms

• eBios: provides an interface between the Embedded


Processor System and the Fabric.
7.Design Process
9.Advantages

can create customized communications signal processors

increased performance and channel count

can more quickly adapt to new requirements and standards

lower development costs and reduce risk.

Reducing power

Reducing manufacturing cost.


10.Disadvantages

Inertia – Engineers slow to change


Inertia is the worst problem facing reconfigurable
computing

 RCP designs requires comprehensive set of tools

'Learning curve' for designers unfamiliar with reconfigurable


logic 
11.Applications

Wireless Base stations 

Wireless Local Loop (WLL)

High-Performance DSL (Digital Subscriber Line Technology)

Software-Defined Radio (SDR) 


12.Conclusion

 These new chips called chameleon chips are able to rewire


themselves on the fly to create the exact hardware needed to run a
piece of software at the outmost speed.

 They are very advantageous and have wide range of


applications.

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