Design of A Simple CPU (MIPS)
MIPS Instruction Formats
uction1 and Data sizes of the MIPS CPU are 32 bits.
Dr. Ibrahim Qamar
Design of A Simple CPU (MIPS)
Some MIPS Instruction
•Immediate Format
(Add rt, rs, Immediate rt ← rs + SignExtend(Immediate)
•Register Addressing
(Add rd, rs, rt rd ← rs + rt)
•Base Addressing
(Ldrt, rs, Address rt ← M[rs(Address)])
(St rt, rs, Address M[rs(Address)] ← rt)
•PC-Relative Addressing
(Beq rs, rt, Address Z:PC ← PC+SignExtend(Address))
•Pseudo-direct Addressing
(Jmp Address PC ← PC(31 : 26) | Address)
Design of A Simple CPU (MIPS)
MIPS Addressing Modes
3 Dr. Ibrahim Qamar
S1
S2
S3
S4
LD
Control Unit R1
(31:26) R2
WR
Z Add
Sub
PC(31:26) Instr(25:0) RD
WD
+
0
MUX4 0 MUX
1 S 3 1S
LD 32*32 Register file
Instruction RDATA RD
Memory RD1 Data Memory
(25:21)
A
RReg1
PC
Address
4 Instruction(31:0) (20:19) RReg2 4 Address DATAO
RD2 R
0 WReg 0
MUX Sub DATAI
MUX
INC 11S B Ad
21S d WD
R1 R2 WR
1 1
Cp (15:11)
(15:0)
SignExtend
Design of A Simple CPU (MIPS)
MIPS Hardware Components
Design of A Simple CPU (MIPS)
Register Transfer of some MIPS Instruction
• Immediate Format
(Q1: Add rt, rs, Immediate rt ← rs + SignExtend(Immediate)
Instruction(31:0) ← InstM[PC], PC(inc) ← 1
RReg1 ← Instruction(25:21), R1 ← 1
WReg ← Instruction(20:16), WR ← 1
ALUA ← RD1, ALUB ← SignExtend(15:0), Add ← 1
RDATA ← ALUR
• Register Addressing
(Q2 : Add rd, rs, rt rd ← rs + rt)
Instruction(31:0) ← InstM[PC], PC(inc) ← 1
RReg1 ← Instruction(25:21), R1 ← 1
RReg2 ← Instruction(20:16), R2 ← 1
WReg ← Instruction(15:11), WR ← 1
ALUA ← RD1, ALUB ← RD2, Add ← 1
RDATA ← ALUR
Design of A Simple CPU (MIPS)
Register Transfer of some MIPS Instruction
• Base Addressing
(Q3:Ld rt, rs, Address rt ← M[rs(Address)])
Instruction(31:0) ← InstM[PC], PC(inc) ← 1
RReg1 ← Instruction(25:21), R1 ← 1
WReg ← Instruction(20:16), WR ← 1
ALUA ← RD1, ALUB ← SignExtend(15:0), Add ← 1
DAddress ← ALUR
RDATA ← DATAO, MR ← 1
(Q4:St rt, rs, Address M[rs(Address)] ← rt)
Instruction(31:0) ← InstM[PC], PC(inc) ← 1
RReg1 ← Instruction(25:21), R1 ← 1
RReg2 ← Instruction(20:16), R2 ← 1
ALUA ← RD1, ALUB ← SignExtend(15:0), Add ← 1
DAddress ← ALUR
DDATA ← RD2, WD ← 1
Design of A Simple CPU (MIPS)
Register Transfer of some MIPS Instruction
• PC-Relative Addressing
(Q5:Beq rs, rt, Address Z : PC ← PC + SignExtend(Address))
Instruction(31:0) ← InstM[PC], PC(inc) ← 1
RReg1 ← Instruction(25:21), R1 ← 1
RReg2 ← Instruction(20:16), R2 ← 1
ALUA ← RD1, ALUB ← RD2, Sub ← 1
Z : PC ← PC + SignExtend(15:0), PC(Ld) ← 1
• Pseudo-direct Addressing
(Q6:Jmp Address PC ← PC(31 : 26) | Address)
Instruction(31:0) ← InstM[PC]
PC ← PC(31:26) | Instruction(25:0)
R
Memory
W
Address Data
Bus Bus
E1 L1 L1
CL
M M A
Control P A D
Unit IR A
C ALU
R R L
E L E L L E L E B
CL SC Internal CPU Bus
Assuming 16 bits registers CPU with the following 4 instructions:
q0 : LD [XYZ] A M[XYZ]
q1 : ST [XYZ] M[XYZ] A
q2 : ADD [XYZ] A A + M[XYZ]
q3 : BRC XXX C : PC XXX
The Instruction Format is as follows:
• 4 instructions need 4 op-codes given in 2 bits
• 16 bits Fixed length Instruction format as shown
Operand
Op-Code
• The instructions is first Fetched from memory to CPU then Executed by the CPU.
• Fetching the instructions is done same way for all instructions, while the execution
changes according to the instruction.
• Fetching the instruction means executing the following register transfer:
IR M[PC]
Instruction Microinstruction
T0 : MAR ← BUS, BUS ← PC
Fetch Cycle T1 : MDR ← M[MAR], R ← 1, PC ← PC + 1
T2 : IR ← BUS, BUS ← MDR
q0.T3 : MAR ← BUS, BUS ← IR
LD [XYZ] q0.T4 : MDR ← M[MAR], R ← 1
q0.T5 : A ← BUS, BUS← MDR, SC ← 0
q1.T3 : MAR ← BUS, BUS ← IR
ST [XYZ] q1.T4 : MDR ← BUS, BUS← A
q1.T5 :M[MAR] ← MDR, W ← 1,SC ← 0
q2.T3 : MAR ← BUS, BUS ← IR
ADD [XYZ] q2.T4 : MDR ← M[MAR], R ← 1
q2.T5 : ALUB← MDR, ADD← 1, A ← ALUR, SC ← 0
q3.T3.CF : PC ← BUS, BUS ← IR
BRC XXX q3.T3 : SC ← 0
Reset PC ← 0, SC ← 0
Grouping the Instructions
-------------------------------------------Register Transfers------------------------------
X0 = T0 : MAR BUS, BUS PC
X1 = T1 + q0.T4 + q2.T4 : MDR M[MAR]
X2 = T2 : IR BUS, BUS MDR
X3 = q0.T3 + q1.T3 + q2.T3 : MAR BUS, BUS IR
X4 = q0.T5 : A BUS, BUS MDR
X5 = q1.T4 : MDR BUS, BUS A
X6= q1.T5 :M[MAR] MDR
X7 = q2.T5 : ALUB MDR, A ALUR
X8 = q3.T3.CF : PC BUS, BUS IR
-------------------------------------------Signals ------------------------------------------
X9 = T1 : PC PC + 1
X1 = T1 + q0.T4 + q2.T4 : R 1
X10 = q0.T5 + q1.T5 + q2.T5 + q3.T3: SC 0
X6 = q1.T5 : W 1
X7 = q2.T5 : ADD 1
Grouping the Instructions
-------------------------------------------Register Transfers------------------------------
L(MAR) = E(PC) = X0 : MAR BUS, BUS PC
L1(MDR) = X1 : MDR M[MAR]
L(IR) = E(MDR) = X2 : IR BUS, BUS MDR
L(MAR) = E(IR) = X3 : MAR BUS, BUS IR
L(A) = E(MDR) = X4 : A BUS, BUS MDR
L(MDR) = E(A) = X5 : MDR BUS, BUS A
E1(MDR) = X6 :M[MAR] MDR
E(MDR) = L1(A) = X7 : ALUB MDR, A ALUR
L(PC) = E(IR) = X8 : PC BUS, BUS IR
-------------------------------------------Signals ------------------------------------------
INC(PC) = X9 : PC PC + 1
R = X1 : R 1
CL(SC) = X10 + Reset : SC 0
W = X6 : W 1
ADD = X7 : ADD 1
CL(PC) = Reset
R Memory
Address Data
W
Bus Bus
E L1 L1
CL
M M A
Control P A D
Unit IR A
C ALU
R R L2
L L L L B
CL SC
0 1 2 3
S1 4:1 Mux
S0
Instruction Microinstruction
T0 : MAR PC
Fetch Cycle T1 : MDR M[MAR], R 1, PC PC + 1
T2 : IR MDR
q0.T3 : MAR IR
LD [XYZ] q0.T4 : MDR M[MAR], R 1
q0.T5 : A MDR, SC 0
q1.T3 : MAR IR
ST [XYZ] q1.T4 : MDR A
q1.T5 :M[MAR] MDR, W 1,SC 0
q2.T3 : MAR IR
ADD [XYZ] q2.T4 : MDR M[MAR], R 1
q2.T5 : ALUB MDR, ADD 1, A ALUR, SC
0
q3.T3.CF : PC IR
BRC XXX q3.T3 : SC 0
Grouping the Instructions
-------------------------------------------Register Transfers---------------S1 S0-------
X0 = T0 : MAR PC 0 1
X1 = T1 + q0.T4 + q2.T4 : MDR M[MAR]
X2 = T2 : IR MDR 1 0
X3 = q0.T3 + q1.T3 + q2.T3 : MAR IR 0 0
X4 = q0.T5 : A MDR 1 0
X5 = q1.T4 : MDR A 1 1
X6= q1.T5 :M[MAR] MDR
X7 = q2.T5 :ALUB MDR, A ALUR 1 0
X8 = q3.T3.CF : PC IR 0 0
-------------------------------------------Signals ------------------------------------------
X9 = T1 : PC PC + 1
X1 = T1 + q0.T4 + q2.T4 : R 1
X10 = q0.T5 + q1.T5 + q2.T5 + q3.T3: SC 0
X6 = q1.T5 : W 1
X7 = q2.T5 : ADD 1
Grouping the Instructions
-------------------------------------------Register Transfers------------------------------
L(MAR) = X0 : MAR PC
L1(MDR) = X1 : MDR M[MAR]
L(IR) = X2 : IR MDR
L(MAR) = X3 : MAR IR
L(A) = X4 : A MDR
L(MDR) = X5 : MDR A
E1(MDR) = X6 :M[MAR] MDR
L1(A) = X7 :ALUB MDR, A ALUR
L(PC) = X8 : PC IR
-------------------------------------------Signals ------------------------------------------
INC(PC) = X9 : PC PC + 1
R = X1 : R 1
CL(SC) = X10 + Reset : SC 0
W = X6 : W 1
ADD = X7 : ADD 1
CL(PC) = Reset S0 = X0 + X5 S1 = X2 + X4 + X5 + X7
ROM Input and Related microinstructions and signals
Reset Q2 Q1 Q0 IR(15) IR(14) C Microinstructions Activated Signals Instruction
PC(CLR)(0) ,
1 X X X X X X PC ¬ 0 (0), SC ¬ 0 (8) SC(CLR)(8) Reset
0 0 0 0 X X X MAR ¬ PC (1) MAR(LD)(1)
MDR(LD)(2), (R)(6), Fetch
0 0 0 1 X X X MDR ¬ M[MAR] (2) , R ¬ 1 (6) , PC ¬ PC + 1 (3) PC(INC)(3)
0 0 1 0 X X X IR ¬ MDR (4) IR(LD)(4)
0 0 1 1 0 0 X MAR ¬ IR (5) MAR(LD)(5)
0 1 0 0 0 0 X MDR ¬ M[MAR] (2) , R ¬ 1 (6) MDR(LD)(2), (R)(6) A ¬ M[XYZ]
AC(LD)(7), SC(CLR)
0 1 0 1 0 0 X AC ¬ MDR (7) , SC ¬ 0 (8) (8)
0 0 1 1 0 1 X MAR ¬ IR (5) MAR(LD)(5)
0 1 0 0 0 1 X MDR ¬ AC (9) MDR(LD)(9) M[XYZ] ¬ A
0 1 0 1 0 1 X M[MAR] ¬ MDR (10) , W ¬ 1 (11), SC ¬ 0 (8) SC(CLR)(8) ,)11()W(
0 0 1 1 1 0 X MAR ¬ IR (5) MAR(LD)(5)
0 1 0 0 1 0 X MDR ¬ M[MAR] (2) , R ¬ 1 (6) MDR(LD)(2), (R)(6) A ¬ A + M[XYZ]
AC(LD)(7), (ADD)
0 1 0 1 1 0 X ALUB ¬ MDR, ADD ¬ 1 (12) , AC ¬ALUR, SC ¬ 0 (8) (12), SC(CLR)(8)
0 0 1 1 1 1 X SC ¬ 0 (8) SC(CLR)(8)
BRC XYZ
0 0 1 1 1 1 1 PC ¬ IR (13) PC(LD)(13)
ROM Input and Output Signals
MDR(LD2)
MAR (LD)
MDR(LD)
MAR(LD)
MDR(LD)
PC(CLR)
SC(CLR)
PC(INC)
AC(LD)
PC(LD)
IR(LD)
(ADD)
(W)
(R)
Reset Q2 Q1 Q0 IR(15) IR(14) C
0 1 2 3 4 5 6 7 8 9 10 11 12 13
1 X X X X X X 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 X X X 0 1 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 X X X 0 0 1 1 0 0 1 0 0 0 0 0 0 0
0 0 1 0 X X X 0 0 0 0 1 0 0 0 0 0 0 0 0 0
0 0 1 1 0 0 X 0 0 0 0 0 1 0 0 0 0 0 0 0 0
0 1 0 0 0 0 X 0 0 1 0 0 0 1 0 0 0 0 0 0 0
0 1 0 1 0 0 X 0 0 0 0 0 0 0 1 1 0 0 0 0 0
0 0 1 1 0 1 X 0 0 0 0 0 1 0 0 0 0 0 0 0 0
0 1 0 0 0 1 X 0 0 0 0 0 0 0 0 0 1 0 0 0 0
0 1 0 1 0 1 X 0 0 0 0 0 0 0 0 1 0 1 1 0 0
0 0 1 1 1 0 X 0 0 0 0 0 1 0 0 0 0 0 0 0 0
0 1 0 0 1 0 X 0 0 1 0 0 0 1 0 0 0 0 0 0 0
0 1 0 1 1 0 X 0 0 0 0 0 0 0 0 1 0 0 0 1 0
0 0 1 1 1 1 X 0 0 0 0 0 0 0 0 1 0 0 0 0 0
0 0 1 1 1 1 1 0
IR(14) 0 0 0 0 0 0 0 0 0 0 0 0 1
IR(15)
Reset
SC0
SC1
SC2
A0 C
A1
A2
A3
A4
A5
A6
Bits 14 * 27
ROM
10
11
12
13
0
1
2
3
4
5
6
7
8
9
