Basic Terms

• Bit: A digit of the binary number { 0 or 1 }

• Nibble: 4 bit Byte: 8 bit word: 16 bit
• Double word: 32 bit
• Data: binary number/code operated by an
instruction
• Address: Identification number for memory
locations
• Clock: square wave used to synchronize various
devices in µP
• Memory Capacity = 2^n ,
n->no. of address lines
1
 BUS CONCEPT
• BUS: Group of conducting lines that carries data ,
address & control signals.
CLASSIFICATION OF BUSES:
1.DATA BUS: group of conducting lines that carries
data.
2. ADDRESS BUS: group of conducting lines that
carries address.
3.CONTROL BUS: group of conducting lines that
carries control signals {RD, WR etc}
CPU BUS: group of conducting lines that directly
connected to µP
SYSTEM BUS: group of conducting lines that carries
data , address & control signals in a µP system
2
 TRISTATE LOGIC
3 logic levels are:
• High State (logic 1)
• Low state (logic 0)
• High Impedance state

High Impedance:  output is not being driven to any defined logic level

by the output circuit.

3
 Microprocessor
• Microprocessor (µP) is the “brain” of a computer
that has been implemented on one
semiconductor chip.
• The word comes from the combination micro and
processor.
• Processor means a device that processes
whatever(binary numbers, 0’s and 1’s)
 To process means to manipulate. It describes all
manipulation.
 Micro - > extremely small

4
Definition of a Microprocessor.
The microprocessor is a
programmable device that takes in numbers,
performs on them arithmetic or logical
operations according to the program stored in
memory and then produces other numbers as
a result.

5
 Microprocessor ?

A microprocessor is multi
programmable clock driven
register based semiconductor
device that is used to fetch ,
process & execute a data
within fraction of seconds.
6
 Applications
• Calculators
• Accounting system
• Games machine
• Instrumentation
• Traffic light Control
• Multi user, multi-function environments
• Military applications
• Communication systems

8
 Microprocessors
• CPU for Computers
• No RAM, ROM, I/O on CPU chip itself
• Example: Intel's x86, Motorola’s 680x0

9
 Microcontroller
• A smaller computer
• On-chip RAM, ROM, I/O ports...
• Example: Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and
PIC

10
Microprocessor vs. Microcontroller
Microprocessor Microcontroller
• CPU is stand-alone, RAM, • CPU, RAM, ROM, I/O and timer
ROM, I/O, timer are separate are all on a single chip

• Designer can decide on the • Fix amount of on-chip ROM,

amount of ROM, RAM and I/O RAM, I/O ports
ports.
• For applications in which cost,
• General-purpose power and space are critical

• Single-purpose
• Access times for memory and
I/O devices are more. • Less access times for built-in
memory and I/O devices.
• Microprocessor based • Microcontroller based system
system requires more requires less hardware reducing PCB
size and increasing the reliability
11
hardware.
 Microcontrollers Applications
• Home
– Appliances, intercom, telephones, security systems, garage door
openers, answering machines, fax machines, home computers,
TVs, cable TV tuner, VCR, camcorder, remote controls, video
games, cellular phones, musical instruments, sewing machines,
lighting control, paging, camera, pinball machines, toys, exercise
equipment etc.

Office
– Telephones, computers, security systems, fax machines,
microwave, copier, laser printer, color printer, paging etc.

• Auto
– Trip computer, engine control, air bag, ABS, instrumentation,
security system, transmission control, entertainment, climate
control, cellular phone, keyless entry 12
13
8051 CPU Operation
1. Pin Diagram
2. Block Diagram

14
Pin Diagram of the 8051

15
General Block Diagram of 8051

Interrupt 4K 128 B
Control ROM RAM

CPU

Bus Serial
OSC 4 I/O Ports
Control Port

TXD RXD
P0 P1 P2 P3 16
Detailed Block Diagram

17
 Program Status Word [PSW]

C AC F0 RS1 RS0 OV F1 P
Carry Parity
Auxiliary Carry User Flag 1

User Flag 0 Register Bank Select Overflow

18
19
BEFORE EXECUTION AFTER
EXECUTION

A 00H MOV A, #0CH A 0CH

BEFORE AFTER
EXECUTION EXECUTION

B 00H MOV B, #F8H B F8H

20
BEFORE EXECUTION AFTER
EXECUTION
A 0CH ADD A, B A 04H

B F8H B F8H

AC

1
A = 0000 1100
B = 1111 1000 A = 0CH
0000 0100 B = F8H
1
1 04H

CY
CY

21
8051 instructions that affects flag

22
 Special
Function
Register [SFR]
23
Special Function Registers [SFR]

24
 SFR Registers & their Addresses
MOV 0E0H,#55H ;is the same as
MOV A,#55H ;which means load 55H into A (A=55H)

MOV 0F0H,#25H ;is the same as

MOV B,#25H ;which means load 25H into B (B=25H)

MOV 0E0H,R2 ;is the same as

MOV A,R2 ;which means copy R2 into A

MOV 0F0H,R0 ;is the same as

MOV B,R0 ;which means copy R0 into B

25
 8051
Memory Space
26
 8051 Memory Structure

External

External
60K

64K 64K

SFR

EXT INT 4K
128
EA = 0 EA = 1

Program Memory Data Memory

27
 128 Byte RAM
• There are 128 bytes of RAM in the 8051.
– Assigned addresses 00H to 7FH
• The 128 bytes are divided into 3 different General Purpose
Area
groups as follows:
1.A total of 32 bytes from locations 00H BIT Addressable
to 1FH are set aside for register banks 128Area BYTE
and the stack. INTERNAL RAM
Reg Bank 3
2.A total of 16 bytes from locations 20H
Reg Bank 2
to 2FH are set aside for bit-addressable Register Banks
read/write memory. Reg Bank 1

3.A total of 80 bytes from locations 30H Reg Bank 0

to 7FH are used for read and write

28
storage, called scratch pad.
8051 RAM with addresses

29
 8051 Register Bank Structure

Bank 3 R0 R1 R2 R3 R4 R5 R6 R7
Bank 2 R0 R1 R2 R3 R4 R5 R6 R7
Bank 1 R0 R1 R2 R3 R4 R5 R6 R7
Bank 0 R0 R1 R2 R3 R4 R5 R6 R7

30
8051 Register Banks with address

31
8051 Programming Model

32
 8051 Stack
• The stack is a section of RAM used by the CPU to
store information temporarily.
– This information could be data or an address

• The register used to access the stack is called the

SP (stack pointer) register
– The stack pointer in the 8051 is only 8 bit wide, which
means that it can take value of 00 to FFH

33
 8051 Stack
• The storing of a CPU register in the stack is called a PUSH
– SP is pointing to the last used location of the stack
– As we push data onto the stack, the SP is incremented
by one
– This is different from many microprocessors

• Loading the contents of the stack back into a CPU register is

called a POP
– With every pop, the top byte of the stack is copied to the
register specified by the instruction and the stack pointer
is decremented once
34
 PUSH DPL
PUSH DPH
INITIAL POSITION

(1) STACK
POINTER
INCREMENTS SP & STORES DPL

(2) STACK POINTER DPL

INCREMENTS SP & STORES DPH

(3) STACK
POINTER DPH
DPL

35
BEFORE EXECUTION

SP 07H
09H

08H
DPH 10 DPL 50
07H

PUSH DPL
PUSH DPH
AFTER EXECUTION
09H 10
SP 09H

08H 50
DPH 10 DPL 50
07H

36
 POP
DPL
POP INITIAL POSITION AND READS DATA 1
DPH
(1) STACK DATA 1
POINTER

DECREMENTS SP & READS DATA 2

DATA 1
(2) STACK DATA 2
POINTER

DECREMENTS SP

DATA 1
DATA 2
(3) STACK
POINTER 37
 BEFORE EXECUTION

09H 30
SP 09H
08H 50
DPH DP
L 07H
POP DPL
POP DPH

AFTER EXECUTION

09H 30
SP 07H 08H 50
DP 5 DP 30 07H
H 0 L 38
External memory
 8051
Addressing
Modes
40
8051 Addressing Modes

41
 1. Immediate Addressing Mode
• The source operand is a constant
• The immediate data must be preceded by the hash sign, “#”
• Can load information into any registers, including 16-bit DPTR
register
– DPTR can also be accessed as two 8-bit registers, the high byte DPH and
low byte DPL

42
 2. Register Addressing Mode
• Use registers to hold the data to be manipulated.

• The source and destination registers must match in size.

MOV DPTR,A will give an error

• The movement of data between Rn registers is not allowed

MOV R4,R7 is invalid
43
 3. Direct Addressing Mode
• The entire 128 bytes of internal RAM and SFR’s
can be accessed directly.
• Contrast this with immediate addressing mode,
there is no “#” sign in the operand.

44
 4. Stack Addressing Mode
• Only direct addressing mode is allowed for pushing or popping the
stack.

• PUSH A is invalid.

• Pushing the accumulator onto the stack must be coded as PUSH

0E0H.

45
5. Register Indirect Addressing Mode
• A register is used as a pointer to the data.
• Only register R0 and R1 are used for this purpose.
• R2 – R7 cannot be used to hold the address of an
operand located in RAM.
• When R0 and R1 hold the addresses of RAM
locations, they must be preceded by the “@” sign.

46
 Examples
• Write a program to copy the value 55H into RAM memory locations 40H to 41H
using (a) direct addressing mode, (b) register indirect addressing mode without
a loop, and (c) with a loop.

47
 6. External Direct
• External Memory is accessed.

• There are only two commands that use External

Direct addressing mode:
– MOVX A, @DPTR
MOVX @DPTR, A

• DPTR must first be loaded with the address of

external memory.
48
 7. Index
• Only program memory (also called code
memory) can be accessed.
• Either DPTR or PC can be used as an index
register
• The letter ‘C’ indicates code memory.
MOVC A, @A+DPTR
MOVC @A+PC, A
INSTRUCTION
SET OF
8051
50
 8051 Instruction Set
• The instructions are grouped into 5 groups
– Data Transfer
– Logic
– Arithmetic
– Bit level
– Control Transfer

51
Programs - 8051
Examples - University Question
 UNIT-5
INTERFACING
MICROCONTROLLER

62
 8051
TIMERS
63
 TIMER REGISTERS
TIMER REGISTERS

TIMER I REGISTER TIMER 0 REGISTER

TH I TL I TH 0 TL 0
(8 bit) (8 bit) (8 bit) (8 bit)

16 bit 16 bit

TIMER/COUNTER CONTROL
REGISTER (TCON)
8 bit

TIMER/COUNTER MODE
REGISTER (TMOD)
8 bit
 TMOD Register

GATE:
When set, counter 0/1 is enabled, if INTx pin is high and
TRx is set.
When cleared, timer 0/1 is enabled, if TRx bit set.

C/T*:
When set, counter operation (input from Tx input pin).
When cleared, timer operation (input from internal clock).

65
 TMOD Register

The TMOD byte is not bit addressable.

66
TCON Register

67
 8051 Timer/Counter
OSC ÷12
C /T  0 TLx THx TFx
(8 Bit) (8 Bit) (1 Bit)
C /T 1

T PIN
INTERRUPT
TR

Gate

INT PIN
68
8051 TIMERS
8051 –Timer
OPERATING
Modes MODES

Timer 0 Timer 1

Mode 0 Mode 0

Mode 1 Mode 1

Mode 2 Mode 2

Mode 3

69
 TIMER 0 / 1
OSC ÷12
C /T  0
TL 0/1 TH 0/1 TF0
C /T 1

T 0 PIN
TR 0 INTERRUPT

Gate

INT 0 PIN
70
 TIMER 0 – Mode 0
13 Bit Timer / Counter

OSC ÷12
C /T  0 TL0 TH0 INTERRUPT
C /T 1 TF0
T 0 PIN (5 Bit) (8 Bit)
TR 0

Gate

INT 0 PIN

Maximum Count = 1FFFH or

(0001111111111111)b or (8191)d 71
 TIMER 0 – Mode 1
16 Bit Timer / Counter

OSC ÷12
C /T  0 TL0 TH0 INTERRUPT
C /T 1 TF0
T 0 PIN (8 Bit) (8 Bit)
TR 0

Gate

INT 0 PIN

Maximum Count = FFFFH (1111111111111111)b

or (65535)d 72
 TIMER 0 – Mode 2
8 Bit Timer / Counter with AUTORELOAD

OSC ÷12
C /T  0 TL0 TH0 INTERRUPT
C /T 1 TF0
T 0 PIN (8 Bit) (8 Bit)
TR 0

Gate Reload

INT 0 PIN

TH0
(8 Bit)

Maximum Count = FFH or (11111111)b or (255)d

73
 TIMER 0 – Mode 3
Two - 8 Bit Timer / Counter

OSC ÷12
C /T  0 TL0 INTERRUPT
C /T 1 TF0
T 0 PIN (8 Bit)
TR 0

Gate

INT 0 PIN

OSC ÷12 TH0 INTERRUPT

TF1
(8 Bit)

TR1
74
 TIMER 1
OSC ÷12
C /T  0
TL1 TH1 TF1
C /T 1

T 1PIN
INTERRUPT
TR1

Gate

INT 1 PIN
75
 TIMER 1 – Mode 0
13 Bit Timer / Counter

OSC ÷12
C /T  0 TL1 TH1 INTERRUPT
C /T 1 TF1
T 1PIN (5 Bit) (8 Bit)
TR1

Gate

INT 1 PIN

Maximum Count = 1FFFH or

(0001111111111111)b or (8191)d 76
 TIMER 1 – Mode 1
16 Bit Timer / Counter

OSC ÷12
C /T  0 TL1 TH1 INTERRUPT
C /T 1 TF1
T 1PIN (8 Bit) (8 Bit)
TR1

Gate

INT 1 PIN

Maximum Count = FFFFH (1111111111111111)b

or (65535)d 77
 TIMER 1 – Mode 2
8 Bit Timer / Counter with AUTORELOAD

OSC ÷12
C /T  0 TL1 TH1 INTERRUPT
C /T 1 TF1
T 1PIN (8 Bit) (8 Bit)
TR1

Gate Reload

INT 1 PIN

TH1
(8 Bit)

Maximum Count = FFH or (11111111)b or (255)d

78
 Programming Timers
• Example: Indicate which mode and which timer are
selected for each of the following.
(a) MOV TMOD, #01H (b) MOV TMOD, #20H (c) MOV
TMOD, #12H

• Solution: We convert the value from hex to binary.

(a) TMOD = 00000001, mode 1 of timer 0 is selected.
(b) TMOD = 00100000, mode 2 of timer 1 is selected.
(c) TMOD = 00010010, mode 2 of timer 0, and mode 1 of timer
1
are selected.
79
 Programming Timers
• Find the timer’s clock frequency and its period for
various 8051-based system, with the crystal frequency
11.0592 MHz when C/T bit of TMOD is 0.

• Solution:

1/12 × 11.0529 MHz = 921.6 MHz;

T = 1/921.6 kHz = 1.085 us

80
8051
Serial
Port 84
 Basics of Serial Communication
• Computers transfer data in two ways:
– Parallel: Often 8 or more lines (wire conductors) are used to
transfer data to a device that is only a few feet away.
– Serial: To transfer to a device located many meters away,
the serial method is used. The data is sent one bit at a time.

85
 Basics of Serial Communication
• Serial data communication uses two methods
– Synchronous method transfers a block of data at a
time

– Asynchronous method transfers a single byte at a time

• There are special IC’s made by many

manufacturers for serial communications.
– UART (universal asynchronous Receiver transmitter)

– USART (universal synchronous-asynchronous Receiver-

transmitter)
86
 Asynchronous – Start & Stop Bit
• Asynchronous serial data communication is widely used
for character-oriented transmissions
– Each character is placed in between start and stop bits, this is
called framing.
– Block-oriented data transfers use the synchronous method.

• The start bit is always one bit, but the stop bit can be
one or two bits

• The start bit is always a 0 (low) and the stop bit(s) is 1

(high)
87
Asynchronous – Start & Stop Bit

88
 Data Transfer Rate
• The rate of data transfer in serial data communication is
stated in bps (bits per second).

• Another widely used terminology for bps is baud rate.

– It is modem terminology and is defined as the number of
signal changes per second
– In modems, there are occasions when a single change of
signal transfers several bits of data

• As far as the conductor wire is concerned, the baud

rate and bps are the same.
89
Registers related to Serial
Communication

1. SBUF Register

2. SCON Register

3. PCON Register

90
 SBUF Register
• SBUF is an 8-bit register used solely for serial communication.
• For a byte data to be transferred via the TxD line, it must be
placed in the SBUF register.
• The moment a byte is written into SBUF, it is framed with the
start and stop bits and transferred serially via the TxD line.
• SBUF holds the byte of data when it is received by 8051 RxD
line.
• When the bits are received serially via RxD, the 8051 deframes
it by eliminating the stop and start bits, making a byte out of
the data received, and then placing it in SBUF.

91
 SCON Register

SM0 SM1 SM2 REN TB8 RB8 TI RI

Set when a Cha-

ractor received
Set to Enable
Serial Data
reception Set when Stop bit Txed

Enable Multiprocessor 9th Data Bit 9th Data Bit

Communication Mode Sent in Mode 2,3 Received in Mode 2,3

93
Programming Serial Data Transmission
1. TMOD register is loaded with the value 20H, indicating the use of timer 1
in mode 2 (8-bit auto-reload) to set baud rate.
2. The TH1 is loaded with one of the values to set baud rate for serial data
transfer.
3. The SCON register is loaded with the value 50H, indicating serial mode 1,
where an 8- bit data is framed with start and stop bits.
4. TR1 is set to 1 to start timer 1
5. TI is cleared by CLR TI instruction
6. The character byte to be transferred serially is written into SBUF register.
7. The TI flag bit is monitored with the use of instruction JNB TI, xx to see if
the character has been transferred completely.
8. To transfer the next byte, go to step 5

94
Programming Serial Data Transmission
1. TMOD register is loaded with the value 20H, indicating the use of timer 1
in mode 2 (8-bit auto-reload) to set baud rate.
2. The TH1 is loaded with one of the values to set baud rate for serial data
transfer.
3. The SCON register is loaded with the value 50H, indicating serial mode 1,
where an 8- bit data is framed with start and stop bits.
4. TR1 is set to 1 to start timer 1
5. TI is cleared by CLR TI instruction
6. The character byte to be transferred serially is written into SBUF register.
7. The TI flag bit is monitored with the use of instruction JNB TI, xx to see if
the character has been transferred completely.
8. To transfer the next byte, go to step 5

95
Programming examples
 Programming Serial Data Reception
1. TMOD register is loaded with the value 20H, indicating the use of timer 1
in mode 2 (8-bit auto-reload) to set baud rate.
2. TH1 is loaded to set baud rate
3. The SCON register is loaded with the value 50H, indicating serial mode 1,
where an 8- bit data is framed with start and stop bits.
4. TR1 is set to 1 to start timer 1
5. RI is cleared by CLR RI instruction
6. The RI flag bit is monitored with the use of instruction JNB RI, xx to see if
an entire character has been received yet
7. When RI is raised, SBUF has the byte, its contents are moved into a safe
place.
8. To receive the next character, go to step 5.
98
Programming examples
 Doubling Baud Rate
• There are two ways to increase the baud rate of data
transfer
1. By using a higher frequency crystal
2. By changing a bit in the PCON register

• PCON register is an 8-bit register.

•When 8051 is powered up, SMOD is zero

•We can set it to high by software and thereby double the baud rate.

101
Doubling Baud Rate (cont…)

102
 8051
Interrupts
103
INTERRUPTS

104
 Interrupt Vs Polling
1. Interrupts
– Whenever any device needs its service, the device notifies the
microcontroller by sending it an interrupt signal.
– Upon receiving an interrupt signal, the microcontroller interrupts
whatever it is doing and serves the device.
– The program which is associated with the interrupt is called the
interrupt service routine (ISR) or interrupt handler.
2. Polling
– The microcontroller continuously monitors the status of a given
device.
– When the conditions met, it performs the service.
– After that, it moves on to monitor the next device until every one is
serviced.

105
 Interrupt Vs Polling
• The polling method is not efficient, since it wastes much of the
microcontroller’s time by polling devices that do not need
service.
• The advantage of interrupts is that the microcontroller can serve
many devices (not all at the same time).
• Each devices can get the attention of the microcontroller based
on the assigned priority.
• For the polling method, it is not possible to assign priority since it
checks all devices in a round-robin fashion.

• The microcontroller can also ignore (mask) a device request for

service in Interrupt.
106
 Steps in Executing an Interrupt
1. It finishes the instruction it is executing and saves the address of the
next instruction (PC) on the stack.
2. It also saves the current status of all the interrupts internally (i.e: not
on the stack).
3. It jumps to a fixed location in memory, called the interrupt vector
table, that holds the address of the ISR.
4. The microcontroller gets the address of the ISR from the interrupt
vector table and jumps to it.
5. It starts to execute the interrupt service subroutine until it reaches the
last instruction of the subroutine which is RETI (return from interrupt).
6. Upon executing the RETI instruction, the microcontroller returns to the
place where it was interrupted.

107
 Six Interrupts in 8051
Six interrupts are allocated as follows:
1.Reset – power-up reset.

2.Two interrupts are set aside for the timers.

– one for timer 0 and one for timer 1

3.Two interrupts are set aside for hardware

external interrupts.
– P3.2 and P3.3 are for the external hardware
interrupts INT0 (or EX1), and INT1 (or EX2)

4.Serial communication has a single interrupt that

belongs to both receive and transfer. 108
 What events can trigger Interrupts?
• We can configure the 8051 so that any of the
following events will cause an interrupt:

– Timer 0 Overflow.
– Timer 1 Overflow.
– Reception/Transmission of Serial Character.
– External Event 0.
– External Event 1.

• We can configure the 8051 so that when Timer 0

Overflows or when a character is sent/received, the
appropriate interrupt handler routines are called.
109
8051 Interrupt Vectors

110
Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode
 8051 Interrupt related Registers
• The various registers associated with the use of
interrupts are:
– TCON - Edge and Type bits for External Interrupts 0/1

– SCON - RI and TI interrupt flags for RS232

– IE - Enable interrupt sources

– IP - Specify priority of interrupts

111
 Enabling and Disabling an Interrupt
• Upon reset, all interrupts are disabled (masked),
meaning that none will be responded to by the
microcontroller if they are activated.

• The interrupts must be enabled by software in order

for the microcontroller to respond to them.

• There is a register called IE (interrupt enable) that is

responsible for enabling (unmasking) and disabling
(masking) the interrupts.
112
 Interrupt Enable (IE) Register

--

• EA : Global enable/disable.
• --- : Reserved for additional interrupt hardware.

MOV IE,#08h
• ES : Enable Serial port interrupt.
or • ET1 : Enable Timer 1 control bit.
SETB ET1
• EX1 : Enable External 1 interrupt.
• ET0 : Enable Timer 0 control bit.
• EX0 : Enable External 0 interrupt.
113
 Enabling and Disabling an Interrupt
• Example: Show the instructions to (a) enable the serial interrupt,
timer 0 interrupt, and external hardware interrupt 1 and (b) disable
(mask) the timer 0 interrupt, then (c) show how to disable all the
interrupts with a single instruction.
• Solution:

– (a) MOV IE,#10010110B ;enable serial, timer 0, EX1

• Another way to perform the same manipulation is:
– SETB IE.7 ;EA=1, global enable
– SETB IE.4 ;enable serial interrupt
– SETB IE.1 ;enable Timer 0 interrupt
– SETB IE.2 ;enable EX1

– (b) CLR IE.1 ;mask (disable) timer 0 interrupt only

– (c) CLR IE.7 ;disable all interrupts
114
 Interrupt Priority
• When the 8051 is powered up, the priorities are assigned according to
the following.

• In reality, the priority scheme is nothing but an internal polling

sequence in which the 8051 polls the interrupts in the sequence listed
and responds accordingly.

115
 Interrupt Priority
• We can alter the sequence of interrupt priority by assigning a
higher priority to any one of the interrupts by programming a
register called IP (interrupt priority).
• To give a higher priority to any of the interrupts, we make the
corresponding bit in the IP register high.

116
 Interrupt Priority (IP) Register

Reserved PS PT1 PX1 PT0 PX0

Serial Port
INT 0 Pin
Timer 1 Pin

INT 1 Pin Timer 0 Pin

Priority bit=1 assigns high priority

Priority bit=0 assigns low priority
117
 KEYBOARD INTERFACING
• Keyboards are organized in a matrix of rows
and columns
The CPU accesses both rows and columns
through ports .
• ƒTherefore, with two 4-bit ports, an 4 x 4
matrix of keys can be connected to a
microprocessor
When a key is pressed, a row and a
column make a contact
121
• Otherwise, there is no connection
between rows and columns
• ‰In IBM PC keyboards, a single
microcontroller takes care of hardware
and software interfacing
• A 4x4 matrix connected to two ports
The rows are connected to an
input port and the columns are
connected to an output port

123