VIDEO LECTURE

ON
MICROPROCESSORS
&
MICROCONTROLLERS
BY
K.RAVICHANDRA
ASST.PROF/ECE
VISVODAYA ENGINEERING COLLEGE,
KAVALI,SPSR NELLORE (DT.), ANDHRA PRADESH – 524201
 UNIT-1
1. Introduction to Microcomputer
2. Introduction to 8086 µp
3. Architecture of 8086 µp
- Block diagram of 8086
- Registers of 8086
- Memory Segmentation
- 20 bit Physical address calculation
4. Pin configuration of 8086
5. Min. Mode operation of 8086 with Timing diagram
6. Max. Mode operation of 8086 with Timing diagram
7. 8086 Interrupts and Interrupt Vector Table
 Bit: A bit is a single binary digit.
 Word: A word refers to the basic data size or bit size that
can be processed by the arithmetic and logic unit of the
processor. A 16-bit binary number is called a word in a
16-bit processor.
 Bus: A bus is a group of wires/lines that carry similar
information.
 System Bus: The system bus is a group of wires/lines
used for communication between the microprocessor and
peripherals.
 Memory Word: The number of bits that can be stored in
a register or memory element is called a memory word.
 Address Bus: It carries the address, which is a unique
binary pattern used to identify a memory location or an I/O
port. For example, an eight bit address bus has eight lines
and thus it can address 2^8 = 256 different locations. The
locations in hexadecimal format can be written as 00H –
FFH.
 Data Bus: The data bus is used to transfer data between
memory and processor or between I/O device and
processor. For example, an 8-bit processor will generally
have an 8-bit data bus and a 16-bit processor will have 16-
bit data bus.
 Control Bus: The control bus carry control signals, which
consists of signals for selection of memory or I/O device
from the given address, direction of data transfer and
synchronization of data transfer in case of slow devices.
8086 FEATURES
1. The 8086 is a 16-bit µp
2. It has 16-bit ALU

3. It has 16-bit data bus and 20-bit address bus

4. It can address 220 locations i.e., 1 M Bytes of memory

5. It can address 64K I/O ports

6. It uses memory segmentation

7. It has multiplexed address and data pins AD0-AD15

8. It uses 2-stage pipeline concept – Fetch and Execute

9. It has 6-bytes of Instruction Queue

10. Can be operated in 2 modes: Min. mode & Max. Mode

11. Available in 3 clock rates: 5 MHz, 10 MHz & 8 MHz

12. It is packaged in 40-pin DIP

 ARCHITECTURE OF 8086
The complete architecture of 8086 is divided into two parts - Bus Interface Unit (BIU)
and Execution Unit (EU). These two parts are operated in parallel for implementing
pipeline.

Bus interface unit (BIU) :

1. The BIU handles all transfer of address, data and code on Buses.
2. It sends out 20-bit Physical address, fetches instruction code bytes from memory and
stores them in Instruction Queue.
3. The BIU is responsible for all read & write operations of Memory and I/O.
4. The BIU consists of
(i) Instruction Queue
(ii) Segment Registers
(iii) Instruction Pointer
(iv) 20-bit Physical address calculation circuit
(i) Instruction Queue:

 While EU is executing an instruction, the BIU will fetch upto

6- instruction code bytes from memory and stores them in a
FIFO group of registers called as Instruction Queue.
 When EU is ready for its next instruction, it simply takes
instruction bytes from Instruction Queue.
 Thus the pipelining concept is implemented in 8086 using an
Instruction Queue.

 Note that the Instruction Queue fails in the case of Branch

instructions (JMP, CALL, RET ..), because, the program
execution jumps to different location.
(ii) Segment Registers

 The 8086 uses memory segmentation. In this scheme, the complete 1 MB

memory is divided into number of logical segments.

 The size of each segment is 64 KB and is addressed by one of the segment

registers.

 The segment registers are used to define the starting address of logical
segments.

 The segment register holds the upper 16-bits of starting address of logical
segments. The BIU inserts ZERO’s for lower 4-bits of 20-bit starting
address.
(iii) Instruction Pointer (IP):

 The IP register holds the offset address of the next

instruction to be fetched from Code segment.

 The Offset address is defined as the distance of operand

from the Starting address of the Segment.
(iv) 20-bit Physical address calculation

 The BIU has a Physical Address Generation Circuit.

 It generates the 20-bit physical address by adding Segment base to the
Offset address.

 The segment register defines the segment base i.e., starting address of a
segment.

 A location within a segment can be addressed by 16-bit offset address.

For example, if CS= 2000H and IP= 5678H then

Segment base = CS*10 = 20000 H
Offset address = IP = 5678 H
20-bit Physical address = Segment base + Offset = 25678 H
For example, if CS= 2000H and IP= 5678H then
Segment base = CS*10 = 20000 H
Offset address = IP = 5678 H
20-bit Physical address = Segment base + Offset = 25678 H
Execution Unit (EU) :
 The Execution unit is responsible for decoding and executing the
instructions.
 It receives instruction code bytes from Instruction Queue in BIU,
decodes and executes them.
 The EU consists of

(i) 16-bit ALU

(ii) General purpose registers: AX,BX,CX,DX
(iii) Index Registers : SI and DI
(iv) Pointers : SP and BP
(v) Flag Register/Program Status Word (PSW)
(i) 16-bit ALU :

 The EU consists of 16-bit ALU which can perform

Arithmetic operations (such as Addition, Subtraction,
Multiplication, Division, Increment, Decrement, etc)
and Logic operations (such as Logic AND, OR, NOT, Ex-
OR, Shift, Rotate, etc)
(ii) General purpose registers :

 The8086 has 4- general purpose registers - AX, BX,

CX, DX used to store 16-bit data

 Each register is divided into TWO 8-bit registers to

store 8-bit data.

 Each register has a special function, shown in the

following table.
Register Name Purpose
Used to hold the results of operations
AX Accumulator
like MUL, DIV, Shift, Rotate…etc
Used to hold the offset address
BX Base Index
(Based addressing)
Used as a counter in LOOP and String
CX Counter
instructions.
Data Index It is used to hold the 16-bit I/O port
(or) address during I/O operation.
DX
Extended It is also used to hold a part of result
Accumulator from MUL & DIV.
REGISTER ORGANIZATION
(iii) Index Registers :

 The Index Registers are used to hold the 16-bit offset address of data stored in Data
and Extra segments.
 These registers are used in string operations to hold the offset address of Source string
and Destination strings.

 The SI holds the offset address of source string in Data Segment.

 The DI holds the offset address of destination string in Extra Segment.
Address of source string  DS:[SI]
Address of destination string  ES:[DI]

 The directional flag (DF) selects either increment (or) decrement mode for SI and DI
registers during String instructions manipulation.
DF=0 selects increment mode and
DF = 1 selects decrement mode
(iv) Pointers :

 The Pointers are used to hold the offset address relative to data
and stack segments.

 The base pointer (BP) is used to access data in stack segment.

 The stack pointer (SP) is used to hold the address of stack top.
(v) Flag Register / Program Status Word (PSW)

 The flag register is used to indicate the status information (or) condition
produced by an instruction execution.
 The 8086 has 6- status flags and 3-control flags.
 
Conditional Flags / Status Flags :
 These flags are Set or Reset according to the condition produced by an
instruction execution.
 The 6- conditional flags of 8086 are CF, PF, AF, ZF, SF, OF

 
Control flags:
 These flags control the operation of the processor.
 The 3- control flags of 8086 are DF, IF, TF.
FLAG REGISTER / PSW

Carry Flag (CF) :

It is set to 1, if a carry is generated in Addition (or) Subtraction
 
Parity Flag(PF) :
It is set to 1, if the result of an operation has even number of 1’s
 
Auxiliary carry Flag (AF) : It is used in BCD operations.
It is set to 1, if addition of lower nibble generates a carry.
 
Zero Flag (ZF) : It is set to 1, if the result of an operation is ZERO
 
Sign Flag (SF) : It is used with signed numbers only.
SF=1 for –ve results and SF =0 for +ve results

Overflow Flag (OF) :

It is set to 1, if the result of a signed operation overflows into Sign bit
 
Directional Flag (DF) :
 It is used in string operations to select either increment (or) decrement mode
for SI and DI registers.
 If DF = 1, The SI & DI registers are automatically decremented after the
execution of string instruction.
 If DF = 0, The SI & DI registers are automatically incremented after the
execution of string instruction.

Interrupt Flag (IF) :

 If IF = 1, all the maskable interrupts are recognized and processed by the
CPU. Otherwise, the maskable interrupts are ignored and not processed by
CPU.

Trap Flag (TF) :

 It is used for debugging purpose

 If TF = 1, the processor enters the ‘Single step execution mode’ i.e., the 8086
gets interrupted automatically at the end of every instruction execution.
MEMORY SEGMENTATION
 The 8086 uses memory segmentation. In this scheme, the
complete 1 MB memory is divided into number of logical
segments.

 The size of each segment is 64 KB and is addressed by one of

the segment registers.

 Note that the 8086 does not work the whole 1 MB memory at
any given time. However it works only with four segments at
any given instant of time.
MEMORY SEGMENTATION
 The four segment registers define the starting addresses of the
four memory segments with which the 8086 is working at that
instant of time.

 The segment registers hold the upper 16-bits of starting

address of logical segments. The BIU inserts ZERO’s for
lower 4-bits of 20-bit starting address.

 The 64 KB logical segment can be located anywhere in 1 MB

memory, but the segment will always start at an address with
ZERO’s in lowest 4-bits.
Code Segment :

 The Code segment is used to store the program instruction codes.

 The Code Segment register (CS) is used define the starting address of the
Code segment.
 For example, if CS=2000H then the Code segment starts at 20000H.

Data Segment :
 The Data segment is used to store data variables and constants of the
program.
 The Data Segment register (DS) is used to define the starting address of the
Data segment.
 Data are accessed from Data segment by an Offset address.

 The SI, DI, BX, BP registers are used to store the offset address for data
segment
Extra Segment :
 The Extra segment is an additional data segment used to in String
operations.
 The Extra Segment register (ES) is used to define the starting address of
the Extra segment.

Stack Segment :
 The Stack segment defines the area of memory used for stack.

 The stack is a section of memory where the data is accessed in LIFO

manner. It is used to store data, address, and status information.
 The stack is used by the processor to store the return address during the
execution of procedures and interrupt service routines.
 The Stack Segment register (SS) is used to define the starting address of
the Stack segment.
NON OVERLAPPING SEGMENTS
OVERLAPPING SEGMENTS
20-bit Physical address calculation :

 The Bus Interface Unit generates the 20-bit Physical Address by adding
Segment base to the Offset address.

 The segment register defines the segment base i.e., starting address of a
segment.
 A location within a segment can be addressed by 16-bit offset address.

For example, if CS= 2000H and IP= 5678H then

Segment base = CS*10 = 20000 H
Offset address = IP = 5678 H
20-bit Physical address = Segment base + Offset = 25678 H
20-bit Physical address calculation :
 The segment register holds the upper 16-bits of starting address of logical
segments. The BIU inserts ZERO’s for lower 4-bits of 20-bit starting address.
Advantages of Memory Segmentation :

 Allows to access 1 MB memory with 16-bit address.

 Provides use of separate memory areas for program, data and stack

 Allows data and code protection

 Provision for relocation may be done

 Provides a powerful memory management mechanism

 Allows the processor to access the data from memory easily and
fastly, which increases the speed of operation
 VIDEO LECTURE
ON
MICROPROCESSORS
&
MICROCONTROLLERS
BY
K.RAVICHANDRA
ASST.PROF/ECE
VISVODAYA ENGINEERING COLLEGE,
KAVALI,SPSR NELLORE (DT.), ANDHRA PRADESH – 524201
PIN DIAGRAM
 The pin diagram of 8086 is shown in Figure.
 It consists of 40-pins.

 Among these, 21 are multiplexed pins to reduce the number of pins.

 The multiplexed pins are

AD0 – AD15
A16/S3 - A19/S6
and BHE / S7
 The 8086 issues two different sets of signals (Pins 24 to 31) in
Minimum mode and Maximum mode operation
AD0 - AD15 (Address / Data lines) :

 The lower order 16-address lines (A0 - A15) of 8086 are

multiplexed with 16- data lines (D0 - D15).

 During T1 state of Bus-cycle, The multiplexed bus AD0-AD15

acts as address bus and during later part of Bus-cycle this
multiplexed bus is used as Data bus.
A16/ S3 - A19/ S6 (Address/Status lines) :

 The higher order 4-address lines (A16 - A19) are multiplexed with Status lines (S3 -
S6).
S4 S3 Segment

 The status signals S3 and S4 0 0 Extra Segment

shows which segment is accessed 0 1 Stack Segment
during current bus cycle.
1 0 Code /
No Segment
 The S5 indicates the status of IF flag. 1 1 Data Segment

 The S6 is always logic 0 and it in not used.

 All the above multiplexed pins are at high-impedance state during DMA operation.
BHE/S7 :

 The 1 M bytes Physical memory of 8086 is divided into two

banks for accessing 16-bit numbers. Each bank size is 512 K
bytes.

 The Bus High Enable (BHE) signal is used to enable the higher
order data bus (D8 - D15) connected to HIGH BANK.
BHE/S7 :

 The 1 M bytes Physical memory of 8086 is divided into two banks for accessing 16-
bit numbers.
 Each bank size is 512 K bytes.

 The data bus (D0 - D7) is connected to LOW /EVEN bank.

 The data bus (D8 - D15) is connected to HIGH/ODD bank.

 The Bus High Enable (BHE) signal is used to enable to HIGH BANK which is
connected to higher order data bus (D8 - D15)

Address lines(A1-A19) are used to select a location within the bank

The LOW bank is selected by A0
The HIGH bank is selected by BHE signal.
Both Banks are enabled at a time for 16-bit operations.
Note that the address must be EVEN for 16-bit access.
NMI :
 It is a positive going edge triggered Non-Maskable Interrupt
input.
 It cannot be disabled by using software.
 This interrupt has highest priority than INTR.
 It is a vectored interrupt. The vector address of NMI is
0000:0008 H.

INTR:
 It is a level triggered maskable Interrupt Request.
 It can be disabled by using software i.e., the processor will get
interrupted only if IF=1. Otherwise the processor cannot get
interrupted even INTR is active.
 It is a non-vectored interrupt.
CLK:
 The clock input provides the basic timing for the
microprocessor and bus control activity.
 The clock frequencies of different versions of 8086 are 5
MHz, 10 MHz, 8 MHz.
 
RESET :
 It forces all the registers to a predefined values and
microprocessor gets reset.
 When Reset is active DS, ES, SS, IP and FLAG registers are
initialized to 0000H and CS is initialized to FFFF H.
 After Reset, the processor starts execution from FFFF0 H.
READY:
 A slow peripheral (or) memory device can be connected to
microprocessor through READY line.
 It is used by the MPU to sense whether the peripheral is ready
to transfer data (or) not.
 It is used to insert wait states in bus cycles as needed to
interface with slow memory & I/O.
 If READY =1, peripheral is ready to transfer data.

 If READY=0, the processor WAITS until it goes to HIGH.

TEST:
 This input is examined by WAIT instruction.

 The 8086 enters into WAIT state after the execution of WAIT
instruction.
 If TEST = 0, the WAIT instruction functions as NOP

 If TEST =1, the processor waits until TEST = 0.

RD : Read Control Signal

 This signal is active whenever the processor is ready to read data
from Memory (or) I/O.

MN/MX :
This pin is used to select the mode of operation of 8086 processor.
 MN/MX = 1 for Minimum mode operation

 MN/MX = 0 for Maximum mode operation

TEST:
 This input is examined by WAIT instruction.

 The 8086 enters into WAIT state after the execution of WAIT instruction.

 If TEST = 0, the WAIT instruction functions as NOP

 If TEST =1, the processor waits until TEST = 0.

 If the co-processor has finished its work then it makes

TEST = 0.

RD : Read Control Signal

 This signal is active whenever the processor is ready to read data from
Memory (or) I/O.

MN/MX :
This pin is used to select the mode of operation of 8086 processor.
 MN/MX = 1 for Minimum mode operation

 MN/MX = 0 for Maximum mode operation

TEST:
 This input is examined by WAIT instruction.

 The 8086 enters into WAIT state after the execution of WAIT instruction.

 If TEST = 0, the WAIT instruction functions as NOP

 If TEST =1, the processor waits until TEST = 0.

 If the co-processor has finished its work then it makes

TEST = 0.

RD : Read Control Signal

 This signal is active whenever the processor is ready to read data from
Memory (or) I/O.

MN/MX :
This pin is used to select the mode of operation of 8086 processor.
 MN/MX = 1 for Minimum mode operation

 MN/MX = 0 for Maximum mode operation

MN/MX :
This pin is used to select the mode of operation of 8086 processor.
 MN/MX = 1 for Minimum mode operation
 MN/MX = 0 for Maximum mode operation

 The 8086 can be operated in two modes – Minimum mode and

Maximum mode. The pin MN/MX is used to select the Min. (or)
Max. mode of operation. The pins(24-31) issues two different set
of signals – for minimum & maximum mode operations
MINIMUM MODE :
 The minimum mode operation is selected by connecting the pin
MN/MX to + 5 V supply
 The 8086 is operated in minimum mode in simple systems with a
single CPU
 In minimum mode operation all the control signals are generated
by CPU
 It is least expensive way to operate and the operation is similar to
8085A.
 VIDEO LECTURE
ON
MICROPROCESSORS
&
MICROCONTROLLERS
BY
K.RAVICHANDRA
ASST.PROF/ECE
VISVODAYA ENGINEERING COLLEGE,
KAVALI,SPSR NELLORE (DT.), ANDHRA PRADESH – 524201
 The locations from FFFF0H to FFFFFH are reserved for
operations including jump to initialization program and I/O
processor initialization .
 The locations 00000H to 003FFH are reserved for interrupt
vector table.
GENERAL BUS OPERATION
 VIDEO LECTURE
ON
MICROPROCESSORS
&
MICROCONTROLLERS
BY
K.RAVICHANDRA
ASST.PROF/ECE
VISVODAYA ENGINEERING COLLEGE,
KAVALI,SPSR NELLORE (DT.), ANDHRA PRADESH – 524201
MINIMUM MODE 8086 SYSTEM
 The microprocessor 8086 is operated in minimum mode by
applying MN/MX pin to logic 1.

 •In this mode, all the control signals are given out by the
microprocessor chip itself. There is a single microprocessor in
the minimum mode system.
 •The remaining components in the system are latches,
transreceivers, clock generator, memory and I/O devices.
Some type of chip selection logic may be required for
selecting memory or I/O devices, depending upon the address
map of the system.
CLK Generator(8284) :
Generates a clock frequency of 5MHZ.

Adress latches :
These are used for demultiplexing of AD0-AD15 ,A16/S3-A19/S6 ,BHE‾/S7 Signals.
The ALE signal is used to enable the address latches.
The ALE signal indicates the presence of valid address information on
multiplexed bus.

Bidirectional data bus buffers (or) Transreceivers:

They are used to maintain proper signal quality to increase the fanout of the
system.
 The DEN‾ Signal is used to enable the data bus buffers.

 The DT/R‾ Signal is used to specify the direction of data flow through
data bus buffers.
 DT/R‾=1 =>Data transmission.
 DT/R‾=0 =>Data reception.
 The minimum mode signals are INTA‾(pin 24), ALE , DEN‾ DT/R‾, M/IO‾,
WR‾, HLDA, HOLD(pin 31).
MINIMUM MODE SIGNALS
INTA ( pin-24) :
The interrupt acknowledge signal is a response to the INTR.
It indicates the recognition of an Interrupt Request.
 
ALE (pin-25) :
The address latch enable signal is used to indicate the presence of valid address information on
multiplexed bus (AD0 - AD15 ) .
 This pin is connected to the Latch enable input of Address Latches.
 The address latches are used to separate the address and data lines.( de-multiplexing)

DEN (pin-26) :
The data bus enable signal is used to enable the bi-directional data bus buffers.
 The data bus buffers( transmitters/receivers) are used to maintain proper signal quality.

 
 DT / R (pin-27) :

The data transmit / receive signal is used to select the direction of data flow
through the data bus buffers.
DT / R = 1 for transmitting data
DT / R = 0 for receiving data
M / IO (pin-28) : This pin selects either Memory or I/O operation
M / IO = 1 selects memory operation
M / IO =0 selects I/O operation
 
WR (pin-29) :
This control signal is active whenever the processor is writing data to Memory or I/O
 
 
HOLD & HLDA (pins 31 & 30):
 These two signals are used in DMA operation

 The HOLD input indicates the processor that other bus master is requesting for the
use of system bus.
 When HOLD =1, the p stops the normal program execution and places address, data
& control buses at high-impedance state and sends HLDA signal to the DMA controller.
 The HLDA signal indicates that the processor has accepted the HOLD request and the
gain control of the system bus is transferred to the DMA controller.
 During HLDA =1 , the DMA controller is the master of the system bus.
 After removal of HOLD request, the HLDA becomes Low.
 VIDEO LECTURE
ON
MICROPROCESSORS
&
MICROCONTROLLERS
BY
K.RAVICHANDRA
ASST.PROF/ECE
VISVODAYA ENGINEERING COLLEGE,
KAVALI,SPSR NELLORE (DT.), ANDHRA PRADESH – 524201
 MAXIMUM MODE

• The max. mode operation is selected by connecting the pin MN/MX to

GND

• The 8086 is operated in max. mode in multi-processor system with more

than one processor.

• In max. mode, the control signals are generated by external Bus-

controller 8288.

• The maximum mode operation is used only when the system contains
arithmetic co-processor such as 8087 numeric co-processor.

• Max. Mode signals  QS1, QS0, S0, S1, S2, LOCK, RQ/GT1, RQ/GT0
QS1 & QS0 (pins-24&25):
 
 The Queue status pins indicate the status of Instruction Queue of 8086
processor.

QS1 QS0 Queue Status

0 0 No operation
0 1 First byte of Opcode
1 0 Queue is empty
1 1 Next byte of Opcode
S0 , S1 , S2 (pins- 26,27&28):

These status signals indicate the function of the current bus-cycle. i.e., the type
of operation being carried out by the processor.

S2 S1 S0 Bus cycle
0 0 0 INTA
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode Fetch
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 Inactive
LOCK : ( pin-29)

 This pin indicates that the processor is executing a LOCK prefixed

instruction and the System bus is not to be used by another bus-master.
 This pin is used in multi-processor system to prevent other Bus masters from
taking the control of System bus during the execution of a critical
instruction.
 
RQ/GT1 & RQ/GT0: ( pins-30 & 31):

 The Request/Grant pins are used to request a DMA action during Maximum
mode operation.
 These are bidirectional and used to request and grant the DMA operation.
Timing diagrams for Max. mode

 Op-code fetch cycle

 Memory Read cycle
 Memory Write cycle
 I/O Read cycle
 I/O Write cycle
INTERRUPTS
 While CPU is executing a program, an interrupt break the normal sequence of
execution of instructions,diverts its execution to some other program called
Interrupt Service Routine(ISR).

 After executing ISR ,the control is transferred back again to the main program.
 Whenever a no.of devices interrupt a CPU at a time and if the processor is able
to handle them properly,it is said to have multiple interrupt processing
capability.
 8086 has two interrupt pins NMI and INTR.

 NMI :Non Maskable Interrupt

 Any interrupt at NMI cannot be masked or disabled.

 INTR interrupt may be masked using Interrupt Flag. INTR is of 256 types.

The INTR types may be from 00 to FF H. If more than one type of INTR
interrupt occurs at a time,then an external chip called Programmable Interrupt
Controller is required to handle them.
 
TYPES OF INTERRUPTS

 External interrupt: due to an external device or a signal

interrupts the processor.
 ex: keyboard interrupt

 Internal interrupt: generated internally by the processor

circuit or by execution of an interrupt instruction.
 Ex: divide by 0, overflow interrupts and interrupts due to
INT instructions.
INTERRUPT CYCLE OF 8086
 When an external device interrupts the CPU at NMI or INTR pin,
while executing a program
 The CPU first completes the execution of current instruction and IP
is incremented to point the next instruction.
 The contents of IP and CS are pushed to stack.

 The CPU then only acknowledges the requesting device

immediately on INTA if it is a NMI,TRAP or divide by 0.
 If it is INTR request, the CPU checks the IF flag.

 If IF flag is set then it acknowledges the device otherwise the

interrupt is ignored.
 After acknowledgement the CPU computes the vector address from
the type of interrupt. Then the control is transferred to ISR for
serving the interrupt device.
 The ISR address is available in Interrupt Vector Table.

 At the end of ISR last instruction should be IRET.

INTERRUPT VECTOR TABLE
 VIDEO LECTURE
ON
MICROPROCESSORS
&
MICROCONTROLLERS
BY
K.RAVICHANDRA
ASST.PROF/ECE
VISVODAYA ENGINEERING COLLEGE,
KAVALI,SPSR NELLORE (DT.), ANDHRA PRADESH – 524201
ORGANIZATION
 In 8086 the 1MB physical memory is organized as odd and even banks,
each of 512KB.
 A byte data with even address is transferred on D0-D7, while byte data
with odd address is transferred on D8-D15.
 The processor provides BHE and A0 for the selection of either odd or
even or both the banks.
 The memory map of 8086 system starts at 00000H to FFFFFH.
 VIDEO LECTURE
ON
MICROPROCESSORS
&
MICROCONTROLLERS
BY
K.RAVICHANDRA
ASST.PROF/ECE
VISVODAYA ENGINEERING COLLEGE,
KAVALI,SPSR NELLORE (DT.), ANDHRA PRADESH – 524201
1.9. INTERRUPTS AND INTERRUPT VECTOR TABLE

 Interrupt is an event that causes the µp to stop the normal

program execution.

 The µp services it by executing a subroutine called Interrupt

Service Routine (ISR)

 After executing ISR , the control is transferred back again to

the main program.
Processing of Interrupts :
There are 3 sources of interrupts for 8086
 Hardware Interrupts  signal applied to NMI, INTR pins

 Software Interrupts  by executing INT instructions

 Error in program execution  Divide Error, Overflow

The 8086 uses 256 types of interrupts :

Type 00 to Type 255

These interrupts are classified as

 Dedicated Interrupts (Type 00 to Type 04) : 05

 Reserved Interrupts (Type 05 to Type 31) : 27

 Available Interrupts (Type 32 to Type 255): 224

The dedicated interrupts (Type 00 – Type 04) are

 Type 0 : Divide Error

 Type 1 : Single step execution (TRAP)
 Type 2 : Non-Maskable Interrupt (NMI)
 Type 3 : Break Point
 Type 4 : Overflow
INTERRUPT VECTOR TABLE:

 When the interrupt is enabled, the present IP and CS are pushed on to the stack
and loaded with the address of ISR, which is available in Interrupt vector table.

 Interrupt Vector 
It is a memory block which contains address of ISR
The size of Interrupt vector is 4-bytes (to store CS and IP of ISR)

 Interrupt Vector Table 

It is a memory block which contains interrupt vectors
Since there are 256 types of interrupts, there are 256
interrupt vectors
 Hence, the size of IVT is 4*256 = 1024 bytes
INTERRUPT VECTOR TABLE:
 In 8086 interrupt system, the first 1 KB memory from 00000 H to
003FF H is reserved for storing the starting addresses of ISRs. This
block of memory is called as IVT.

 The Interrupt vector table contains 256 interrupt vectors. The

interrupt vector contains address of ISR,
i.e., IP and CS values of ISR address.

 The interrupt vector address can be calculated by multiplying the

TYPE with 4

 For example, The interrupt vector address for Type-02 interrupt = 02

H*4= 00008 H
PROBLEM :
The contents of memory location 0000:008C are given
below.
0000:008C  12, 34, 56, 78, 90, 92

(a) What is the interrupt vector address for Type-23H

interrupt?

(b) Find the address of ISR corresponding to INT 23H

(c) For which type of interrupt, the interrupt vector

address is 0000:00C8H