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Part-III: DC Biasing

The document discusses the design and operation of a two-stage CMOS operational amplifier. It consists of a differential pair first stage and a common-source second stage. The differential pair provides a voltage gain of 20-60 V/V while the second stage provides an additional gain of 50-80 V/V. Frequency compensation is achieved by introducing a pole at a low frequency using a compensation capacitor in the second stage feedback path. Proper transistor sizing is needed to eliminate any dc offset voltage at the output. As it drives only small on-chip loads, this internal CMOS op amp does not require an output stage.

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Muhammad Nawaz Awan
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41 views67 pages

Part-III: DC Biasing

The document discusses the design and operation of a two-stage CMOS operational amplifier. It consists of a differential pair first stage and a common-source second stage. The differential pair provides a voltage gain of 20-60 V/V while the second stage provides an additional gain of 50-80 V/V. Frequency compensation is achieved by introducing a pole at a low frequency using a compensation capacitor in the second stage feedback path. Proper transistor sizing is needed to eliminate any dc offset voltage at the output. As it drives only small on-chip loads, this internal CMOS op amp does not require an output stage.

Uploaded by

Muhammad Nawaz Awan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Part-III

DC BIASING
General Information
•  Initially the IC 741 was manufactured by “Fairchid Corporation”
• It consists of
24 Transistors
11 Resistors
1 Capacitor
• It requires two power supplies +
• Normally +=+15V and =-15V
• The IC is capable of operating at much lower power supplies such as
Mirror-2

Mirror-1

Widlar current source


: Introduction
: Introduction
  𝟏𝟓+𝟏𝟓 − 𝟎 . 𝟕 − 𝟎 . 𝟕 −𝟑
𝑰 𝑹𝒆𝒇 = =𝟎 . 𝟕𝟑× 𝟏𝟎
𝟑𝟗𝟎𝟎𝟎
Widler
Recall from Chap. 7
 𝑄 13
 𝑄 14
733µA 180µA

Output
Final Stage
Class AB
 ,
733 Mirror
µA Reference
current 550µA
source  , Diff
First
19µA Stage

Active
733µA Load
CE
Widler
Second
 𝑄 10
Stage
 𝑄 17
Second Stage Biasing
𝑄
  23
Biasing Output Stage
 ≅ 𝟎𝐼  𝐵 14

 ≅ 𝟎
𝐼  𝐵 20
Summary : DC currents
Op. Amp. 741

Lec-4
Small Signal Analysis
Small Signal Analysis
Summary of small signal analysis of first stage
Second Stage
Summary of small signal analysis of second stage
Output Stage
Simplified : Output stage
Output Resistance
Part -IV

The Two-Stage CMOS Op Amp


Introduction
The CMOS op-amp are usually designed with a specific application in mind, such as high dc
gain, wide bandwidth, or large output-signal swing.

Many CMOS op amps are utilized within an IC and do not connect to the outside terminals of
the chip. As a result, the loads on their outputs are usually limited to small capacitances of at
most few picofarads.
Internal CMOS op amps therefore do not need to have low output resistances, and their
design rarely incorporates an output stage.
As not connected to outside world there will be no danger of static charge damaging the
gate oxide of the input MOSFETs. Hence, internal CMOS op amps do not need input clamping
diodes for gate protection and thus do not suffer from the leakage effects of such diodes.

In other words, the advantage of near-infinite input resistance of the MOSFET is fully
realized
Visualizing a CMOS operational amplifier

Current source or Active Load

𝛽
Reference
First stage of   Second stage of
amplification
source Amplification

Current source or Active Load


The circuit consists of two
Current source or Active Load gain stages: The first stage
isThis
formed by thebut
simple differential
pair Q –Q circuit
elegant
1 2 togetherhaswith its
current mirror load
become a classic and Q3 –Q4 .
This differential-amplifier
is used in a variety of

𝛽
Refere First stage of   Second stage circuit, provides a voltage
nce of forms
gain thatin
is the design
typically of
in the
source Amplification amplification
VLSIofsystems
range 20 V/V to 60 V/V,
as well as performing
conversion from differential
to single-ended
Lets identifyform while
various
providing
sectionsa in
reasonable
this circuit
Current source or Active Load common-mode rejection
ratio (CMRR).
The differential pair is
biased by current source
Q , which is one of the
5

two output transistors of


the current mirror
formed by Q , Q , and
8 5

Q.
7
The second gain stage
consists of the common-
source transistor Q and its
6

current-source load Q . The


7

second stage typically


provides a gain of 50 V/V to
80 V/V.
In addition 2nd stage takes part in
the process of frequency
compensating the op amp. This
in turn is achieved by
introducing a pole at a relatively
low frequency and arranging for
it to dominate the frequency-
response determination this is
implemented using a
compensation capacitance CC
connected in the negative-
feedback path of the second-
stage amplifying transistor Q6
Unless properly designed, the CMOS op-amp circuit can exhibit a systematic
output dc offset voltage. this dc offset can be eliminated by sizing the transistors
so as to satisfy the following constraint:

Finally, we observe that the CMOS op-amp circuit does not have an output stage. This is
because it is usually required to drive only small on-chip capacitive loads.

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