Design of 2-Stage Differential Amplifiers: Presented By, Bhavana Shekar

DESIGN OF 2-STAGE
DIFFERENTIAL AMPLIFIERS
PRESENTED BY,
BHAVANA SHEKAR
2ND SEM M.TECH
VLSI DESIGN & EMBEDDED SYSTEMS
Dept E&C,PESCE,MANDYA 1
2 stage differential amplifiers
•The circuit consists of two
gain stages: The first stage
is formed by the differential
pair Q1-Q2 together with
its current mirror load Q3-
Q4.
2 stage differential amplifiers
• This differential-amplifier circuit, provides a voltage gain that is
typically in the range of 20 V /V to 60 V/V, as well as performing
conversion from differential to single-ended form while providing
a reasonable common-mode rejection ratio (CMRR).
•The differential pair is biased by current source Q5, which is

one of the two output transistors of the current mirror formed
by Q8, Q5, and Q7. The current mirror is fed by a reference
current Iref.
•The second gain stage consists of the common-source
transistor Q6 and its current source load Q7. The second
stage typically provides a gain of 50 V/V to 80 V/V.
•A compensation capacitance Cc connected in the

negative-feedback path of the second stage amplifying
transistor Q6. As will be seen, Cc is Miller-multiplied by the
gain of the second stage, and the resulting capacitance at
the input of the second stage interacts with the total
resistance there to provide the required dominant pole
Voltage Gain
•The first-stage transconductance Gm1 is equal to the transconductance of

each of Q1 and Q2 ,Since Q1 and Q2 are operated at equal bias currents I/2
and equal overdrive voltages,Vov1=Vov2
.’.Gm1=2(I/2) / Vov1
=I / Vov1
•Resistance R1 represents the output resistance of the first stage, thus
R1=ro2 ‫ ׀׀‬ro4
where ro2=VA2 /(I/2) & ro4=VA4 /(I/2)
•The dc gain of the first stage is thus,
•Observe that the magnitude of A1 is increased by operating the

differential-pair transistors,Q1 and Q2, at a low overdrive voltage,
and by choosing a longer channel length to obtain larger voltages,
VA. Both actions, however, degrade the frequency response &
bandwidth of the amplifier
the second-stage transconductance Gm2 is given by
Resistance R2 represents the output resistance of the second stage,

thus
where
•The voltage gain of the second stage can now be found as,
•Here again we Observe that the magnitude of A2 is increased by

operating the differential-pair transistors,Q6 and Q7, at a low
overdrive voltage, and by choosing a longer channel length to obtain
larger voltages, VA. Both actions, however, degrade the frequency
response & bandwidth of the amplifier
•The overall dc voltage gain can b e found as the product A1 & A2,
•Note that Av is of the order of (gmr0)2. Thus the maximum value of

Av will be in the range of 500 V/V to 5000 V/V.
•Finally, we note that the output resistance of the op amp is equal to
the output resistance of the second stage,
Frequency Response
•Capacitance C1 is the total capacitance between the output node

of the first stage and ground, thus
•Capacitance C2 represents the total capacitance between the

output node of the op amp and ground and includes whatever load
capacitance CL that the amplifier is required to drive, thus
•Usually, CL is larger than the transistor capacitances, with the
result that C2 becomes much larger than C1. Finally, note that Cgd6
should be shown in parallel with Cc but has been ignored because
Cc is usually much larger.
•Equivalent circuit has two poles and a positive real-axis zero

with the following approximate frequencies:
•To achieve the goal of a uniform - 2 0 dB/decade gain rolloff down
to 0 dB, the unity-gain frequency ft,
must be lower than fp2 & fz , thus the design must satisfy the
following two conditions
&
Advantages
 CMOS differential amplifiers are used for various applications
because a number of advantages can be derived from these types
of amplifiers, as compared to single-ended amplifiers.
 Differential amplifiers are used where linear amplification having

a minimum of distortion is desired.
 A fully differential amplifier circuit is a special type of amplifier

that has two inputs and two outputs. This device amplifies input
signals on the two input lines that are out of phase and rejects
input signals that have a common phase such as induced noise.
•The common mode feedback is accomplished by the use of a
common mode feedback circuit that monitors the two
differential amplifier output lines and provides a feedback
signal that adjusts the amplifier's bias current, thereby
rejecting the unwanted common mode signals on the amplifier's
output.
Applications
•The differential
amplifier features a
differential input and an
active load to increase
the gain. The inputs can
either be fed into the gate
of the PMOS or NMOS
differential pair, and the
active load uses its'
complementary (i.e.
NMOS or PMOS) as an
active load to boost the
gain of the differential
amplifier stage.
•The common source amplifier is known to provide high gain at the
tradeoff of stability. A compensation capacitance (CC) is used in a
feedback configuration between the output and the input of the
common source amplifier, otherwise called a Miller Capacitance.
•The biasing stage will be a Wilson Current Mirror configuration

used to provide a constant current source to bias the differential
amplifier and common source amplifier stages
•The overall 2-stage opamp will be designed to maximize gain,
bandwidth, slew rate and voltage swing, and minimize power
dissipation. Phase margin will be set to ensure stability of the
opamp and the settling time will be optimized.
Design specification:
•A phase margin of 64º was chosen to select compensation
capacitance, CC.
•A high bias current – set by the current mirror feeding a bias
current into the differential amplifier stage – will be set to boost
the slew rate.
•Optimal width of NMOS & PMOS transistors maximize both gain and
bandwidth.
•A reference current, IREF, was set up by a NMOS transistor operating
in the triode regionA. A NMOS transistor operating in the triode region
will be used in place of a biasing resistor to improve power consumption
and ease of fabrication.
•Wilson current mirror was used to set up a bias current – both PMOS
and NMOS current mirrors – for the biasing of the differential stage
amplifier, common source amplifier stage and the lead compensation
transistor in the feedback configuration with the compensation
capacitor.
Results
The desired gain of 60dB is obtained
The outputs were found to saturate at 995.66mV (maximum)
and 79.898mV (minimum)
Slew rate was found to be 5.2521V/um
REFERENCES
• P.R. Gray, Analysis and Design of Analog Integrated
Circuits 4th Edition. New York: Wiley, 2001, pp. 223-
231, 425439, 637-652.
• A. Sedra, K. Smith, “Microelectronic Circuits, 5th

Edition,” Oxford University Press Inc., New York,
New York, pp 651-653, 922-943
• D. Johns, K. Martin, “Analog Integrated Circuit

Design”, New York:
Wiley, 1996, pp 221-239
QUESTIONS ?

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DESIGN OF 2-STAGE

•The differential pair is biased by current source Q5, which is

•A compensation capacitance Cc connected in the

•The first-stage transconductance Gm1 is equal to the transconductance of

•Observe that the magnitude of A1 is increased by operating the

Resistance R2 represents the output resistance of the second stage,

•Here again we Observe that the magnitude of A2 is increased by

•Note that Av is of the order of (gmr0)2. Thus the maximum value of

•Capacitance C1 is the total capacitance between the output node

•Capacitance C2 represents the total capacitance between the

•Equivalent circuit has two poles and a positive real-axis zero

 Differential amplifiers are used where linear amplification having

 A fully differential amplifier circuit is a special type of amplifier

•The biasing stage will be a Wilson Current Mirror configuration

• A. Sedra, K. Smith, “Microelectronic Circuits, 5th

• D. Johns, K. Martin, “Analog Integrated Circuit

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