Digital Electronics

Dr.A.N.Jayanthi
Assoc.Prof/ECE
 Memory Unit
• A memory unit is a device to which binary information is
stored and retrieved when needed

• Eg. 1 KB of memory  2^10= 1024

 2^k =1024, Hence k=10
 k address lines=1024 address lines
 Each 1024 locations has 8 bit Data(Byte)
• Example – 1024x16 memory Content
Memory operation
 Write and Read Operations
Write Operation Read Operation
1. Apply the binary address of • 1. Apply the binary address
the desired word to the of the desired word to the
address lines. address lines.
2. Apply the data bits that • 2. Activate the read input.
must be stored in memory to
the data input lines.
3. Activate the write input.
Classification of Memories
 Random Access Memory (RAM)

Can be written to or read from.
 Read/Write memory

Reading from RAM is non-destructive.

Access time to read from any memory
location is the same.
 As compared to serial access memory.

Volatile
 Information is lost when power is removed.
 Random Access Memory (RAM)

Static Random Access Memory (SRAM)
 Based on the Flip-Flop
 Requires a large number of transistors
 Fast

Dynamic Random Access Memory (DRAM)
 Uses a single transistor to store charge
 Requires very few transistors
 Must be periodically refreshed
 Slow(er)
 SRAM- Memory Cell
Internal Construction -SRAM Block Diagram
Construction of 4x4 RAM
 Coincident Decoding
• For 1K-word memory instead of using 10 x1024 decoder, we
use two 5x32 decoder in a two dimensional selection scheme.
• A 10x1024 decoder requires 1024 AND gates with 10 inputs
each, whereas when we use two 5x32 decoder it requires
totally 64 AND gates with five inputs each
• 10 Bit address is split into MSB 5 bits and LSB 5 bits. The MSB
bits are given to X and LSB bits are given to y
Coincident Decoding-Example
 DRAM
• SRAM typically has 6 transistors
• DRAM consists of only one transistor and capacitor
• Capacitor charge will be discharged with respect to time.
Hence it should be periodically recharged.
• DRAMS have 4 times the density and cost is also 4 times less
Address multiplexing for 64K DRAM
Random Access Memory
Read Cycle
Random Access Memory
Write Cycle
 Read Only Memory (ROM)

Can only be read from.

Memory is written (or “programmed”) once

Reading from ROM is non-destructive.

Access time to read from any memory location is
the same.
 As compared to serial access memory.

Non-Volatile
 Information is retained even after power is
removed.
 Read Only Memory

• The inputs provide the address for memory, and the outputs
give the data bits of the stored word that is selected by the
address.
• The number of words in a ROM is determined from the fact
that k address input lines are needed to specify 2k words.
• Note that ROM does not have data inputs, because it does not
have a write operation.
 Eg:32x 8 ROM
• Here 2^k = 32 and n=8, Therefore 32 address locations and 8
output lines. The 32 addresses are generated by a 5 x32
decoder.
Programming ROM
 ROM Example
• Design a combinational circuit using a ROM. The circuit
accepts a three‐bit number and outputs a binary number
equal to the square of the input number.
Types of Read Only Memory (ROM)

Programmable Read Only Memory (PROM)
 Can be “programmed”

Erasable PROM (EPROM)
 Can be “programmed” and erased

Electrically Erasable PROM (EEPROM)
 Can be erased using an electrical signal

UV Erasable PROM (UVEPROM)
 Can be erased using Ultraviolet light
 ERROR DETECTION
• The reliability of a memory unit is improved by using error‐detecting and error‐
correcting codes.
• Most common error detection scheme is the parity bit.
• The parity of the word is checked after reading it from memory. The data word
is accepted if the parity of the bits read out is correct. If the parity checked
results in an inversion, an error is detected, but it cannot be corrected.
 ERROR CORRECTION
• An error‐correcting code generates multiple parity check bits that are stored
with the data word in memory.
• Each check bit is a parity over a group of bits in the data word.

• When the word is read back from memory, the associated parity bits are also
read from memory and compared with a new set of check bits generated
from the data that have been read.
• If the check bits are correct, no error has occurred.

• If the check bits do not match the stored parity, they generate a unique
pattern, called a syndrome, that can be used to identify the bit that is in error.
 Hamming Code
• k parity bits are added to an n ‐bit data word, forming a new
word of n + k bits.
• The bit positions are numbered in sequence from 1 to n + k.
• Those positions numbered as a power of 2 are reserved for
the parity bits. The remaining bits are the data bits. The code
can be used with words of any length.
• Consider, for example, the 8‐bit data word 11000100. We
include 4 parity bits with the 8‐bit word and arrange the 12
bits as follows:
• Bit position: 1 2 3 4 5 6 7 8 9 10 11 12
P1 P2 1 P4 1 0 0 P8 0 1 0 0
The Parity bits are
P1 = XOR of bits (3, 5, 7, 9, 11) = 0
P2 = XOR of bits (3, 5, 7, 10, 11) = 0
P4 = XOR of bits (5, 6, 7, 12) = 1
P8 = XOR of bits (9, 10, 11, 12) = 1
• The 8‐bit data word is stored in memory together with the 4 parity bits as
a 12‐bit composite word.

Bit Position
0 0 1 1 1 0 0 1 0 1 0 0
• 1 122 bits2 are4read5 from
When the 6 memory,
7 8 they
6 are
10 checked
11 12 again for
errors. The parity is checked over the same combination of bits, including
the parity bit.
• The Check bits are
C1 = XOR of bits (1, 3, 5, 7, 9, 11) = 0
C2 = XOR of bits (2, 3, 6, 7, 10, 11) = 0
C4 = XOR of bits (4, 5, 6, 7, 12) = 0
C8 = XOR of bits (8, 9, 10, 11, 12) = 0
• A 0 check bit designates even parity over the checked bits and a 1
designates odd parity.
• Since the bits were stored with even parity, the result, C = C8C4C2C1 =
0000, indicates that no error has occurred.
• if C ≠ 0, then the 4‐bit binary number formed by the check bits gives the
position of the erroneous bit.
• Bit position:

1 2 3 4 5 6 7 8 9 10 11 12
0 0 1 1 1 0 0 1 0 1 0 0 No error
1 0 1 1 1 0 0 1 0 1 0 0 Error in
bit 1
0 0 1 1 0 0 0 1 0 1 0 1 Error in
bit 5
 C8 C4 C2 C1
• For no error: 0 0 0 0
• With error in bit 1: 0 0 0 1
• With error in bit 5: 0 1 0 1
• When the binary number C is not equal to 0000, it gives the position of
the bit in error.
• The error can be corrected by complementing the corresponding bit.
• The syndrome value C consists of k bits and has a range of 2k values
between 0 and 2k - 1.
• One of these values, usually zero, is used to indicate that no error was
detected, leaving 2k – 1 values to indicate which of the n + k bits was in
error.
• The range of k must be equal to or greater than n + k, giving the
relationship
2k – 1-K ≥n
Range of Data Bits for k Check Bits
Number of Check Bits, k Range of Data Bits, n
3 2–4
4 5–11
5 12–26
6 27–57
7 58–120

Single‐Error Correction, Double‐Error Detection

• The Hamming code can detect and correct only a single error. By adding another
parity bit to the coded word, the Hamming code can be used to correct a single
error and detect double errors.
• If this additional parity bit is included, then the previous 12‐bit coded word
becomes 001110010100P13. This produces the 13‐bit word 0011100101001 (even
parity).
• P = 0, the parity is correct (even parity)
• P = 1, then the parity is incorrect (odd parity)
• If C = 0 and P = 0, no error occurred.

• If C ≠ 0 and P = 1, a single error occurred that can be corrected.

• If C ≠ 0 and P = 0, a double error occurred that is detected, but that cannot
be corrected.
• If C = 0 and P = 1, an error occurred in the P13 bit.

• This scheme may detect more than two errors, but is not guaranteed to
detect all such errors.
• Integrated circuits use a modified Hamming code to generate and check
parity bits for single‐error correction and double‐error detection.
 Combinational PLDs
• The PROM is a combinational programmable logic device
(PLD)—an integrated circuit with programmable gates divided
into an AND array and an OR array to provide an AND–OR
sum‐of‐product implementation.
• Three types
a) PROM (Programmable read only memory)
b) PAL (Programmable Array logic)
c) PLA (Programmable Logic Array)
Types of Combinational PLDs
1.Programmable Read Only Memory(PROM)

2.Programmable Array Logic(PAL)

3.Programmbale Logic Array (PLA)

 Programmable Logic Array(PLA)
• The PLA is similar in concept to the PROM, except that the
PLA does not provide full decoding of the variables and does
not generate all the minterms.
• The decoder is replaced by an array of AND gates that can be
programmed to generate any product term of the input
variables.
• The product terms are then connected to OR gates to provide
the sum of products for the required Boolean functions.
Boolean Function Implementation in PLA
• Eg. Implement the following fn in PLA
Boolean Function Implementation in PLA
(Contd.)
• PLA Programming Table
 PLA Example
• Implement the following two Boolean functions with a PLA:
 Programmable Array Logic(PAL)
• The PAL is a programmable logic device with a fixed OR array
and a programmable AND array. Because only the AND gates
are programmable, the PAL is easier to program than, but is
not as flexible as, the PLA.
 PAL Implementation Example
• Implement the function

• After K-map simplification

w = ABC’+A’B’CD’
x = A+BCD
y = A’B+CD+B’D’
z = ABC’+A’B’CD’+AC’D’+A’B’C’D
• z can be written in terms of w as
z= w+ AC’D’+A’B’C’D
 PAL Implementation Example(Contd.)
w = ABC’+A’B’CD’
x = A+BCD
y = A’B+CD+B’D’
z = w+ AC’D’+A’B’C’D
 Sequential Programmable Devices
• Digital systems are designed with flip‐flops and gates. Since
the combinational PLD consists of only gates, it is necessary to
include external flip‐flops when they are used in the design.
• Sequential programmable devices include both gates and flip‐
flops. In this way, the device can be programmed to perform a
variety of sequential‐circuit functions.
• Three types
1. Sequential (or simple) programmable logic device (SPLD)
2. Complex programmable logic device (CPLD)
3. Field‐programmable gate array (FPGA)
1. Sequential (or simple) programmable logic device (SPLD)

• The SPLD includes flip‐flops, in addition to the AND–OR array

• A PAL or PLA is modified by including a number of flip‐flops
connected to form a register.
• The circuit outputs can be taken from the OR gates or from the
outputs of the flip‐flops.
• THANK YOU