CMP2008 L1

Lecture 1: CMP 2008 Introduction
• Today’s topics:
 Why computer organization is important

 Logistics
 Modern trends
 Performance trends
Thanks to Rajeev Balasubramonian 1

from University of Utah
Why Computer Organization
2
Image credits: uber, extremetech, anandtech
https://meltdownattack.com/
3
Image credits: gizmodo
• Embarrassing if you are a BS in CMP/EE and can’t

make sense of the following terms: DRAM, pipelining,
cache hierarchies, I/O, virtual memory, …
• Embarrassing if you are a BS in CMP/EE and can’t decide

which processor to buy: 4.4 GHz Intel Core i9 or
4.7 GHz AMD Ryzen 9 (reason about performance/power)
• Obvious first step for chip designers, compiler/OS writers
• Will knowledge of the hardware help you write better

and more secure programs?
4
Must a Programmer Care About Hardware?
• Must know how to reason about program performance

and energy and security
• Memory management: if we understand how/where data

is placed, we can help ensure that relevant data is nearby
• Thread management: if we understand how threads

interact, we can write smarter multi-threaded programs
 Why do we care about multi-threaded programs?
5
Example
200x speedup for matrix vector multiplication
• Data level parallelism: 3.8x

• Loop unrolling and out-of-order execution: 2.3x
• Cache blocking: 2.5x
• Thread level parallelism: 14x
Further, can use accelerators to get an additional 100x.
6
Key Topics
• Moore’s Law, power wall

• Use of abstractions
• Assembly language
• Computer arithmetic
• Pipelining
• Using predictions
• Memory hierarchies
• Accelerators
• Reliability and Security
7
Logistics
• See class web-page

– Itslearning, MS Teams
• Office hours: TBA
• Most communication on itslearning; email me directly to set

up office hours
• Textbook: Computer Organization – HW/SW Interface,

Patterson and Hennessy, 5th edition
8
Course Organization
• 20% midterm, 40% final, 40% quizzes
• ~10 quizzes – all quizzes are done during class hours

on itslearning
• Exams are on paper and Face to Face.
• Slides will be uploaded USUALLY one day before the class
9
Microprocessor Performance
Source: H&P Textbook

50% improvement every year!!
What contributes to this improvement?
10
Microprocessor Performance
Source: karlrupp.net
11
Power Consumption Trends
12
Source: H&P Textbook
Summary
• Increasing frequency led to power wall in early 2000s
• Frequency becomes constant (almost) since then
• End of voltage (Dennard) scaling in early 2010s
13
Important Trends
• Running out of ideas to improve single thread performance
• Power wall makes it harder to add complex features
• Power wall makes it harder to increase frequency
• Additional performance provided by: more cores, occasional

spikes in frequency, accelerators
14
Important Trends
• Historical contributions to performance:

1. Better processes (faster devices) ~20%
2. Better circuits/pipelines ~15%
3. Better organization/architecture ~15%
In the future, bullet-2 will help little and bullet-1 will

eventually disappear!
Pentium P-Pro P-II P-III P-4 Itanium Montecito

Year 1993 95 97 99 2000 2002 2005
Transistors 3.1M 5.5M 7.5M 9.5M 42M 300M 1720M
Clock Speed 60M 200M 300M 500M 1500M 800M 1800M
Moore’s Law in action At this point, adding transistors

to a core yields little benefit 15
What Does This Mean to a Programmer?
• Today, one can expect only a 20% annual improvement;

the improvement is even lower if the program is not
multi-threaded
 A program needs many threads
 The threads need efficient synchronization and

communication
 Data placement in the memory hierarchy is important
 Accelerators should be used when possible
16
Challenges for Hardware Designers
• Find efficient ways to
 improve single-thread performance and energy
 improve data sharing
 boost programmer productivity
 manage the memory system
 build accelerators for important kernels
 provide security
17
The HW/SW Interface
Application software a[i] = b[i] + c;
Compiler
lw $15, 0($2)
add $16, $15, $14
Systems software add $17, $15, $13
(OS, compiler) lw $18, 0($12)
lw $19, 0($17)
add $20, $18, $19
sw $20, 0($16)
Assembler
Hardware 000000101100000
110100000100010
18
…
Computer Components
• Input/output devices
• Secondary storage: non-volatile, slower, cheaper (HDD/SSD)
• Primary storage: volatile, faster, costlier (RAM)
• CPU/processor (datapath and control)
19
Next Class
• Topics: Performance, MIPS instruction set

architecture (Chapter 2)
• Visit the class web-page on itslearning for more info
20

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Lecture 1: CMP 2008 Introduction

 Why computer organization is important

Thanks to Rajeev Balasubramonian 1

• Embarrassing if you are a BS in CMP/EE and can’t

• Embarrassing if you are a BS in CMP/EE and can’t decide

• Obvious first step for chip designers, compiler/OS writers

• Will knowledge of the hardware help you write better

• Must know how to reason about program performance

• Memory management: if we understand how/where data

• Thread management: if we understand how threads

 Why do we care about multi-threaded programs?

200x speedup for matrix vector multiplication

• Data level parallelism: 3.8x

Further, can use accelerators to get an additional 100x.

• Moore’s Law, power wall

• See class web-page

• Office hours: TBA

• Most communication on itslearning; email me directly to set

• Textbook: Computer Organization – HW/SW Interface,

• 20% midterm, 40% final, 40% quizzes

• ~10 quizzes – all quizzes are done during class hours

• Exams are on paper and Face to Face.

• Slides will be uploaded USUALLY one day before the class

Source: H&P Textbook

• Increasing frequency led to power wall in early 2000s

• Frequency becomes constant (almost) since then

• End of voltage (Dennard) scaling in early 2010s

• Running out of ideas to improve single thread performance

• Power wall makes it harder to add complex features

• Power wall makes it harder to increase frequency

• Additional performance provided by: more cores, occasional

• Historical contributions to performance:

In the future, bullet-2 will help little and bullet-1 will

Pentium P-Pro P-II P-III P-4 Itanium Montecito

Moore’s Law in action At this point, adding transistors

• Today, one can expect only a 20% annual improvement;

 A program needs many threads

 The threads need efficient synchronization and

 Data placement in the memory hierarchy is important

 Accelerators should be used when possible

• Find efficient ways to

 improve single-thread performance and energy

 improve data sharing

 boost programmer productivity

 manage the memory system

 build accelerators for important kernels

Application software a[i] = b[i] + c;

• Secondary storage: non-volatile, slower, cheaper (HDD/SSD)

• Primary storage: volatile, faster, costlier (RAM)

• CPU/processor (datapath and control)

• Topics: Performance, MIPS instruction set

• Visit the class web-page on itslearning for more info

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