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    Lecture 5-6 Computer Organization and Architecture

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    The document discusses different instruction set architectures including accumulator architecture, general register architecture, register (load/store) architecture, and stack architecture. It provides examples of how each architecture handles an arithmetic expression of A*B - (X+Y*Z). Accumulator architecture uses a single accumulator register, general register architecture uses multiple general purpose registers, register (load/store) architecture separates instructions into load/store and arithmetic instructions, and stack architecture uses a stack and push/pop instructions.

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    Lecture 5-6 Computer Organization and Architecture

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    shashank kumar
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    The document discusses different instruction set architectures including accumulator architecture, general register architecture, register (load/store) architecture, and stack architecture. It provides examples of how each architecture handles an arithmetic expression of A*B - (X+Y*Z). Accumulator architecture uses a single accumulator register, general register architecture uses multiple general purpose registers, register (load/store) architecture separates instructions into load/store and arithmetic instructions, and stack architecture uses a stack and push/pop instructions.

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    The document discusses different instruction set architectures including accumulator architecture, general register architecture, register (load/store) architecture, and stack architecture. It provides examples of how each architecture handles an arithmetic expression of A*B - (X+Y*Z). Accumulator architecture uses a single accumulator register, general register architecture uses multiple general purpose registers, register (load/store) architecture separates instructions into load/store and arithmetic instructions, and stack architecture uses a stack and push/pop instructions.

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    © All Rights Reserved
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    Download as pptx, pdf, or txt
    35 views16 pages

    Lecture 5-6 Computer Organization and Architecture

    Uploaded by

    shashank kumar
    The document discusses different instruction set architectures including accumulator architecture, general register architecture, register (load/store) architecture, and stack architecture. It provides examples of how each architecture handles an arithmetic expression of A*B - (X+Y*Z). Accumulator architecture uses a single accumulator register, general register architecture uses multiple general purpose registers, register (load/store) architecture separates instructions into load/store and arithmetic instructions, and stack architecture uses a stack and push/pop instructions.

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    Computer Organization and Architecture

    CSEN 2202
    Lecture 5 – 6
    22/01/2020

    Dr. Debranjan Sarkar


    Instruction Format
    • Operation Code
    • Example: Add, Sub, Complement etc.
    • Address field Operation Code Mode Address
    • Memory location
    • Processor Register
    • Operand value
    • Mode
    • Specifies the addressing mode to get the operand
    • Effective address of the operand
    • In some computer, no separate mode field and the addressing mode is specified in
    the instruction (opcode) itself
    • Example: ADD R1, R0
    Instruction Format (contd.)
    • In certain situations, special fields are used
    • Number of shifts in a SHIFT type instruction
    • Label field in a BRANCH type instruction
    • Memory or Registers store the operand values on which the
    instructions are executed
    • Memory addresses are used to specify operands stored in memory
    • A register address (k-bit) specifies one out of 2k registers in the CPU
    • A CPU with 32 registers has a register address field of 5 bits
    Various types of Instruction Set Architecture
    • Accumulator architecture
    • General Register based architecture
    • Register-Memory architecture
    • Memory-Memory architecture
    • Register (Load/ store) architecture
    • Stack architecture
    Accumulator architecture
    • A single register, called the Accumulator is used to
    • process all the instructions
    • store the operand before the operation
    • store intermediate results
    • store the result after the operation
    • Instruction format has only one operand (in register or memory)
    • Accumulator almost always implicitly used
    • This type of CPU is known as one-address machine
    • Example: MULT X [ X = address of the operand]
    • (AC)  (AC) * mem[X]
    Accumulator architecture
    • Example: A*B - (X+Y*Z)
    load Z
    mul Y
    add X Accumulator
    store C
    load A
    mul B
    sub C
    • Advantages
    –Very low hardware requirements
    –Easy to design and understand
    –Short instruction and less memory space
    –Instruction cycle is faster
    • Disadvantages
    –Accumulator becomes the bottleneck
    –Little ability for parallelism or pipelining
    –Program size increases as many short instructions are required Memory
    –High memory traffic and more execution time
    General Register Architecture
    • Multiple general purpose registers (GPRs)
    • Two or Three address fields in the Instruction Format
    • Each address field may specify a general register or a memory word
    • One operand Register and other operand Memory → Register-Memory architecture
    • All operands memory → Memory-Memory architecture
    • Example (3-address)
    • SUB R1, A, B which means (R1)  mem[A] – mem[B]
    • MULT R1, R2, R3 which means (R1)  (R2) * (R3)
    • Example (2-address)
    • MULT R1, R2 which means (R1)  (R1) * (R2)
    • ADD R1, A which means (R1)  (R1) + mem[A]
    General Register Architecture
    Registers
    • Example: A*B - (X+Y*Z)
    3 operands 2 operands
    mul D, A, B mov D, A
    mul E, Y, Z mul D, B
    add E, X, E mov E, Y
    sub E, D, E mul E, Z
    add E, X
    sub E, D
    • Advantages
    – Many registers are used, so program size is less
    – Requires fewer instructions (especially if 3 operands)
    – Less memory required to store the program
    – Easy to write compilers for (especially if 3 operands)
    • Disadvantages Memory
    – Very high memory traffic (especially if 3 operands)
    – Variable number of clocks per instruction
    – With two operands, more data movements are required
    Register (Load/ Store) Architecture
    • Divides instructions into two categories:
    • Memory access (Load and Store between memory and registers)
    • Arithmetic / Logic operations (which only occur between registers)
    • For example, both operands and destination for an ADD operation must be in
    registers
    • Only load and store instructions access the memory (memory indirect addressing
    mode)
    • All other instructions use registers as operands
    • Primary motivation is speedup –registers are faster
    • RISC instruction set architectures such as PowerPC, SPARC, RISC-V, ARM and
    MIPS are load–store architectures
    Load/ Store Architecture
    • Example: C = A*B - (X+Y*Z) Registers
    load R1, &A
    load R2, &B
    load R3, &X
    load R4, &Y
    load R5, &Z
    mul R7, R4, R5 /* Y*Z */
    add R8, R7, R3 /* X + Y*Z */
    mul R9, R1, R2 /* A*B*/
    sub R10, R9, R8 /* A*B – (X+Y*Z) */
    store R10, &C
    • Advantages
    – Simple, fixed length instruction encodings
    – Instructions take similar number of cycles
    – Relatively easy to pipeline and make superscalar
    • Disadvantages
    – Higher instruction count
    – Not all instructions need three operands
    – Dependent on good compiler
    Stack architecture
    • What is stack?
    • A portion of memory, used to store operands in successive locations
    • A data structure in which a list of data is accessed with LIFO access
    method
    • Only two operations: PUSH and POP
    • PUSH inserts one operand at the top of the stack
    • POP takes out one operand from the top of the stack
    • Operands are pushed or popped from one end only
    • Stack Pointer (SP) holds the address of the top of the stack
    Example of PUSH and POP
    • PUSH <memory address>

    • SP  SP – 1
    • Top of stack  < memory address>

    • POP <memory address>

    • < memory address>  Top of stack


    • SP  SP + 1
    Stack architecture
    • No operand
    • This type of CPU is known as zero-address machine
    • The two operands are on the top of the stack
    • Result will be on the top of stack Stack

    • Example: A*B - (X+Y*Z)


    push A
    push B
    mul
    push X
    push Y
    push Z
    mul
    add
    sub
    Stack architecture
    • Advantages
    • No address field -> length of the instruction is short
    • Low hardware requirements
    • Efficient computation of complex arithmetic expression
    • Execution of instruction is fast, because operands are stored in consecutive memory locations
    • Easy to write a simpler compiler for stack architectures

    • Disadvantages
    • Stack becomes the bottleneck
    • Little ability for parallelism or pipelining
    • Difficult to write an optimizing compiler for stack architectures
    Arithmetic Expression Evaluation
    • Infix notation
    • Example: (A + B) * (C + D)
    • Polish Notation (or Prefix notation)
    • Example: +AB (in Prefix) means A + B (in Infix)
    • No parenthesis required
    • Reverse Polish Notation (or Postfix notation)
    • Example: AB+ (in Postfix) means A + B (in Infix)
    • No parenthesis required
    • Stack oriented computers are better suited to postfix notation than Infix
    notation
    • Example: (A +B) * [C/(D-E) + F] is equivalent to AB+CDE-/F+*
    • Explain with a Numerical example (40, 60, 100, 50, 30, 35) → 4000
    Thank you

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