EE8551

MICROPROCESSORS AND
MICROCONTROLLERS
 SYLLABUS
UNIT I
8085 PROCESSOR 

Hardware Architecture, pinouts – Functional Building Blocks of

Processor – Memory organization – I/O ports and data transfer concepts–
Timing Diagram Interrupts.

UNIT II
PROGRAMMING OF 8085 PROCESSOR

Instruction - format and addressing modes – Assembly language format –

Data transfer, data manipulation & control instructions – Programming:
Loop structure with counting & Indexing – Look up ability – Subroutine
instructions – stack.
 UNIT III
8051 MICRO CONTROLLER
 
Hardware Architecture, pinouts – Functional Building Blocks of Processor –
Memory organization – I/O ports and data transfer concepts– Timing
Diagram – Interrupts- Data Transfer, Manipulation, Control Algorithms&
I/O instructions, Comparison to Programming concepts with 8085.
UNIT IV
PERIPHERAL INTERFACING 

Study on need, Architecture, configuration and interfacing, with ICs: 8255,

8259, 8254, 8279, – A/D and D/A converters & Interfacing with 8085 &
8051.

UNIT V
MICRO CONTROLLER PROGRAMMING & APPLICATIONS

Simple programming exercises- key board and display interface –Control of

servo motor – Stepper motor control – Application to automation System
Microprocessor
 An integrated circuit that contains all the functions
of a central processing unit of a computer.
 It is a Multipurpose, Programmable logic device
 Performs fetching, decoding and execution.
Applications/Uses of microprocessor-based system.

Mobiles, Calculators, Accounting system, Games

machine
Military applications
Communication systems.
For traffic control and industrial tool control.
For speed control of machines.
Bit, Nibble, Byte and Word
A digit of the binary number or code is called bit.
The 4 bit binary number is called nibble.
The 8-bit (8-digit) binary number or code is
called byte and
16-bit binary number or code is called word.
Evolution of Processors
Advanced Processors
Intel Core i7
Intel Core i3
Core i5
Core i7
Core i9
Programming languages
Machine language
Assembly language
High level language
Features of 8085
1) 8 bit microprocessor. I.e. it can accept or provide 8 bit
data simultaneously.
2) Single chip, NMOS device implemented with 6200
transistors.
3) Requires a single +5V DC power supply.
4) Provides on chip clock generator, therefore there is no
need of external clock generator, but it requires
external tuned circuit like LC, RC or crystal.
5) 8085 microprocessor requires two phase, 50% duty
cycle, TTL clock.
6) The max clock frequency of 8085 microprocessor is
3MHz where as minimum clock frequency is 500 KHz.
7)  8085 provides 74 instructions
8) The data bus is multiplexed with the address bus.
9) Provides 16 address lines, therefore it can access
2^16 = 64K bytes of memory.
10)It generates 8 bit I/O address, it can access 2^8 =
256 input ports and 256 output ports.
11) It performs arithmetic and logical operations.
12)8085 microprocessor has five hardware
interrupts: TRAP, RST 7.5, RST 6.5, RST 5.5,
INTR
13)8085 microprocessor provides two serial I/O
lines which are SOD and SID.
Architecture of 8085
1. Arithmetic and Logic Unit
ALU performs arithmetic operations like +, -, *, /
and to perform logical operations like AND, OR,
NOT operations on 8-bit data.
2) Register structure of 8085
General Purpose Registers - B, C, D, E, H and L.
Temporary Registers - a) Temporary data register
b) W and Z registers
Special Purpose Registers - a) Accumulator b)
Flag registers c) Instruction register
Sixteen Bit Registers - a) Program Counter (PC)
b) Stack Pointer (SP)
i) General Purpose Registers
 The six special types of registers (or) general purpose
registers are B, C, D, E, H and L. Each register can hold 8-bit
data.
 They can work in pairs such as B-C, D-E and H-L to store 16-
bit data.
 The H-L pair (store 16-bit address) works as a memory pointer
which holds the address of a particular memory location.
 
ii) Special purpose register
 a) Accumulator
 It is 8-bit register which can hold 8-bit data.
 The accumulator is connected to Internal Data bus and ALU
(arithmetic and logic unit).
 used to send or receive data from the Internal Data bus.
Flags (or) Flag register of 8085
A flag is actually a latch.
It alerts the processor that some event has
taken place.
S-Sign flag:
 After an ALU operation, if D7 is 1(set), the number
will be viewed as negative number.
 if D7 is 0, the number will be considered as positive
number.
Z-Zero flag:
 The zero flag sets -result of operation in ALU is
zero
 Flag resets if result is non zero.
AC-Auxiliary Carry flag:
 This flag is set if there is an overflow out of bit
 This flag is used for BCD operations and it is not
available for the programmer.
P-Parity flag:
if the result has an even number of ones,
i.e. even parity, the flag is set.
If the parity is odd, flag is reset.
CY-Carry flag:
This flag is set if there is an overflow out of
bit 7.
The carry flag also serves as a borrow flag
for subtraction.
c) Instruction register: The CPU stores this
opcode in a register called the instruction register.
iii) Temporary Register:
Temporary Data Register:
Acts as a temporary memory during the
arithmetic and logical operations.
Inaccessible to programmers.
W and Z Registers:
hold 8-bit data during execution.
not available for programmer, since 8085 uses
them internally.
Sixteen Bit Registers
a) Program counter
 A program counter stores the address of the next
instruction to be executed.
b) Stack pointer
 Used as a memory pointer.
 A stack is nothing but the portion of RAM (Random
access memory).
 Stack pointer maintains the address of the last byte that
is entered into stack.
 Each time when the data is loaded into stack, Stack
pointer gets decremented. it is incremented when data is
retrieved from stack.
 Timing and Control Unit
Oscillator generates two-phase clock
signals which aids in synchronizing the
registers and flow of data through various
registers and other units.
Control unit sends control signals needed
for internal and external control of data and
other units.
Interrupt Control
Whenever the interrupt signal is enabled or requested
the microprocessor shifts the control from main
program to process the incoming request and after the
completion of request, the control goes back to the
main program.
Interrupt signals present in 8085 are:
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR
Serial I/O control
The input and output of serial data can be
carried out using 2 instructions in 8085.
◦ SID-Serial Input Data
◦ SOD-Serial Output Data
Instructions are used to perform serial-
parallel conversion
◦ SIM
◦ RIM
6) Address buffer and Address-Data buffer
 The contents of the stack pointer and program
counter are loaded into the address buffer and
address-data buffer.
 The address data buffer can both send and receive
data from internal data bus.

7) Address Bus/Data Bus:

 The address/data bus is time multiplexed.
 For few microseconds, the 8 least significant bits of
address are generated, while for next few seconds the
same pin generates the data. This is called Time
multiplexing.
Pin configuration (Pin diagram) (signals) of 8085
The 8085 microprocessor is available on a
40-pin dual in line package (DIP).
It consists of
1. Power supply and frequency signals.
2. Data bus and address bus.
3. Control bus.
4. Interrupt signals.
5. Serial I/O signals.
6. DMA signals.
7. Reset signals.
a) Power Supply and Frequency Signals
VCC: It requires a single +5 V power supply.
VSS: Ground reference.
X1 and x2: A tuned circuit like LC, RC or crystal is connected at these TWO
pins.
iv) CLK OUT: This signal is used as a system clock for other devices. Its
frequency is half the oscillator frequency.

b) Data Bus and Address Bus

A )ADOto AD7:The 8 bit data bus (Do–D7) is multiplexed with the lower half
(A0–A7) of the16 bit address bus.
B) A8 to A15: The upper half of the 16 bit address appears on the address lines
A8to A15.
c ) Control and Status Signals
Control Pins – RD, WR These are active low Read & Write pins
Status Pins – ALE, IO/M(active low), S1, S0
ALE (Address Latch Enable)-Used to de-multiplex AD7-AD0
IO/M – Used to select I/O or Memory operation
S1,S0 – Denote the status of data on data bus
d) Interrupt Signals
 The 8085 has five hardware interrupt signals. TRAP, RST 7.5, RST 6.5,
RST 5.5, and INTR.
 The microprocessor recognizes interrupt requests on these lines at the
end of the current instruction execution.
 The INTA(Interrupt Acknowledge) signal is used to indicate that the
processor has acknowledged an INTR interrupt.
 
e) Serial I/O Signals
 A ) SID (Serial Input Data): This input signal is used to accept serial
data bit by bit from the external device.
 B) SOD (Serial O/P Data):This is an output signal which enables the
transmission of serial data bit by bit to the external device.

f) DMA Signal
 HOLD: This signal indicates that another master is requesting for the
use of address bus, data bus and control bus.
 HLDA: This active high signal is used to acknowledge HOLD request.
g) Reset Signals
 A low on this pin
 Internal sets the program counter to zero (0000H).
 Resets the interrupt enable and HLDA flip-flops.
 Tri-states the data bus, address bus and control bus
(Note: Only during RESET is active).
 Affects the contents of processor's registers
randomly.
 
RESET OUT: This active high signal indicates that
processor is being reset. This signal is synchronized
to the processor clock and it can be used to reset
other devices connected in the system.
 Memory interfacing in 8085
microprocessor
The memory interfacing requires to:
 Select the chip
 Identify the register
 Enable the appropriate buffer.
 Microprocessor system includes memory devices and I/O
devices.
 It is important to note that microprocessor can communicate
(read/write) with only one device at a time, since the data,
address and control buses are common for all the devices.
 In order to communicate with memory or I/O devices, it is
necessary to decode the address from the microprocessor.
 Due to this each device (memory or I/O) can be accessed
independently.
 The different types of Address decoding
techniques are:

Address Decoding Techniques:

Absolute decoding/Full Decoding
Linear decoding/Partial Decoding
Absolute decoding
In absolute decoding technique, all the
higher address lines are decoded to select
the memory chip, and the memory chip is
selected only for the specified logic levels
on this high-order address lines; no other
logic levels can select the chip.
Linear decoding
In small systems, hardware for the
decoding logic can be eliminated by using
individual high-order address lines to select
memory chips. This is referred to as linear
decoding.
A15 address line is directly connected to the chip
select signal of EPROM and after inversion it is
connected to the chip select signal of the RAM.
Therefore, when the status of A15 line is 'zero',
EPROM gets selected and when the status of A15
line is 'one' RAM gets selected.
The status of the other address lines is not
considered, since those address lines are not used
for generation of chip select signals.
I/O Interfacing Techniques
The I/O interfacing techniques are:
I/O Mapped I/O interface
Memory Mapped I/O interface
I/O Mapped I/O Interface

 The I/O devices are identified by port numbers, and

memory locations are identified by addresses.
 The memory read/write operations and I/O read/write
operations are performed by different software
instructions.
 Whether the read/write operations are being performed on
memory or I/O, or in other words whether the information
on address and data lines is meant for a memory location
or an I/O device—this identification is done by separate
signals.
 Thus, when read from an I/O device instruction is
executed, the I/O signal is ON and the address on the
address bus is decoded as the port number and an I/O
device is selected.
 In case of read/write from memory, the MEMORY signal
is ON and a particular location of memory is selected.
 Because of separate memory and I/O signals, there is no
confusion between device address (i.e. port number) and
memory address. This is called I/O mapped I/O interface
since I/O devices are treated separately from memory.
Memory Mapped I/O Interface
 If this memory location address is the same as that of a port
number of an I/O device, an I/O device will also get selected
together with the memory read operation being performed.
Thus, there will be confusion between memory location and
I/O device having the same address and port number.

 To read from device 1 (Port no. 00) memory location 00 will

also get selected. However, if some memory locations is
satisfied for the sake of I/O devices, this problem would not
arise. It means that the I/O addresses (port numbers) and the
memory addresses will not be the same. If the memory starts
from address 04 onwards, then there would not be any
problem.
 
 The memory read/write instructions are quite versatile and powerful in
general. If a microprocessor has more than one register apart from ACC (the
8085 has six registers other than ACC), then the memory operations can be
performed using any of these registers.
 
 These instructions automatically become valid for I/O devices if connected
in this fashion. The I/O read/write instructions in I/O-mapped I/O, normally
require the transfer from an I/O port to accumulator. The same data is then
subsequently transferred to the other register, thus wasting one instruction.
 
 The memory read/write instructions employ various powerful addressing
modes like indexed, indirect, base register addressing, etc. which is not true
in the case of I/O read/write instructions.

 Thus, more compact and more efficient handling of I/O devices can be
achieved if they are interfaced to microprocessor in this way. Since an I/O
device is treated as memory location (identified by memory address), this
interface is called memory mapped I/O.
Data Transfer Schemes of 8085
Parallel Data Transfer
Programmed I/0
 In programmed I/O, the data transfer is controlled by the user
program being executed.
 Depending on the type of the device, data transfer may be
synchronous or asynchronous. Synchronous data transfer is used
when the I/0 device matches in speed with the microprocessor.
 The microprocessor issues the read/write instruction addressing the
device whenever data transfer is required. The actual data transfer
takes place in one clock cycle.
 When the I/O device speed and the microprocessor speed do not
match, i.e. when the I/O device is slower than the microprocessor,
asynchronous data transfer is used. In this mode of data transfer, the
microprocessor checks the status of the device.
 If the device is not ready, the microprocessor continuously checks the
status of the device till it becomes ready. The data transfer instruction
is then issued by the microprocessor
Interrupt I/O
The data transfer scheme is quite inefficient, since
the microprocessor is kept busy for the slower I/O
device.
The remedy to this problem is to allow the
microprocessor to do its job when the device is
getting ready and when the device is ready, the
microprocessor can transfer the data. This can be
achieved through interrupt.
 Followingis the operation sequence for interrupt operation.
 Normal program execution by microprocessor.
◦ The microprocessor initiates the device through a code/signal (e.g. start
convert signal to initiate ADC conversion).
◦ The device when ready to send the data sends an interrupt signal on one of
the interrupt pins.
◦ The microprocessor checks the validity of the interrupt request by
checking whether
 The interrupt system is enabled.
 The particular interrupt is not disabled.
 Any higher priority interrupt is not pending or being processed.
 If an interrupt request is valid, the microprocessor
 Completes the current instruction execution.
 Saves the Status Register and Program Counter (PC) in stack.
 Issues the interrupt acknowledgement signal.
 Determines the address of the interrupt servicing routine and
stores the starting address in PC. The program thus branches to
Interrupt Servicing Routine.
Direct memory access
 Followingis the operation sequence in case of
Direct Memory Access.
◦ The microprocessor checks for DMA request signal once
in each machine cycle.
◦ The I/0 device sends the signal on DMA Request pin.
◦ The microprocessor tristates the address, data and control
buses.
◦ The microprocessor sends the acknowledgement signal to
the I/O device on DMA Acknowledgement pin.
◦ The I/O device uses the bus system to perform the data
transfer operation on memory.
◦ On completion of data transfer, the I/O device withdraws
the DMA request signal.
◦ The microprocessor continuously checks the DMA request
signal. When the signal is withdrawn, the microprocessor
regains the control of buses and resumes normal operation.
Serial Data Transfer
The data is transferred bit by bit on a single
line. This minimizes the number of
interconnecting wires.
Timing diagram of 8085 processor
Timing Diagram:
 Timing Diagram is a graphical representation. It represents the
execution time taken by each instruction in a graphical format.
The execution time is represented in T-states.
Instruction Cycle:
 The time required to execute an instruction
Machine Cycle:
 The time required to access the memory or input/output devices
T-State:
 The machine cycle and instruction cycle takes multiple clock
periods.
 A portion of an operation carried out in one system clock period
is called as T-state.
MACHINE CYCLES OF 8085:

The 8085 microprocessor has 5 (seven)

basic machine cycles. They are
1. Opcode fetch cycle (4T)
2. Memory read cycle (3 T)
3. Memory write cycle (3 T)
4. I/O read cycle (3 T)
5. I/O write cycle (3 T)
Opcode fetch machine cycle of 8085
 The opcodes are stored in memory. So, the processor executes
the opcode fetch machine cycle to fetch the opcode from
memory.
 Hence, every instruction starts with opcode fetch machine
cycle.
 The time taken by the processor to execute the opcode fetch
cycle is 4T.
 In this time, the first, 3 T-states are used for fetching the opcode
from memory and the remaining T-states are used for internal
operations by the processor.
Memory read machine cycle of 8085 :
 

 The memory read machine cycle is executed by the processor

to read a data byte from memory.
 The processor takes 3T states to execute this cycle.
 The instructions which have more than one byte word size
will use the machine cycle after the opcode fetch machine
cycle.
Memory write machine cycle of 8085:
 The 8085 executes the memory write cycle to store the
data into data memory or stack memory. The length of this
machine cycle is 3T states (TI - T3).
 In this machine cycle, processor places the address on the
address lines from the stack pointer or general purpose
register pair and through the write process, stores the data
into the addressed memory location.
I/O read cycle of 8085:
I/O write cycle of 8085:
The I/O write machine cycle is executed by the
processor to write a data byte in the I/O port or
to a peripheral, which is I/O, mapped in the
system.
The processor takes 3T states to execute this
machine cycle.
Interrupt structure of 8085 processor
Interrupt is signals send by an external device to the
processor, to request the processor to perform a
particular task or work.
The interrupts are used for data transfer between the
peripheral and the microprocessor.
The processor will check the interrupts always at the
2nd T-state of last machine cycle.
If there is any interrupt it accept the interrupt and
send the INTA (active low) signal to the peripheral.
Types of Interrupts: It supports two types of
interrupts.
Hardware
Software
Hardware interrupts:
An external device initiates the hardware
interrupts and placing an appropriate signal
at the interrupt pin of the processor.
If the interrupt is accepted then the
processor executes an interrupt service
routine.
TRAP:
 It is a non-maskable interrupt. It is unaffected by any
mask or interrupt enable.
 TRAP bas the highest priority and vectored interrupt.
 TRAP interrupt is edge and level triggered. This
means hat the TRAP must go high and remain high
until it is acknowledged.
 In sudden power failure, it executes a ISR and send
the data from main memory to backup memory.
 There are two ways to clear TRAP interrupt.
 By resetting microprocessor (External signal)
 By giving a high TRAP ACKNOWLEDGE (Internal
signal)
RST 7.5, RST 6.5 and 5.5:
 RST 7.5, RST 6.5 and 5.5 are Maskable interrupts. vectored
interrupts.
 RST 7.5 has the second highest priority.
 The RST 6.5 has the third priority whereas RST 5.5 has the
fourth priority.
 RST 7.5 is edge sensitive. ie. Input goes to high and no need to
maintain high state until it recognized.
 The RST 6.5 and RST 5.5 both are level triggered. .ie. Input goes
to high and stay high until it recognized.
 These are disabled by,
◦ DI, SIM instruction
◦ System or processor reset.
◦ After reorganization of interrupt.
 These are Enabled by EI instruction.
 
INTR:
Maskable interrupt. It has lowest priority.
Non- vectored interrupt. After receiving
INTA (active low) signal, it has to supply
the address of ISR.
It is a level sensitive interrupts. ie. Input
goes to high and it is necessary to maintain
high state until it recognized.
SIM and RIM for interrupts:

SIM instruction
The 8085 provide additional masking facility
for RST 7.5, RST 6.5 and RST 5.5 using SIM
instruction.
The status of these interrupts can be read by
executing RIM instruction.
RIM instruction
The status of pending interrupts can be read
from accumulator after executing RIM
instruction. When RIM instruction is
executed an 8-bit data is loaded in
accumulator
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