Intel 8253/8254 –

Programmable Interval Timer

• It is always possible to generate accurate time delays using the microprocessor
system by using software loop programs. But that will waste the precious time of
CPU.
• INTEL introduced the chips 8253/8254 which is a hardware solution for the
problem of generating accurate time delays.
• Programmable interval timer/counter
• Has six modes of operation
• It has three independent 16-bit down counters.
• Operation
- A 16 bit count is loaded on the counter and on command it starts decrement
- When the count reaches zero it generates a pulse
Features of 8253 / 54
• It can handle inputs from DC to 10 MHz.
• 3 counters can be programmed for either binary or BCD count.
• To operate a counter, a 16-bit count is loaded in its register on
command, it begins to decrement the count until it reaches 0. At the
end of the count, it generates a pulse that can be used to interrupt the
CPU.
• It is compatible with almost all microprocessors.
• 8254 has a powerful command called READ BACK command, which
allows the user to check the count value, the programmed mode, the
current mode, and the current status of the counter.
ARCHITECTURE
Data Bus Buffer
• It is a tri-state, bi-directional, 8-bit buffer, which is used to interface
the 8253/54 to the system data bus. It has three basic functions −
• Programming the modes of 8253/54.
• Loading the count registers.
• Reading the count values.
Read/Write Logic
• It includes 5 signals, i.e. RD, WR, CS, and the address lines A 0 &
A1 .
• In the peripheral I/O mode, the RD and WR signals are connected A1 A0 Result
to IOR and IOW, respectively. In the memory-mapped I/O mode, 0 0 Counter 0
these are connected to MEMR and MEMW. 0 1 Counter 1
• Address lines A0 & A1 of the CPU are connected to lines A0 and 1 0 Counter 2
A1 of the 8253/54, and CS is tied to a decoded address. 1 1 Control Word
Register
• The control word register and counters are selected according to
X X No Selection
the signals on lines A0 & A1.
Control Word Register
• This register is accessed when lines A0 & A1 are at logic 1.
• It is used to write a command word, which specifies the counter to be used,
its mode, and either a read or write operation. Following table shows the
result for various control inputs.
A1 A0 RD WR CS Result
0 0 1 0 0 Write Counter 0
0 1 1 0 0 Write Counter 1
1 0 1 0 0 Write Counter 2
1 1 1 0 0 Write Control Word
0 0 0 1 0 Read Counter 0
0 1 0 1 0 Read Counter 1
1 0 0 1 0 Read Counter 2
1 1 0 1 0 No operation
X X 1 1 0 No operation
X X X X 1 No operation
Counters
• Each counter consists of a single, 16 bit-down counter, which can be operated
in either binary or BCD.
• Its input and output is configured by the selection of modes stored in the
control word register.
• The programmer can read the contents of any of the three counters without
disturbing the actual count in process.
• Counters are programmed by writing a Control Word and then an initial count.
• GATE=1 enables counting, GATE=0 disables counting.
Counter Latch Command
• It is written to the Control Word Register like a Control Word, but
two bits (D5,D4) distinguish this command from a Control Word.
• The selected Counter latches the count at the time the Counter
Latch Command is received.
• The count is held in the latch until it is read by the CPU.
Read-Back Command (Available only for 8254)
• This command allows the user to check the count value,
programmed Mode, and current states of the OUT pin, etc...
Intel 8253/54 - Operational Modes
Mode 0 ─ Interrupt on Terminal Count
• It is used to generate an interrupt to the microprocessor after a certain interval.
• Initially the output is low after the mode is set. The output remains LOW after
the count value is loaded into the counter.
• The process of decrementing the counter continues till the terminal count is
reached, i.e., the count become zero and the output goes HIGH and will
remain high until it reloads a new count.
• The GATE signal is high for normal counting. When GATE goes low, counting
is terminated and the current count is latched till the GATE goes high again.
Mode 1 – Programmable One Shot
• It can be used as a mono stable multi-vibrator.
• The gate input is used as a trigger input in this mode.
• The output remains high until the count is loaded and a trigger is applied.
• In Mode 1, after sending the 0-to-1 pulse to GATE, OUT becomes low and
stays low for a duration of count, then becomes high and stays high until the
GATE is triggered again
Mode 2 – Rate Generator
• The output is normally high after initialization.
• After loading the counter and triggering(gate=1) it, the output will be high till
the last one period (i.e. The output will be high for (N-1) clock pulses and
then it will go low for one cycle of input clock and then return HIGH and the
count value is automatically reloaded into the counter
• If the gate is low, the output will be HIGH and no counting will be performed.
Mode 3 – Square Wave Generator
• This mode is similar to Mode 2 except the output remains low for half of the timer
period and high for the other half of the period.
• This is accomplished internally by decrementing the counter by two on the falling
edge of each pulse
• When the count N loaded is EVEN, then for half of the count, the output remains
high and for the remaining half it remains low.
• If the loaded count value N is ODD, then for (N+1)/2 pulses the output remains
high & for (N-1)/2 pulses it remains low
Mode 4 − Software Triggered Mode
• In this mode, the output will remain high until the timer has counted to zero, at which point
the output will pulse low and then go high again.
• The count is latched when the GATE signal goes LOW.
• On the terminal count, the output goes low for one clock cycle then goes HIGH. This low
pulse can be used as a strobe.
• Here, the counter is not reloaded automatically. To repeat the strobe, the count must be
reloaded
• This is called software triggered strobe as the count down is initiated by a program
Mode 5 – Hardware Triggered Mode
• This mode generates a strobe in response to an externally generated signal.
• This mode is similar to mode 4 except that the counting is initiated by a signal at
the gate input, which means it is hardware triggered instead of software triggered.
• After it is initialized, the output goes high.
• When the terminal count is reached, the output goes low for one clock cycle.